Revision 4ad40f36 target-mips/cpu.h
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#if !defined (__MIPS_CPU_H__) |
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#define __MIPS_CPU_H__ |
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#define TARGET_HAS_ICE 1 |
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#include "mips-defs.h" |
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#include "cpu-defs.h" |
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#include "config.h" |
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struct tlb_t {
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target_ulong VPN; |
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target_ulong end; |
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target_ulong end2; |
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uint8_t ASID; |
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uint8_t G; |
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uint8_t C[2]; |
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#define MIPS_HFLAG_DM 0x0008 /* Debug mode */ |
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#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */ |
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#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */ |
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#define MIPS_HFLAG_DS 0x0080 /* In / out of delay slot */
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/* Those flags keep the branch state if the translation is interrupted
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* between the branch instruction and the delay slot
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*/ |
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#define MIPS_HFLAG_BMASK 0x0F00
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#define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
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#define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
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#define MIPS_HFLAG_BL 0x0400 /* Likely branch */
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#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
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/* If translation is interrupted between the branch instruction and
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* the delay slot, record what type of branch it is so that we can
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* resume translation properly. It might be possible to reduce
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* this from three bits to two. */
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#define MIPS_HFLAG_BMASK 0x0380
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#define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
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#define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
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#define MIPS_HFLAG_BL 0x0180 /* Likely branch */
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#define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
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target_ulong btarget; /* Jump / branch target */ |
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int bcond; /* Branch condition (if needed) */ |
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int halted; /* TRUE if the CPU is in suspend state */ |
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CPU_COMMON |
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}; |
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EXCP_IBE, |
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EXCP_DBp, |
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EXCP_SYSCALL, |
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EXCP_BREAK, |
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EXCP_CpU, /* 16 */
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EXCP_BREAK, /* 16 */
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EXCP_CpU, |
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EXCP_RI, |
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EXCP_OVERFLOW, |
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EXCP_TRAP, |
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EXCP_DDBS, |
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EXCP_DWATCH, |
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EXCP_LAE, /* 22 */
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EXCP_SAE, |
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EXCP_LAE, |
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EXCP_SAE, /* 24 */
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EXCP_LTLBL, |
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EXCP_TLBL, |
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EXCP_TLBS, |
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