Revision 4ad40f36 target-mips/helper.c
| b/target-mips/helper.c | ||
|---|---|---|
| 46 | 46 |
tlb = &env->tlb[i]; |
| 47 | 47 |
/* Check ASID, virtual page number & size */ |
| 48 | 48 |
if ((tlb->G == 1 || tlb->ASID == ASID) && |
| 49 |
tlb->VPN == tag && address < tlb->end) {
|
|
| 49 |
tlb->VPN == tag && address < tlb->end2) {
|
|
| 50 | 50 |
/* TLB match */ |
| 51 | 51 |
n = (address >> 12) & 1; |
| 52 | 52 |
/* Check access rights */ |
| ... | ... | |
| 167 | 167 |
int ret = 0; |
| 168 | 168 |
|
| 169 | 169 |
if (logfile) {
|
| 170 |
#if 0 |
|
| 170 | 171 |
cpu_dump_state(env, logfile, fprintf, 0); |
| 172 |
#endif |
|
| 171 | 173 |
fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n", |
| 172 | 174 |
__func__, env->PC, address, rw, is_user, is_softmmu); |
| 173 | 175 |
} |
| 176 |
|
|
| 177 |
rw &= 1; |
|
| 178 |
|
|
| 174 | 179 |
/* data access */ |
| 175 | 180 |
/* XXX: put correct access by using cpu_restore_state() |
| 176 | 181 |
correctly */ |
| ... | ... | |
| 226 | 231 |
/* Raise exception */ |
| 227 | 232 |
env->CP0_BadVAddr = address; |
| 228 | 233 |
env->CP0_Context = (env->CP0_Context & 0xff800000) | |
| 229 |
((address >> 8) & 0x007ffff0);
|
|
| 234 |
((address >> 9) & 0x007ffff0);
|
|
| 230 | 235 |
env->CP0_EntryHi = |
| 231 | 236 |
(env->CP0_EntryHi & 0x000000FF) | (address & 0xFFFFF000); |
| 232 | 237 |
env->exception_index = exception; |
| ... | ... | |
| 276 | 281 |
env->CP0_Debug |= 1 << CP0DB_DDBL; |
| 277 | 282 |
goto set_DEPC; |
| 278 | 283 |
set_DEPC: |
| 279 |
if (env->hflags & MIPS_HFLAG_DS) {
|
|
| 284 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
| 280 | 285 |
/* If the exception was raised from a delay slot, |
| 281 | 286 |
* come back to the jump |
| 282 | 287 |
*/ |
| 283 | 288 |
env->CP0_DEPC = env->PC - 4; |
| 289 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
|
| 284 | 290 |
} else {
|
| 285 | 291 |
env->CP0_DEPC = env->PC; |
| 286 | 292 |
} |
| ... | ... | |
| 316 | 322 |
env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) | |
| 317 | 323 |
(1 << CP0St_NMI); |
| 318 | 324 |
set_error_EPC: |
| 319 |
env->hflags = MIPS_HFLAG_ERL; |
|
| 320 |
if (env->hflags & MIPS_HFLAG_DS) {
|
|
| 325 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
| 321 | 326 |
/* If the exception was raised from a delay slot, |
| 322 | 327 |
* come back to the jump |
| 323 | 328 |
*/ |
| ... | ... | |
| 325 | 330 |
} else {
|
| 326 | 331 |
env->CP0_ErrorEPC = env->PC; |
| 327 | 332 |
} |
| 333 |
env->hflags = MIPS_HFLAG_ERL; |
|
| 328 | 334 |
pc = 0xBFC00000; |
| 329 | 335 |
break; |
| 330 | 336 |
case EXCP_MCHECK: |
| ... | ... | |
| 366 | 372 |
goto set_EPC; |
| 367 | 373 |
case EXCP_CpU: |
| 368 | 374 |
cause = 11; |
| 369 |
/* XXX: fill in the faulty unit number */
|
|
| 375 |
env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
|
|
| 370 | 376 |
goto set_EPC; |
| 371 | 377 |
case EXCP_OVERFLOW: |
| 372 | 378 |
cause = 12; |
| ... | ... | |
| 391 | 397 |
env->hflags |= MIPS_HFLAG_EXL; |
| 392 | 398 |
pc += offset; |
| 393 | 399 |
env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2); |
| 394 |
if (env->hflags & MIPS_HFLAG_DS) {
|
|
| 400 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
| 395 | 401 |
/* If the exception was raised from a delay slot, |
| 396 | 402 |
* come back to the jump |
| 397 | 403 |
*/ |
| 398 | 404 |
env->CP0_EPC = env->PC - 4; |
| 399 | 405 |
env->CP0_Cause |= 0x80000000; |
| 406 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
|
| 400 | 407 |
} else {
|
| 401 | 408 |
env->CP0_EPC = env->PC; |
| 402 | 409 |
env->CP0_Cause &= ~0x80000000; |
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