Revision 4b48bf05
| b/hw/eccmemctl.c | ||
|---|---|---|
| 335 | 335 |
ecc_reset(s); |
| 336 | 336 |
} |
| 337 | 337 |
|
| 338 |
void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
|
| 339 |
{
|
|
| 340 |
DeviceState *dev; |
|
| 341 |
SysBusDevice *s; |
|
| 342 |
|
|
| 343 |
dev = qdev_create(NULL, "eccmemctl"); |
|
| 344 |
qdev_prop_set_uint32(dev, "version", version); |
|
| 345 |
qdev_init(dev); |
|
| 346 |
s = sysbus_from_qdev(dev); |
|
| 347 |
sysbus_connect_irq(s, 0, irq); |
|
| 348 |
sysbus_mmio_map(s, 0, base); |
|
| 349 |
if (version == ECC_MCC) { // SS-600MP only
|
|
| 350 |
sysbus_mmio_map(s, 1, base + 0x1000); |
|
| 351 |
} |
|
| 352 |
} |
|
| 353 |
|
|
| 354 | 338 |
static SysBusDeviceInfo ecc_info = {
|
| 355 | 339 |
.init = ecc_init1, |
| 356 | 340 |
.qdev.name = "eccmemctl", |
| b/hw/iommu.c | ||
|---|---|---|
| 366 | 366 |
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
| 367 | 367 |
} |
| 368 | 368 |
|
| 369 |
void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
|
| 370 |
{
|
|
| 371 |
DeviceState *dev; |
|
| 372 |
SysBusDevice *s; |
|
| 373 |
IOMMUState *d; |
|
| 374 |
|
|
| 375 |
dev = qdev_create(NULL, "iommu"); |
|
| 376 |
qdev_prop_set_uint32(dev, "version", version); |
|
| 377 |
qdev_init(dev); |
|
| 378 |
s = sysbus_from_qdev(dev); |
|
| 379 |
sysbus_connect_irq(s, 0, irq); |
|
| 380 |
sysbus_mmio_map(s, 0, addr); |
|
| 381 |
|
|
| 382 |
d = FROM_SYSBUS(IOMMUState, s); |
|
| 383 |
|
|
| 384 |
return d; |
|
| 385 |
} |
|
| 386 |
|
|
| 387 | 369 |
static void iommu_init1(SysBusDevice *dev) |
| 388 | 370 |
{
|
| 389 | 371 |
IOMMUState *s = FROM_SYSBUS(IOMMUState, dev); |
| b/hw/sbi.c | ||
|---|---|---|
| 131 | 131 |
} |
| 132 | 132 |
} |
| 133 | 133 |
|
| 134 |
DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq) |
|
| 135 |
{
|
|
| 136 |
DeviceState *dev; |
|
| 137 |
SysBusDevice *s; |
|
| 138 |
unsigned int i; |
|
| 139 |
|
|
| 140 |
dev = qdev_create(NULL, "sbi"); |
|
| 141 |
qdev_init(dev); |
|
| 142 |
|
|
| 143 |
s = sysbus_from_qdev(dev); |
|
| 144 |
|
|
| 145 |
for (i = 0; i < MAX_CPUS; i++) {
|
|
| 146 |
sysbus_connect_irq(s, i, *parent_irq[i]); |
|
| 147 |
} |
|
| 148 |
|
|
| 149 |
sysbus_mmio_map(s, 0, addr); |
|
| 150 |
|
|
| 151 |
return dev; |
|
| 152 |
} |
|
| 153 |
|
|
| 154 | 134 |
static void sbi_init1(SysBusDevice *dev) |
| 155 | 135 |
{
|
| 156 | 136 |
SBIState *s = FROM_SYSBUS(SBIState, dev); |
| b/hw/slavio_intctl.c | ||
|---|---|---|
| 416 | 416 |
slavio_intctl_reset(s); |
| 417 | 417 |
} |
| 418 | 418 |
|
| 419 |
DeviceState *slavio_intctl_init(target_phys_addr_t addr, |
|
| 420 |
target_phys_addr_t addrg, |
|
| 421 |
const uint32_t *intbit_to_level, |
|
| 422 |
qemu_irq **parent_irq, unsigned int cputimer) |
|
| 423 |
{
|
|
| 424 |
DeviceState *dev; |
|
| 425 |
SysBusDevice *s; |
|
| 426 |
unsigned int i, j; |
|
| 427 |
|
|
| 428 |
dev = qdev_create(NULL, "slavio_intctl"); |
|
| 429 |
qdev_prop_set_ptr(dev, "intbit_to_level", (void *)intbit_to_level); |
|
| 430 |
qdev_prop_set_uint32(dev, "cputimer_bit", cputimer); |
|
| 431 |
qdev_init(dev); |
|
| 432 |
|
|
| 433 |
s = sysbus_from_qdev(dev); |
|
| 434 |
|
|
| 435 |
for (i = 0; i < MAX_CPUS; i++) {
|
|
| 436 |
for (j = 0; j < MAX_PILS; j++) {
|
|
| 437 |
sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
|
| 438 |
} |
|
| 439 |
} |
|
| 440 |
sysbus_mmio_map(s, 0, addrg); |
|
| 441 |
for (i = 0; i < MAX_CPUS; i++) {
|
|
| 442 |
sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); |
|
| 443 |
} |
|
| 444 |
|
|
| 445 |
return dev; |
|
| 446 |
} |
|
| 447 |
|
|
| 448 | 419 |
static SysBusDeviceInfo slavio_intctl_info = {
|
| 449 | 420 |
.init = slavio_intctl_init1, |
| 450 | 421 |
.qdev.name = "slavio_intctl", |
| b/hw/slavio_misc.c | ||
|---|---|---|
| 63 | 63 |
#define MISC_SIZE 1 |
| 64 | 64 |
#define SYSCTRL_SIZE 4 |
| 65 | 65 |
|
| 66 |
#define MISC_LEDS 0x01600000 |
|
| 67 |
#define MISC_CFG 0x01800000 |
|
| 68 |
#define MISC_DIAG 0x01a00000 |
|
| 69 |
#define MISC_MDM 0x01b00000 |
|
| 70 |
#define MISC_SYS 0x01f00000 |
|
| 71 |
|
|
| 72 | 66 |
#define AUX1_TC 0x02 |
| 73 | 67 |
|
| 74 | 68 |
#define AUX2_PWROFF 0x01 |
| ... | ... | |
| 440 | 434 |
return 0; |
| 441 | 435 |
} |
| 442 | 436 |
|
| 443 |
void *slavio_misc_init(target_phys_addr_t base, |
|
| 444 |
target_phys_addr_t aux1_base, |
|
| 445 |
target_phys_addr_t aux2_base, qemu_irq irq, |
|
| 446 |
qemu_irq fdc_tc) |
|
| 447 |
{
|
|
| 448 |
DeviceState *dev; |
|
| 449 |
SysBusDevice *s; |
|
| 450 |
MiscState *d; |
|
| 451 |
|
|
| 452 |
dev = qdev_create(NULL, "slavio_misc"); |
|
| 453 |
qdev_init(dev); |
|
| 454 |
s = sysbus_from_qdev(dev); |
|
| 455 |
if (base) {
|
|
| 456 |
/* 8 bit registers */ |
|
| 457 |
/* Slavio control */ |
|
| 458 |
sysbus_mmio_map(s, 0, base + MISC_CFG); |
|
| 459 |
/* Diagnostics */ |
|
| 460 |
sysbus_mmio_map(s, 1, base + MISC_DIAG); |
|
| 461 |
/* Modem control */ |
|
| 462 |
sysbus_mmio_map(s, 2, base + MISC_MDM); |
|
| 463 |
/* 16 bit registers */ |
|
| 464 |
/* ss600mp diag LEDs */ |
|
| 465 |
sysbus_mmio_map(s, 3, base + MISC_LEDS); |
|
| 466 |
/* 32 bit registers */ |
|
| 467 |
/* System control */ |
|
| 468 |
sysbus_mmio_map(s, 4, base + MISC_SYS); |
|
| 469 |
} |
|
| 470 |
if (aux1_base) {
|
|
| 471 |
/* AUX 1 (Misc System Functions) */ |
|
| 472 |
sysbus_mmio_map(s, 5, aux1_base); |
|
| 473 |
} |
|
| 474 |
if (aux2_base) {
|
|
| 475 |
/* AUX 2 (Software Powerdown Control) */ |
|
| 476 |
sysbus_mmio_map(s, 6, aux2_base); |
|
| 477 |
} |
|
| 478 |
sysbus_connect_irq(s, 0, irq); |
|
| 479 |
sysbus_connect_irq(s, 1, fdc_tc); |
|
| 480 |
|
|
| 481 |
d = FROM_SYSBUS(MiscState, s); |
|
| 482 |
|
|
| 483 |
return d; |
|
| 484 |
} |
|
| 485 |
|
|
| 486 | 437 |
static void apc_init1(SysBusDevice *dev) |
| 487 | 438 |
{
|
| 488 | 439 |
APCState *s = FROM_SYSBUS(APCState, dev); |
| ... | ... | |
| 495 | 446 |
sysbus_init_mmio(dev, MISC_SIZE, io); |
| 496 | 447 |
} |
| 497 | 448 |
|
| 498 |
void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
|
| 499 |
{
|
|
| 500 |
DeviceState *dev; |
|
| 501 |
SysBusDevice *s; |
|
| 502 |
|
|
| 503 |
dev = qdev_create(NULL, "apc"); |
|
| 504 |
qdev_init(dev); |
|
| 505 |
s = sysbus_from_qdev(dev); |
|
| 506 |
/* Power management (APC) XXX: not a Slavio device */ |
|
| 507 |
sysbus_mmio_map(s, 0, power_base); |
|
| 508 |
sysbus_connect_irq(s, 0, cpu_halt); |
|
| 509 |
} |
|
| 510 |
|
|
| 511 | 449 |
static void slavio_misc_init1(SysBusDevice *dev) |
| 512 | 450 |
{
|
| 513 | 451 |
MiscState *s = FROM_SYSBUS(MiscState, dev); |
| b/hw/slavio_timer.c | ||
|---|---|---|
| 76 | 76 |
#define SYS_TIMER_SIZE 0x14 |
| 77 | 77 |
#define CPU_TIMER_SIZE 0x10 |
| 78 | 78 |
|
| 79 |
#define SYS_TIMER_OFFSET 0x10000ULL |
|
| 80 |
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
|
| 81 |
|
|
| 82 | 79 |
#define TIMER_LIMIT 0 |
| 83 | 80 |
#define TIMER_COUNTER 1 |
| 84 | 81 |
#define TIMER_COUNTER_NORST 2 |
| ... | ... | |
| 415 | 412 |
s->cputimer_mode = 0; |
| 416 | 413 |
} |
| 417 | 414 |
|
| 418 |
void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
|
| 419 |
qemu_irq *cpu_irqs, unsigned int num_cpus) |
|
| 420 |
{
|
|
| 421 |
DeviceState *dev; |
|
| 422 |
SysBusDevice *s; |
|
| 423 |
unsigned int i; |
|
| 424 |
|
|
| 425 |
dev = qdev_create(NULL, "slavio_timer"); |
|
| 426 |
qdev_prop_set_uint32(dev, "num_cpus", num_cpus); |
|
| 427 |
qdev_init(dev); |
|
| 428 |
s = sysbus_from_qdev(dev); |
|
| 429 |
sysbus_connect_irq(s, 0, master_irq); |
|
| 430 |
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); |
|
| 431 |
|
|
| 432 |
for (i = 0; i < MAX_CPUS; i++) {
|
|
| 433 |
sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i)); |
|
| 434 |
sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
|
| 435 |
} |
|
| 436 |
} |
|
| 437 |
|
|
| 438 | 415 |
static void slavio_timer_init1(SysBusDevice *dev) |
| 439 | 416 |
{
|
| 440 | 417 |
int io; |
| b/hw/sun4c_intctl.c | ||
|---|---|---|
| 198 | 198 |
s->pending = 0; |
| 199 | 199 |
} |
| 200 | 200 |
|
| 201 |
DeviceState *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq *parent_irq) |
|
| 202 |
{
|
|
| 203 |
DeviceState *dev; |
|
| 204 |
SysBusDevice *s; |
|
| 205 |
unsigned int i; |
|
| 206 |
|
|
| 207 |
dev = qdev_create(NULL, "sun4c_intctl"); |
|
| 208 |
qdev_init(dev); |
|
| 209 |
|
|
| 210 |
s = sysbus_from_qdev(dev); |
|
| 211 |
|
|
| 212 |
for (i = 0; i < MAX_PILS; i++) {
|
|
| 213 |
sysbus_connect_irq(s, i, parent_irq[i]); |
|
| 214 |
} |
|
| 215 |
sysbus_mmio_map(s, 0, addr); |
|
| 216 |
|
|
| 217 |
return dev; |
|
| 218 |
} |
|
| 219 |
|
|
| 220 | 201 |
static void sun4c_intctl_init1(SysBusDevice *dev) |
| 221 | 202 |
{
|
| 222 | 203 |
Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev); |
| b/hw/sun4m.c | ||
|---|---|---|
| 36 | 36 |
#include "isa.h" |
| 37 | 37 |
#include "fw_cfg.h" |
| 38 | 38 |
#include "escc.h" |
| 39 |
#include "qdev-addr.h" |
|
| 39 | 40 |
|
| 40 | 41 |
//#define DEBUG_IRQ |
| 41 | 42 |
|
| ... | ... | |
| 364 | 365 |
return kernel_size; |
| 365 | 366 |
} |
| 366 | 367 |
|
| 368 |
static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
|
| 369 |
{
|
|
| 370 |
DeviceState *dev; |
|
| 371 |
SysBusDevice *s; |
|
| 372 |
|
|
| 373 |
dev = qdev_create(NULL, "iommu"); |
|
| 374 |
qdev_prop_set_uint32(dev, "version", version); |
|
| 375 |
qdev_init(dev); |
|
| 376 |
s = sysbus_from_qdev(dev); |
|
| 377 |
sysbus_connect_irq(s, 0, irq); |
|
| 378 |
sysbus_mmio_map(s, 0, addr); |
|
| 379 |
|
|
| 380 |
return s; |
|
| 381 |
} |
|
| 382 |
|
|
| 367 | 383 |
static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
| 368 | 384 |
void *dma_opaque, qemu_irq irq, qemu_irq *reset) |
| 369 | 385 |
{
|
| ... | ... | |
| 382 | 398 |
*reset = qdev_get_gpio_in(dev, 0); |
| 383 | 399 |
} |
| 384 | 400 |
|
| 401 |
static DeviceState *slavio_intctl_init(target_phys_addr_t addr, |
|
| 402 |
target_phys_addr_t addrg, |
|
| 403 |
const uint32_t *intbit_to_level, |
|
| 404 |
qemu_irq **parent_irq, |
|
| 405 |
unsigned int cputimer) |
|
| 406 |
{
|
|
| 407 |
DeviceState *dev; |
|
| 408 |
SysBusDevice *s; |
|
| 409 |
unsigned int i, j; |
|
| 410 |
|
|
| 411 |
dev = qdev_create(NULL, "slavio_intctl"); |
|
| 412 |
qdev_prop_set_ptr(dev, "intbit_to_level", (void *)intbit_to_level); |
|
| 413 |
qdev_prop_set_uint32(dev, "cputimer_bit", cputimer); |
|
| 414 |
qdev_init(dev); |
|
| 415 |
|
|
| 416 |
s = sysbus_from_qdev(dev); |
|
| 417 |
|
|
| 418 |
for (i = 0; i < MAX_CPUS; i++) {
|
|
| 419 |
for (j = 0; j < MAX_PILS; j++) {
|
|
| 420 |
sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
|
| 421 |
} |
|
| 422 |
} |
|
| 423 |
sysbus_mmio_map(s, 0, addrg); |
|
| 424 |
for (i = 0; i < MAX_CPUS; i++) {
|
|
| 425 |
sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); |
|
| 426 |
} |
|
| 427 |
|
|
| 428 |
return dev; |
|
| 429 |
} |
|
| 430 |
|
|
| 431 |
#define SYS_TIMER_OFFSET 0x10000ULL |
|
| 432 |
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
|
| 433 |
|
|
| 434 |
static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
|
| 435 |
qemu_irq *cpu_irqs, unsigned int num_cpus) |
|
| 436 |
{
|
|
| 437 |
DeviceState *dev; |
|
| 438 |
SysBusDevice *s; |
|
| 439 |
unsigned int i; |
|
| 440 |
|
|
| 441 |
dev = qdev_create(NULL, "slavio_timer"); |
|
| 442 |
qdev_prop_set_uint32(dev, "num_cpus", num_cpus); |
|
| 443 |
qdev_init(dev); |
|
| 444 |
s = sysbus_from_qdev(dev); |
|
| 445 |
sysbus_connect_irq(s, 0, master_irq); |
|
| 446 |
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); |
|
| 447 |
|
|
| 448 |
for (i = 0; i < MAX_CPUS; i++) {
|
|
| 449 |
sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i)); |
|
| 450 |
sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
|
| 451 |
} |
|
| 452 |
} |
|
| 453 |
|
|
| 454 |
#define MISC_LEDS 0x01600000 |
|
| 455 |
#define MISC_CFG 0x01800000 |
|
| 456 |
#define MISC_DIAG 0x01a00000 |
|
| 457 |
#define MISC_MDM 0x01b00000 |
|
| 458 |
#define MISC_SYS 0x01f00000 |
|
| 459 |
|
|
| 460 |
static void *slavio_misc_init(target_phys_addr_t base, |
|
| 461 |
target_phys_addr_t aux1_base, |
|
| 462 |
target_phys_addr_t aux2_base, qemu_irq irq, |
|
| 463 |
qemu_irq fdc_tc) |
|
| 464 |
{
|
|
| 465 |
DeviceState *dev; |
|
| 466 |
SysBusDevice *s; |
|
| 467 |
|
|
| 468 |
dev = qdev_create(NULL, "slavio_misc"); |
|
| 469 |
qdev_init(dev); |
|
| 470 |
s = sysbus_from_qdev(dev); |
|
| 471 |
if (base) {
|
|
| 472 |
/* 8 bit registers */ |
|
| 473 |
/* Slavio control */ |
|
| 474 |
sysbus_mmio_map(s, 0, base + MISC_CFG); |
|
| 475 |
/* Diagnostics */ |
|
| 476 |
sysbus_mmio_map(s, 1, base + MISC_DIAG); |
|
| 477 |
/* Modem control */ |
|
| 478 |
sysbus_mmio_map(s, 2, base + MISC_MDM); |
|
| 479 |
/* 16 bit registers */ |
|
| 480 |
/* ss600mp diag LEDs */ |
|
| 481 |
sysbus_mmio_map(s, 3, base + MISC_LEDS); |
|
| 482 |
/* 32 bit registers */ |
|
| 483 |
/* System control */ |
|
| 484 |
sysbus_mmio_map(s, 4, base + MISC_SYS); |
|
| 485 |
} |
|
| 486 |
if (aux1_base) {
|
|
| 487 |
/* AUX 1 (Misc System Functions) */ |
|
| 488 |
sysbus_mmio_map(s, 5, aux1_base); |
|
| 489 |
} |
|
| 490 |
if (aux2_base) {
|
|
| 491 |
/* AUX 2 (Software Powerdown Control) */ |
|
| 492 |
sysbus_mmio_map(s, 6, aux2_base); |
|
| 493 |
} |
|
| 494 |
sysbus_connect_irq(s, 0, irq); |
|
| 495 |
sysbus_connect_irq(s, 1, fdc_tc); |
|
| 496 |
|
|
| 497 |
return s; |
|
| 498 |
} |
|
| 499 |
|
|
| 500 |
static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
|
| 501 |
{
|
|
| 502 |
DeviceState *dev; |
|
| 503 |
SysBusDevice *s; |
|
| 504 |
|
|
| 505 |
dev = qdev_create(NULL, "eccmemctl"); |
|
| 506 |
qdev_prop_set_uint32(dev, "version", version); |
|
| 507 |
qdev_init(dev); |
|
| 508 |
s = sysbus_from_qdev(dev); |
|
| 509 |
sysbus_connect_irq(s, 0, irq); |
|
| 510 |
sysbus_mmio_map(s, 0, base); |
|
| 511 |
if (version == 0) { // SS-600MP only
|
|
| 512 |
sysbus_mmio_map(s, 1, base + 0x1000); |
|
| 513 |
} |
|
| 514 |
} |
|
| 515 |
|
|
| 516 |
static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
|
| 517 |
{
|
|
| 518 |
DeviceState *dev; |
|
| 519 |
SysBusDevice *s; |
|
| 520 |
|
|
| 521 |
dev = qdev_create(NULL, "apc"); |
|
| 522 |
qdev_init(dev); |
|
| 523 |
s = sysbus_from_qdev(dev); |
|
| 524 |
/* Power management (APC) XXX: not a Slavio device */ |
|
| 525 |
sysbus_mmio_map(s, 0, power_base); |
|
| 526 |
sysbus_connect_irq(s, 0, cpu_halt); |
|
| 527 |
} |
|
| 528 |
|
|
| 529 |
static void tcx_init(target_phys_addr_t addr, int vram_size, int width, |
|
| 530 |
int height, int depth) |
|
| 531 |
{
|
|
| 532 |
DeviceState *dev; |
|
| 533 |
SysBusDevice *s; |
|
| 534 |
|
|
| 535 |
dev = qdev_create(NULL, "SUNW,tcx"); |
|
| 536 |
qdev_prop_set_taddr(dev, "addr", addr); |
|
| 537 |
qdev_prop_set_uint32(dev, "vram_size", vram_size); |
|
| 538 |
qdev_prop_set_uint16(dev, "width", width); |
|
| 539 |
qdev_prop_set_uint16(dev, "height", height); |
|
| 540 |
qdev_prop_set_uint16(dev, "depth", depth); |
|
| 541 |
qdev_init(dev); |
|
| 542 |
s = sysbus_from_qdev(dev); |
|
| 543 |
/* 8-bit plane */ |
|
| 544 |
sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
|
| 545 |
/* DAC */ |
|
| 546 |
sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
|
| 547 |
/* TEC (dummy) */ |
|
| 548 |
sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
|
| 549 |
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ |
|
| 550 |
sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
|
| 551 |
if (depth == 24) {
|
|
| 552 |
/* 24-bit plane */ |
|
| 553 |
sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
|
| 554 |
/* Control plane */ |
|
| 555 |
sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
|
| 556 |
} else {
|
|
| 557 |
/* THC 8 bit (dummy) */ |
|
| 558 |
sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
|
| 559 |
} |
|
| 560 |
} |
|
| 561 |
|
|
| 385 | 562 |
/* NCR89C100/MACIO Internal ID register */ |
| 386 | 563 |
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
|
| 387 | 564 |
|
| ... | ... | |
| 1314 | 1491 |
}, |
| 1315 | 1492 |
}; |
| 1316 | 1493 |
|
| 1494 |
static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq) |
|
| 1495 |
{
|
|
| 1496 |
DeviceState *dev; |
|
| 1497 |
SysBusDevice *s; |
|
| 1498 |
unsigned int i; |
|
| 1499 |
|
|
| 1500 |
dev = qdev_create(NULL, "sbi"); |
|
| 1501 |
qdev_init(dev); |
|
| 1502 |
|
|
| 1503 |
s = sysbus_from_qdev(dev); |
|
| 1504 |
|
|
| 1505 |
for (i = 0; i < MAX_CPUS; i++) {
|
|
| 1506 |
sysbus_connect_irq(s, i, *parent_irq[i]); |
|
| 1507 |
} |
|
| 1508 |
|
|
| 1509 |
sysbus_mmio_map(s, 0, addr); |
|
| 1510 |
|
|
| 1511 |
return dev; |
|
| 1512 |
} |
|
| 1513 |
|
|
| 1317 | 1514 |
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
| 1318 | 1515 |
const char *boot_device, |
| 1319 | 1516 |
const char *kernel_filename, |
| ... | ... | |
| 1494 | 1691 |
}, |
| 1495 | 1692 |
}; |
| 1496 | 1693 |
|
| 1694 |
static DeviceState *sun4c_intctl_init(target_phys_addr_t addr, |
|
| 1695 |
qemu_irq *parent_irq) |
|
| 1696 |
{
|
|
| 1697 |
DeviceState *dev; |
|
| 1698 |
SysBusDevice *s; |
|
| 1699 |
unsigned int i; |
|
| 1700 |
|
|
| 1701 |
dev = qdev_create(NULL, "sun4c_intctl"); |
|
| 1702 |
qdev_init(dev); |
|
| 1703 |
|
|
| 1704 |
s = sysbus_from_qdev(dev); |
|
| 1705 |
|
|
| 1706 |
for (i = 0; i < MAX_PILS; i++) {
|
|
| 1707 |
sysbus_connect_irq(s, i, parent_irq[i]); |
|
| 1708 |
} |
|
| 1709 |
sysbus_mmio_map(s, 0, addr); |
|
| 1710 |
|
|
| 1711 |
return dev; |
|
| 1712 |
} |
|
| 1713 |
|
|
| 1497 | 1714 |
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
| 1498 | 1715 |
const char *boot_device, |
| 1499 | 1716 |
const char *kernel_filename, |
| b/hw/sun4m.h | ||
|---|---|---|
| 6 | 6 |
/* Devices used by sparc32 system. */ |
| 7 | 7 |
|
| 8 | 8 |
/* iommu.c */ |
| 9 |
void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq); |
|
| 10 | 9 |
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
| 11 | 10 |
uint8_t *buf, int len, int is_write); |
| 12 | 11 |
static inline void sparc_iommu_memory_read(void *opaque, |
| ... | ... | |
| 23 | 22 |
sparc_iommu_memory_rw(opaque, addr, buf, len, 1); |
| 24 | 23 |
} |
| 25 | 24 |
|
| 26 |
/* tcx.c */ |
|
| 27 |
void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height, |
|
| 28 |
int depth); |
|
| 29 |
|
|
| 30 | 25 |
/* slavio_intctl.c */ |
| 31 |
DeviceState *slavio_intctl_init(target_phys_addr_t addr, |
|
| 32 |
target_phys_addr_t addrg, |
|
| 33 |
const uint32_t *intbit_to_level, |
|
| 34 |
qemu_irq **parent_irq, unsigned int cputimer); |
|
| 35 | 26 |
void slavio_pic_info(Monitor *mon, void *opaque); |
| 36 | 27 |
void slavio_irq_info(Monitor *mon, void *opaque); |
| 37 | 28 |
|
| 38 |
/* sbi.c */ |
|
| 39 |
DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq); |
|
| 40 |
|
|
| 41 | 29 |
/* sun4c_intctl.c */ |
| 42 |
DeviceState *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq *parent_irq); |
|
| 43 | 30 |
void sun4c_pic_info(Monitor *mon, void *opaque); |
| 44 | 31 |
void sun4c_irq_info(Monitor *mon, void *opaque); |
| 45 | 32 |
|
| 46 |
/* slavio_timer.c */ |
|
| 47 |
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq, |
|
| 48 |
qemu_irq *cpu_irqs, unsigned int num_cpus); |
|
| 49 |
|
|
| 50 | 33 |
/* slavio_misc.c */ |
| 51 |
void *slavio_misc_init(target_phys_addr_t base, |
|
| 52 |
target_phys_addr_t aux1_base, |
|
| 53 |
target_phys_addr_t aux2_base, qemu_irq irq, |
|
| 54 |
qemu_irq fdc_tc); |
|
| 55 | 34 |
void slavio_set_power_fail(void *opaque, int power_failing); |
| 56 |
void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt); |
|
| 57 | 35 |
|
| 58 | 36 |
/* sparc32_dma.c */ |
| 59 | 37 |
#include "sparc32_dma.h" |
| 60 | 38 |
|
| 61 |
/* eccmemctl.c */ |
|
| 62 |
void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version); |
|
| 63 |
|
|
| 64 | 39 |
#endif |
| b/hw/tcx.c | ||
|---|---|---|
| 515 | 515 |
tcx_dummy_writel, |
| 516 | 516 |
}; |
| 517 | 517 |
|
| 518 |
void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height, |
|
| 519 |
int depth) |
|
| 520 |
{
|
|
| 521 |
DeviceState *dev; |
|
| 522 |
SysBusDevice *s; |
|
| 523 |
|
|
| 524 |
dev = qdev_create(NULL, "SUNW,tcx"); |
|
| 525 |
qdev_prop_set_taddr(dev, "addr", addr); |
|
| 526 |
qdev_prop_set_uint32(dev, "vram_size", vram_size); |
|
| 527 |
qdev_prop_set_uint16(dev, "width", width); |
|
| 528 |
qdev_prop_set_uint16(dev, "height", height); |
|
| 529 |
qdev_prop_set_uint16(dev, "depth", depth); |
|
| 530 |
qdev_init(dev); |
|
| 531 |
s = sysbus_from_qdev(dev); |
|
| 532 |
/* 8-bit plane */ |
|
| 533 |
sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
|
| 534 |
/* DAC */ |
|
| 535 |
sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
|
| 536 |
/* TEC (dummy) */ |
|
| 537 |
sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
|
| 538 |
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ |
|
| 539 |
sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
|
| 540 |
if (depth == 24) {
|
|
| 541 |
/* 24-bit plane */ |
|
| 542 |
sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
|
| 543 |
/* Control plane */ |
|
| 544 |
sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
|
| 545 |
} else {
|
|
| 546 |
/* THC 8 bit (dummy) */ |
|
| 547 |
sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
|
| 548 |
} |
|
| 549 |
} |
|
| 550 |
|
|
| 551 | 518 |
static void tcx_init1(SysBusDevice *dev) |
| 552 | 519 |
{
|
| 553 | 520 |
TCXState *s = FROM_SYSBUS(TCXState, dev); |
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