Revision 4b48bf05 hw/sun4m.h
| b/hw/sun4m.h | ||
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| 6 | 6 |
/* Devices used by sparc32 system. */ |
| 7 | 7 |
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| 8 | 8 |
/* iommu.c */ |
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void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq); |
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| 10 | 9 |
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
| 11 | 10 |
uint8_t *buf, int len, int is_write); |
| 12 | 11 |
static inline void sparc_iommu_memory_read(void *opaque, |
| ... | ... | |
| 23 | 22 |
sparc_iommu_memory_rw(opaque, addr, buf, len, 1); |
| 24 | 23 |
} |
| 25 | 24 |
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/* tcx.c */ |
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void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height, |
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int depth); |
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/* slavio_intctl.c */ |
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DeviceState *slavio_intctl_init(target_phys_addr_t addr, |
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target_phys_addr_t addrg, |
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const uint32_t *intbit_to_level, |
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qemu_irq **parent_irq, unsigned int cputimer); |
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| 35 | 26 |
void slavio_pic_info(Monitor *mon, void *opaque); |
| 36 | 27 |
void slavio_irq_info(Monitor *mon, void *opaque); |
| 37 | 28 |
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/* sbi.c */ |
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DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq); |
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/* sun4c_intctl.c */ |
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DeviceState *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq *parent_irq); |
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| 43 | 30 |
void sun4c_pic_info(Monitor *mon, void *opaque); |
| 44 | 31 |
void sun4c_irq_info(Monitor *mon, void *opaque); |
| 45 | 32 |
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/* slavio_timer.c */ |
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void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq, |
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qemu_irq *cpu_irqs, unsigned int num_cpus); |
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/* slavio_misc.c */ |
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void *slavio_misc_init(target_phys_addr_t base, |
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target_phys_addr_t aux1_base, |
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target_phys_addr_t aux2_base, qemu_irq irq, |
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qemu_irq fdc_tc); |
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void slavio_set_power_fail(void *opaque, int power_failing); |
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void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt); |
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| 57 | 35 |
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| 58 | 36 |
/* sparc32_dma.c */ |
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#include "sparc32_dma.h" |
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/* eccmemctl.c */ |
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void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version); |
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#endif |
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