tcg-sparc: Implement neg.
The fallback implementation of "ret = 0 - arg1" isn't ideal,first because of the extra tcg op to load the zero, and secondbecause we fail to handle zero as %g0 for arg1 of the sub.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg-sparc: Implement setcond, setcond2.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-sparc: Implement ext32[su]_i64
The 32-bit right-shift instructions is defined to extend the shiftedoutput to 64-bits. A shift count of zero therefore is a simpleextension without actually shifting.
tcg-sparc: Implement division properly.
The {div,divu}2 opcodes are intended for systems for which thedivision instruction produces both quotient and remainder. Sparcis not such a system. Indeed, the remainder must be computed as
quot = a / b rem = a - (quot * b)...
tcg-sparc: Do not remove %o012 from 'r' constraint.
Only 'L' constraint needs that.
tcg-sparc: Implement add2, sub2, mulu2.
Add missing 32-bit double-word support opcodes.
tcg-sparc: Add tcg_out_arithc.
Add a function to handle the register-vs-immediate test for arithmetic.
Also, adjust the OP_32_64 macro so that it auto-indents properly.Rename the gen_arith32 label to gen_arith, since it handles 64-bitarithmetic as well....
tcg-sparc: Implement brcond2.
Split out tcg_out_cmp and properly handle immediate arguments.Fix constraints on brcond to match what SUBCC accepts.Add tcg_out_brcond2_i32 for 32-bit host.
tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.
The test TCG_TARGET_REG_BITS==64 is exactly the feature that weare checking for, whereas something involving sparc_v9 orsparc_v8plus should be reserved for something ISA related,as with SMULX....
tcg-sparc: Improve tcg_out_movi for sparc64.
Generate sign-extended 32-bit constants with SETHI+XOR.Otherwise tidy the routine to avoid the need forconditional compilation and code duplication with movi_imm32.
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