Revision 4b8b8b76 target-sparc/cpu.h

b/target-sparc/cpu.h
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#define TT_TRAP     0x100
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#endif
73 73 

  		





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#define PSR_NEG   (1<<23)


  		





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#define PSR_ZERO  (1<<22)


  		





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#define PSR_OVF   (1<<21)


  		





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#define PSR_CARRY (1<<20)


  		





  
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#define PSR_NEG_SHIFT 23


  		





  
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#define PSR_NEG   (1 << PSR_NEG_SHIFT)


  		





  
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#define PSR_ZERO_SHIFT 22


  		





  
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#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)


  		





  
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#define PSR_OVF_SHIFT 21


  		





  
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#define PSR_OVF   (1 << PSR_OVF_SHIFT)


  		





  
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#define PSR_CARRY_SHIFT 20


  		





  
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#define PSR_CARRY (1 << PSR_CARRY_SHIFT)


  		





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#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)


  		





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#define PSR_EF    (1<<12)


  		





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#define PSR_PIL   0xf00


  		





  ......




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#define FSR_FTT_SEQ_ERROR (4 << 14)


  		





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#define FSR_FTT_INVAL_FPR (6 << 14)


  		





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#define FSR_FCC1  (1<<11)


  		





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#define FSR_FCC0  (1<<10)


  		





  
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#define FSR_FCC1_SHIFT 11


  		





  
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#define FSR_FCC1  (1 << FSR_FCC1_SHIFT)


  		





  
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#define FSR_FCC0_SHIFT 10


  		





  
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#define FSR_FCC0  (1 << FSR_FCC0_SHIFT)


  		





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/* MMU */


  		





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#define MMU_E     (1<<0)


  		












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