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1
/*
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 *  i386 translation
3
 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include <sys/mman.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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33
/* XXX: move that elsewhere */
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
36

    
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#define PREFIX_REPZ   0x01
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#define PREFIX_REPNZ  0x02
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#define PREFIX_LOCK   0x04
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#define PREFIX_DATA   0x08
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#define PREFIX_ADR    0x10
42

    
43
typedef struct DisasContext {
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    /* current insn context */
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    int override; /* -1 if no override */
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    int prefix;
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    int aflag, dflag;
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    uint8_t *pc; /* pc = eip + cs_base */
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    int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
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                   static state change (stop translation) */
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    /* current block context */
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    uint8_t *cs_base; /* base of CS segment */
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    int pe;     /* protected mode */
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    int code32; /* 32 bit code segment */
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    int ss32;   /* 32 bit stack segment */
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    int cc_op;  /* current CC operation */
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    int addseg; /* non zero if either DS/ES/SS have a non zero base */
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    int f_st;   /* currently unused */
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    int vm86;   /* vm86 mode */
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    int cpl;
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    int iopl;
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    int tf;     /* TF cpu flag */
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    int singlestep_enabled; /* "hardware" single step enabled */
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    int jmp_opt; /* use direct block chaining for direct jumps */
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    int mem_index; /* select memory access functions */
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    int flags; /* all execution flags */
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    struct TranslationBlock *tb;
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    int popl_esp_hack; /* for correct popl with esp base handling */
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} DisasContext;
70

    
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static void gen_eob(DisasContext *s);
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static void gen_jmp(DisasContext *s, unsigned int eip);
73

    
74
/* i386 arith/logic operations */
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enum {
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    OP_ADDL, 
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    OP_ORL, 
78
    OP_ADCL, 
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    OP_SBBL,
80
    OP_ANDL, 
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    OP_SUBL, 
82
    OP_XORL, 
83
    OP_CMPL,
84
};
85

    
86
/* i386 shift ops */
87
enum {
88
    OP_ROL, 
89
    OP_ROR, 
90
    OP_RCL, 
91
    OP_RCR, 
92
    OP_SHL, 
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    OP_SHR, 
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    OP_SHL1, /* undocumented */
95
    OP_SAR = 7,
96
};
97

    
98
enum {
99
#define DEF(s, n, copy_size) INDEX_op_ ## s,
100
#include "opc.h"
101
#undef DEF
102
    NB_OPS,
103
};
104

    
105
#include "gen-op.h"
106

    
107
/* operand size */
108
enum {
109
    OT_BYTE = 0,
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    OT_WORD,
111
    OT_LONG, 
112
    OT_QUAD,
113
};
114

    
115
enum {
116
    /* I386 int registers */
117
    OR_EAX,   /* MUST be even numbered */
118
    OR_ECX,
119
    OR_EDX,
120
    OR_EBX,
121
    OR_ESP,
122
    OR_EBP,
123
    OR_ESI,
124
    OR_EDI,
125
    OR_TMP0,    /* temporary operand register */
126
    OR_TMP1,
127
    OR_A0, /* temporary register used when doing address evaluation */
128
    OR_ZERO, /* fixed zero register */
129
    NB_OREGS,
130
};
131

    
132
static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
133
    [OT_BYTE] = {
134
        gen_op_movb_EAX_T0,
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        gen_op_movb_ECX_T0,
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        gen_op_movb_EDX_T0,
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        gen_op_movb_EBX_T0,
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        gen_op_movh_EAX_T0,
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        gen_op_movh_ECX_T0,
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        gen_op_movh_EDX_T0,
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        gen_op_movh_EBX_T0,
142
    },
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    [OT_WORD] = {
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        gen_op_movw_EAX_T0,
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        gen_op_movw_ECX_T0,
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        gen_op_movw_EDX_T0,
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        gen_op_movw_EBX_T0,
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        gen_op_movw_ESP_T0,
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        gen_op_movw_EBP_T0,
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        gen_op_movw_ESI_T0,
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        gen_op_movw_EDI_T0,
152
    },
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    [OT_LONG] = {
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        gen_op_movl_EAX_T0,
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        gen_op_movl_ECX_T0,
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        gen_op_movl_EDX_T0,
157
        gen_op_movl_EBX_T0,
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        gen_op_movl_ESP_T0,
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        gen_op_movl_EBP_T0,
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        gen_op_movl_ESI_T0,
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        gen_op_movl_EDI_T0,
162
    },
163
};
164

    
165
static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
166
    [OT_BYTE] = {
167
        gen_op_movb_EAX_T1,
168
        gen_op_movb_ECX_T1,
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        gen_op_movb_EDX_T1,
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        gen_op_movb_EBX_T1,
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        gen_op_movh_EAX_T1,
172
        gen_op_movh_ECX_T1,
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        gen_op_movh_EDX_T1,
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        gen_op_movh_EBX_T1,
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    },
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    [OT_WORD] = {
177
        gen_op_movw_EAX_T1,
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        gen_op_movw_ECX_T1,
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        gen_op_movw_EDX_T1,
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        gen_op_movw_EBX_T1,
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        gen_op_movw_ESP_T1,
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        gen_op_movw_EBP_T1,
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        gen_op_movw_ESI_T1,
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        gen_op_movw_EDI_T1,
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    },
186
    [OT_LONG] = {
187
        gen_op_movl_EAX_T1,
188
        gen_op_movl_ECX_T1,
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        gen_op_movl_EDX_T1,
190
        gen_op_movl_EBX_T1,
191
        gen_op_movl_ESP_T1,
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        gen_op_movl_EBP_T1,
193
        gen_op_movl_ESI_T1,
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        gen_op_movl_EDI_T1,
195
    },
196
};
197

    
198
static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
199
    [0] = {
200
        gen_op_movw_EAX_A0,
201
        gen_op_movw_ECX_A0,
202
        gen_op_movw_EDX_A0,
203
        gen_op_movw_EBX_A0,
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        gen_op_movw_ESP_A0,
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        gen_op_movw_EBP_A0,
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        gen_op_movw_ESI_A0,
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        gen_op_movw_EDI_A0,
208
    },
209
    [1] = {
210
        gen_op_movl_EAX_A0,
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        gen_op_movl_ECX_A0,
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        gen_op_movl_EDX_A0,
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        gen_op_movl_EBX_A0,
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        gen_op_movl_ESP_A0,
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        gen_op_movl_EBP_A0,
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        gen_op_movl_ESI_A0,
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        gen_op_movl_EDI_A0,
218
    },
219
};
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static GenOpFunc *gen_op_mov_TN_reg[3][2][8] = 
222
{
223
    [OT_BYTE] = {
224
        {
225
            gen_op_movl_T0_EAX,
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            gen_op_movl_T0_ECX,
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            gen_op_movl_T0_EDX,
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            gen_op_movl_T0_EBX,
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            gen_op_movh_T0_EAX,
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            gen_op_movh_T0_ECX,
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            gen_op_movh_T0_EDX,
232
            gen_op_movh_T0_EBX,
233
        },
234
        {
235
            gen_op_movl_T1_EAX,
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            gen_op_movl_T1_ECX,
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            gen_op_movl_T1_EDX,
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            gen_op_movl_T1_EBX,
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            gen_op_movh_T1_EAX,
240
            gen_op_movh_T1_ECX,
241
            gen_op_movh_T1_EDX,
242
            gen_op_movh_T1_EBX,
243
        },
244
    },
245
    [OT_WORD] = {
246
        {
247
            gen_op_movl_T0_EAX,
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            gen_op_movl_T0_ECX,
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            gen_op_movl_T0_EDX,
250
            gen_op_movl_T0_EBX,
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            gen_op_movl_T0_ESP,
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            gen_op_movl_T0_EBP,
253
            gen_op_movl_T0_ESI,
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            gen_op_movl_T0_EDI,
255
        },
256
        {
257
            gen_op_movl_T1_EAX,
258
            gen_op_movl_T1_ECX,
259
            gen_op_movl_T1_EDX,
260
            gen_op_movl_T1_EBX,
261
            gen_op_movl_T1_ESP,
262
            gen_op_movl_T1_EBP,
263
            gen_op_movl_T1_ESI,
264
            gen_op_movl_T1_EDI,
265
        },
266
    },
267
    [OT_LONG] = {
268
        {
269
            gen_op_movl_T0_EAX,
270
            gen_op_movl_T0_ECX,
271
            gen_op_movl_T0_EDX,
272
            gen_op_movl_T0_EBX,
273
            gen_op_movl_T0_ESP,
274
            gen_op_movl_T0_EBP,
275
            gen_op_movl_T0_ESI,
276
            gen_op_movl_T0_EDI,
277
        },
278
        {
279
            gen_op_movl_T1_EAX,
280
            gen_op_movl_T1_ECX,
281
            gen_op_movl_T1_EDX,
282
            gen_op_movl_T1_EBX,
283
            gen_op_movl_T1_ESP,
284
            gen_op_movl_T1_EBP,
285
            gen_op_movl_T1_ESI,
286
            gen_op_movl_T1_EDI,
287
        },
288
    },
289
};
290

    
291
static GenOpFunc *gen_op_movl_A0_reg[8] = {
292
    gen_op_movl_A0_EAX,
293
    gen_op_movl_A0_ECX,
294
    gen_op_movl_A0_EDX,
295
    gen_op_movl_A0_EBX,
296
    gen_op_movl_A0_ESP,
297
    gen_op_movl_A0_EBP,
298
    gen_op_movl_A0_ESI,
299
    gen_op_movl_A0_EDI,
300
};
301

    
302
static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
303
    [0] = {
304
        gen_op_addl_A0_EAX,
305
        gen_op_addl_A0_ECX,
306
        gen_op_addl_A0_EDX,
307
        gen_op_addl_A0_EBX,
308
        gen_op_addl_A0_ESP,
309
        gen_op_addl_A0_EBP,
310
        gen_op_addl_A0_ESI,
311
        gen_op_addl_A0_EDI,
312
    },
313
    [1] = {
314
        gen_op_addl_A0_EAX_s1,
315
        gen_op_addl_A0_ECX_s1,
316
        gen_op_addl_A0_EDX_s1,
317
        gen_op_addl_A0_EBX_s1,
318
        gen_op_addl_A0_ESP_s1,
319
        gen_op_addl_A0_EBP_s1,
320
        gen_op_addl_A0_ESI_s1,
321
        gen_op_addl_A0_EDI_s1,
322
    },
323
    [2] = {
324
        gen_op_addl_A0_EAX_s2,
325
        gen_op_addl_A0_ECX_s2,
326
        gen_op_addl_A0_EDX_s2,
327
        gen_op_addl_A0_EBX_s2,
328
        gen_op_addl_A0_ESP_s2,
329
        gen_op_addl_A0_EBP_s2,
330
        gen_op_addl_A0_ESI_s2,
331
        gen_op_addl_A0_EDI_s2,
332
    },
333
    [3] = {
334
        gen_op_addl_A0_EAX_s3,
335
        gen_op_addl_A0_ECX_s3,
336
        gen_op_addl_A0_EDX_s3,
337
        gen_op_addl_A0_EBX_s3,
338
        gen_op_addl_A0_ESP_s3,
339
        gen_op_addl_A0_EBP_s3,
340
        gen_op_addl_A0_ESI_s3,
341
        gen_op_addl_A0_EDI_s3,
342
    },
343
};
344

    
345
static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
346
    [0] = {
347
        gen_op_cmovw_EAX_T1_T0,
348
        gen_op_cmovw_ECX_T1_T0,
349
        gen_op_cmovw_EDX_T1_T0,
350
        gen_op_cmovw_EBX_T1_T0,
351
        gen_op_cmovw_ESP_T1_T0,
352
        gen_op_cmovw_EBP_T1_T0,
353
        gen_op_cmovw_ESI_T1_T0,
354
        gen_op_cmovw_EDI_T1_T0,
355
    },
356
    [1] = {
357
        gen_op_cmovl_EAX_T1_T0,
358
        gen_op_cmovl_ECX_T1_T0,
359
        gen_op_cmovl_EDX_T1_T0,
360
        gen_op_cmovl_EBX_T1_T0,
361
        gen_op_cmovl_ESP_T1_T0,
362
        gen_op_cmovl_EBP_T1_T0,
363
        gen_op_cmovl_ESI_T1_T0,
364
        gen_op_cmovl_EDI_T1_T0,
365
    },
366
};
367

    
368
static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
369
    NULL,
370
    gen_op_orl_T0_T1,
371
    NULL,
372
    NULL,
373
    gen_op_andl_T0_T1,
374
    NULL,
375
    gen_op_xorl_T0_T1,
376
    NULL,
377
};
378

    
379
#define DEF_ARITHC(SUFFIX)\
380
    {\
381
        gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
382
        gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
383
    },\
384
    {\
385
        gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
386
        gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
387
    },\
388
    {\
389
        gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
390
        gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
391
    },
392

    
393
static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
394
    DEF_ARITHC( )
395
};
396

    
397
static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[9][2] = {
398
    DEF_ARITHC(_raw)
399
#ifndef CONFIG_USER_ONLY
400
    DEF_ARITHC(_kernel)
401
    DEF_ARITHC(_user)
402
#endif
403
};
404

    
405
static const int cc_op_arithb[8] = {
406
    CC_OP_ADDB,
407
    CC_OP_LOGICB,
408
    CC_OP_ADDB,
409
    CC_OP_SUBB,
410
    CC_OP_LOGICB,
411
    CC_OP_SUBB,
412
    CC_OP_LOGICB,
413
    CC_OP_SUBB,
414
};
415

    
416
#define DEF_CMPXCHG(SUFFIX)\
417
    gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
418
    gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
419
    gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,
420

    
421

    
422
static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
423
    DEF_CMPXCHG( )
424
};
425

    
426
static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[9] = {
427
    DEF_CMPXCHG(_raw)
428
#ifndef CONFIG_USER_ONLY
429
    DEF_CMPXCHG(_kernel)
430
    DEF_CMPXCHG(_user)
431
#endif
432
};
433

    
434
#define DEF_SHIFT(SUFFIX)\
435
    {\
436
        gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
437
        gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
438
        gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
439
        gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
440
        gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
441
        gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
442
        gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
443
        gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
444
    },\
445
    {\
446
        gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
447
        gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
448
        gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
449
        gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
450
        gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
451
        gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
452
        gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
453
        gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
454
    },\
455
    {\
456
        gen_op_roll ## SUFFIX ## _T0_T1_cc,\
457
        gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
458
        gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
459
        gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
460
        gen_op_shll ## SUFFIX ## _T0_T1_cc,\
461
        gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
462
        gen_op_shll ## SUFFIX ## _T0_T1_cc,\
463
        gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
464
    },
465

    
466
static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
467
    DEF_SHIFT( )
468
};
469

    
470
static GenOpFunc *gen_op_shift_mem_T0_T1_cc[9][8] = {
471
    DEF_SHIFT(_raw)
472
#ifndef CONFIG_USER_ONLY
473
    DEF_SHIFT(_kernel)
474
    DEF_SHIFT(_user)
475
#endif
476
};
477

    
478
#define DEF_SHIFTD(SUFFIX, op)\
479
    {\
480
        NULL,\
481
        NULL,\
482
    },\
483
    {\
484
        gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
485
        gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
486
    },\
487
    {\
488
        gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
489
        gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
490
    },
491

    
492

    
493
static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[3][2] = {
494
    DEF_SHIFTD(, im)
495
};
496

    
497
static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[3][2] = {
498
    DEF_SHIFTD(, ECX)
499
};
500

    
501
static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[9][2] = {
502
    DEF_SHIFTD(_raw, im)
503
#ifndef CONFIG_USER_ONLY
504
    DEF_SHIFTD(_kernel, im)
505
    DEF_SHIFTD(_user, im)
506
#endif
507
};
508

    
509
static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[9][2] = {
510
    DEF_SHIFTD(_raw, ECX)
511
#ifndef CONFIG_USER_ONLY
512
    DEF_SHIFTD(_kernel, ECX)
513
    DEF_SHIFTD(_user, ECX)
514
#endif
515
};
516

    
517
static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
518
    [0] = {
519
        gen_op_btw_T0_T1_cc,
520
        gen_op_btsw_T0_T1_cc,
521
        gen_op_btrw_T0_T1_cc,
522
        gen_op_btcw_T0_T1_cc,
523
    },
524
    [1] = {
525
        gen_op_btl_T0_T1_cc,
526
        gen_op_btsl_T0_T1_cc,
527
        gen_op_btrl_T0_T1_cc,
528
        gen_op_btcl_T0_T1_cc,
529
    },
530
};
531

    
532
static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
533
    [0] = {
534
        gen_op_bsfw_T0_cc,
535
        gen_op_bsrw_T0_cc,
536
    },
537
    [1] = {
538
        gen_op_bsfl_T0_cc,
539
        gen_op_bsrl_T0_cc,
540
    },
541
};
542

    
543
static GenOpFunc *gen_op_lds_T0_A0[3 * 3] = {
544
    gen_op_ldsb_raw_T0_A0,
545
    gen_op_ldsw_raw_T0_A0,
546
    NULL,
547
#ifndef CONFIG_USER_ONLY
548
    gen_op_ldsb_kernel_T0_A0,
549
    gen_op_ldsw_kernel_T0_A0,
550
    NULL,
551

    
552
    gen_op_ldsb_user_T0_A0,
553
    gen_op_ldsw_user_T0_A0,
554
    NULL,
555
#endif
556
};
557

    
558
static GenOpFunc *gen_op_ldu_T0_A0[3 * 3] = {
559
    gen_op_ldub_raw_T0_A0,
560
    gen_op_lduw_raw_T0_A0,
561
    NULL,
562

    
563
#ifndef CONFIG_USER_ONLY
564
    gen_op_ldub_kernel_T0_A0,
565
    gen_op_lduw_kernel_T0_A0,
566
    NULL,
567

    
568
    gen_op_ldub_user_T0_A0,
569
    gen_op_lduw_user_T0_A0,
570
    NULL,
571
#endif
572
};
573

    
574
/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
575
static GenOpFunc *gen_op_ld_T0_A0[3 * 3] = {
576
    gen_op_ldub_raw_T0_A0,
577
    gen_op_lduw_raw_T0_A0,
578
    gen_op_ldl_raw_T0_A0,
579

    
580
#ifndef CONFIG_USER_ONLY
581
    gen_op_ldub_kernel_T0_A0,
582
    gen_op_lduw_kernel_T0_A0,
583
    gen_op_ldl_kernel_T0_A0,
584

    
585
    gen_op_ldub_user_T0_A0,
586
    gen_op_lduw_user_T0_A0,
587
    gen_op_ldl_user_T0_A0,
588
#endif
589
};
590

    
591
static GenOpFunc *gen_op_ld_T1_A0[3 * 3] = {
592
    gen_op_ldub_raw_T1_A0,
593
    gen_op_lduw_raw_T1_A0,
594
    gen_op_ldl_raw_T1_A0,
595

    
596
#ifndef CONFIG_USER_ONLY
597
    gen_op_ldub_kernel_T1_A0,
598
    gen_op_lduw_kernel_T1_A0,
599
    gen_op_ldl_kernel_T1_A0,
600

    
601
    gen_op_ldub_user_T1_A0,
602
    gen_op_lduw_user_T1_A0,
603
    gen_op_ldl_user_T1_A0,
604
#endif
605
};
606

    
607
static GenOpFunc *gen_op_st_T0_A0[3 * 3] = {
608
    gen_op_stb_raw_T0_A0,
609
    gen_op_stw_raw_T0_A0,
610
    gen_op_stl_raw_T0_A0,
611

    
612
#ifndef CONFIG_USER_ONLY
613
    gen_op_stb_kernel_T0_A0,
614
    gen_op_stw_kernel_T0_A0,
615
    gen_op_stl_kernel_T0_A0,
616

    
617
    gen_op_stb_user_T0_A0,
618
    gen_op_stw_user_T0_A0,
619
    gen_op_stl_user_T0_A0,
620
#endif
621
};
622

    
623
static GenOpFunc *gen_op_st_T1_A0[3 * 3] = {
624
    NULL,
625
    gen_op_stw_raw_T1_A0,
626
    gen_op_stl_raw_T1_A0,
627

    
628
#ifndef CONFIG_USER_ONLY
629
    NULL,
630
    gen_op_stw_kernel_T1_A0,
631
    gen_op_stl_kernel_T1_A0,
632

    
633
    NULL,
634
    gen_op_stw_user_T1_A0,
635
    gen_op_stl_user_T1_A0,
636
#endif
637
};
638

    
639
static inline void gen_string_movl_A0_ESI(DisasContext *s)
640
{
641
    int override;
642

    
643
    override = s->override;
644
    if (s->aflag) {
645
        /* 32 bit address */
646
        if (s->addseg && override < 0)
647
            override = R_DS;
648
        if (override >= 0) {
649
            gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
650
            gen_op_addl_A0_reg_sN[0][R_ESI]();
651
        } else {
652
            gen_op_movl_A0_reg[R_ESI]();
653
        }
654
    } else {
655
        /* 16 address, always override */
656
        if (override < 0)
657
            override = R_DS;
658
        gen_op_movl_A0_reg[R_ESI]();
659
        gen_op_andl_A0_ffff();
660
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
661
    }
662
}
663

    
664
static inline void gen_string_movl_A0_EDI(DisasContext *s)
665
{
666
    if (s->aflag) {
667
        if (s->addseg) {
668
            gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
669
            gen_op_addl_A0_reg_sN[0][R_EDI]();
670
        } else {
671
            gen_op_movl_A0_reg[R_EDI]();
672
        }
673
    } else {
674
        gen_op_movl_A0_reg[R_EDI]();
675
        gen_op_andl_A0_ffff();
676
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
677
    }
678
}
679

    
680
static GenOpFunc *gen_op_movl_T0_Dshift[3] = {
681
    gen_op_movl_T0_Dshiftb,
682
    gen_op_movl_T0_Dshiftw,
683
    gen_op_movl_T0_Dshiftl,
684
};
685

    
686
static GenOpFunc2 *gen_op_jz_ecx[2] = {
687
    gen_op_jz_ecxw,
688
    gen_op_jz_ecxl,
689
};
690
    
691
static GenOpFunc1 *gen_op_jz_ecx_im[2] = {
692
    gen_op_jz_ecxw_im,
693
    gen_op_jz_ecxl_im,
694
};
695

    
696
static GenOpFunc *gen_op_dec_ECX[2] = {
697
    gen_op_decw_ECX,
698
    gen_op_decl_ECX,
699
};
700

    
701
#ifdef USE_DIRECT_JUMP
702
typedef GenOpFunc GenOpFuncTB2;
703
#define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot]()
704
#else
705
typedef GenOpFunc1 GenOpFuncTB2;
706
#define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot](tb)
707
#endif
708

    
709
static GenOpFuncTB2 *gen_op_string_jnz_sub2[2][3] = {
710
    {
711
        gen_op_string_jnz_subb,
712
        gen_op_string_jnz_subw,
713
        gen_op_string_jnz_subl,
714
    },
715
    {
716
        gen_op_string_jz_subb,
717
        gen_op_string_jz_subw,
718
        gen_op_string_jz_subl,
719
    },
720
};
721

    
722
static GenOpFunc1 *gen_op_string_jnz_sub_im[2][3] = {
723
    {
724
        gen_op_string_jnz_subb_im,
725
        gen_op_string_jnz_subw_im,
726
        gen_op_string_jnz_subl_im,
727
    },
728
    {
729
        gen_op_string_jz_subb_im,
730
        gen_op_string_jz_subw_im,
731
        gen_op_string_jz_subl_im,
732
    },
733
};
734

    
735
static GenOpFunc *gen_op_in_DX_T0[3] = {
736
    gen_op_inb_DX_T0,
737
    gen_op_inw_DX_T0,
738
    gen_op_inl_DX_T0,
739
};
740

    
741
static GenOpFunc *gen_op_out_DX_T0[3] = {
742
    gen_op_outb_DX_T0,
743
    gen_op_outw_DX_T0,
744
    gen_op_outl_DX_T0,
745
};
746

    
747
static GenOpFunc *gen_op_in[3] = {
748
    gen_op_inb_T0_T1,
749
    gen_op_inw_T0_T1,
750
    gen_op_inl_T0_T1,
751
};
752

    
753
static GenOpFunc *gen_op_out[3] = {
754
    gen_op_outb_T0_T1,
755
    gen_op_outw_T0_T1,
756
    gen_op_outl_T0_T1,
757
};
758

    
759
static GenOpFunc *gen_check_io_T0[3] = {
760
    gen_op_check_iob_T0,
761
    gen_op_check_iow_T0,
762
    gen_op_check_iol_T0,
763
};
764

    
765
static GenOpFunc *gen_check_io_DX[3] = {
766
    gen_op_check_iob_DX,
767
    gen_op_check_iow_DX,
768
    gen_op_check_iol_DX,
769
};
770

    
771
static void gen_check_io(DisasContext *s, int ot, int use_dx, int cur_eip)
772
{
773
    if (s->pe && (s->cpl > s->iopl || s->vm86)) {
774
        if (s->cc_op != CC_OP_DYNAMIC)
775
            gen_op_set_cc_op(s->cc_op);
776
        gen_op_jmp_im(cur_eip);
777
        if (use_dx)
778
            gen_check_io_DX[ot]();
779
        else
780
            gen_check_io_T0[ot]();
781
    }
782
}
783

    
784
static inline void gen_movs(DisasContext *s, int ot)
785
{
786
    gen_string_movl_A0_ESI(s);
787
    gen_op_ld_T0_A0[ot + s->mem_index]();
788
    gen_string_movl_A0_EDI(s);
789
    gen_op_st_T0_A0[ot + s->mem_index]();
790
    gen_op_movl_T0_Dshift[ot]();
791
    if (s->aflag) {
792
        gen_op_addl_ESI_T0();
793
        gen_op_addl_EDI_T0();
794
    } else {
795
        gen_op_addw_ESI_T0();
796
        gen_op_addw_EDI_T0();
797
    }
798
}
799

    
800
static inline void gen_update_cc_op(DisasContext *s)
801
{
802
    if (s->cc_op != CC_OP_DYNAMIC) {
803
        gen_op_set_cc_op(s->cc_op);
804
        s->cc_op = CC_OP_DYNAMIC;
805
    }
806
}
807

    
808
static inline void gen_jz_ecx_string(DisasContext *s, unsigned int next_eip)
809
{
810
    if (s->jmp_opt) {
811
        gen_op_jz_ecx[s->aflag]((long)s->tb, next_eip);
812
    } else {
813
        /* XXX: does not work with gdbstub "ice" single step - not a
814
           serious problem */
815
        gen_op_jz_ecx_im[s->aflag](next_eip);
816
    }
817
}
818

    
819
static inline void gen_stos(DisasContext *s, int ot)
820
{
821
    gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
822
    gen_string_movl_A0_EDI(s);
823
    gen_op_st_T0_A0[ot + s->mem_index]();
824
    gen_op_movl_T0_Dshift[ot]();
825
    if (s->aflag) {
826
        gen_op_addl_EDI_T0();
827
    } else {
828
        gen_op_addw_EDI_T0();
829
    }
830
}
831

    
832
static inline void gen_lods(DisasContext *s, int ot)
833
{
834
    gen_string_movl_A0_ESI(s);
835
    gen_op_ld_T0_A0[ot + s->mem_index]();
836
    gen_op_mov_reg_T0[ot][R_EAX]();
837
    gen_op_movl_T0_Dshift[ot]();
838
    if (s->aflag) {
839
        gen_op_addl_ESI_T0();
840
    } else {
841
        gen_op_addw_ESI_T0();
842
    }
843
}
844

    
845
static inline void gen_scas(DisasContext *s, int ot)
846
{
847
    gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
848
    gen_string_movl_A0_EDI(s);
849
    gen_op_ld_T1_A0[ot + s->mem_index]();
850
    gen_op_cmpl_T0_T1_cc();
851
    gen_op_movl_T0_Dshift[ot]();
852
    if (s->aflag) {
853
        gen_op_addl_EDI_T0();
854
    } else {
855
        gen_op_addw_EDI_T0();
856
    }
857
}
858

    
859
static inline void gen_cmps(DisasContext *s, int ot)
860
{
861
    gen_string_movl_A0_ESI(s);
862
    gen_op_ld_T0_A0[ot + s->mem_index]();
863
    gen_string_movl_A0_EDI(s);
864
    gen_op_ld_T1_A0[ot + s->mem_index]();
865
    gen_op_cmpl_T0_T1_cc();
866
    gen_op_movl_T0_Dshift[ot]();
867
    if (s->aflag) {
868
        gen_op_addl_ESI_T0();
869
        gen_op_addl_EDI_T0();
870
    } else {
871
        gen_op_addw_ESI_T0();
872
        gen_op_addw_EDI_T0();
873
    }
874
}
875

    
876
static inline void gen_ins(DisasContext *s, int ot)
877
{
878
    gen_op_in_DX_T0[ot]();
879
    gen_string_movl_A0_EDI(s);
880
    gen_op_st_T0_A0[ot + s->mem_index]();
881
    gen_op_movl_T0_Dshift[ot]();
882
    if (s->aflag) {
883
        gen_op_addl_EDI_T0();
884
    } else {
885
        gen_op_addw_EDI_T0();
886
    }
887
}
888

    
889
static inline void gen_outs(DisasContext *s, int ot)
890
{
891
    gen_string_movl_A0_ESI(s);
892
    gen_op_ld_T0_A0[ot + s->mem_index]();
893
    gen_op_out_DX_T0[ot]();
894
    gen_op_movl_T0_Dshift[ot]();
895
    if (s->aflag) {
896
        gen_op_addl_ESI_T0();
897
    } else {
898
        gen_op_addw_ESI_T0();
899
    }
900
}
901

    
902
/* same method as Valgrind : we generate jumps to current or next
903
   instruction */
904
#define GEN_REPZ(op)                                                          \
905
static inline void gen_repz_ ## op(DisasContext *s, int ot,                   \
906
                                 unsigned int cur_eip, unsigned int next_eip) \
907
{                                                                             \
908
    gen_update_cc_op(s);                                                      \
909
    gen_jz_ecx_string(s, next_eip);                                           \
910
    gen_ ## op(s, ot);                                                        \
911
    gen_op_dec_ECX[s->aflag]();                                               \
912
    /* a loop would cause two single step exceptions if ECX = 1               \
913
       before rep string_insn */                                              \
914
    if (!s->jmp_opt)                                                          \
915
        gen_op_jz_ecx_im[s->aflag](next_eip);                                 \
916
    gen_jmp(s, cur_eip);                                                      \
917
}
918

    
919
#define GEN_REPZ2(op)                                                         \
920
static inline void gen_repz_ ## op(DisasContext *s, int ot,                   \
921
                                   unsigned int cur_eip,                      \
922
                                   unsigned int next_eip,                     \
923
                                   int nz)                                    \
924
{                                                                             \
925
    gen_update_cc_op(s);                                                      \
926
    gen_jz_ecx_string(s, next_eip);                                           \
927
    gen_ ## op(s, ot);                                                        \
928
    gen_op_dec_ECX[s->aflag]();                                               \
929
    gen_op_set_cc_op(CC_OP_SUBB + ot);                                        \
930
    if (!s->jmp_opt)                                                          \
931
        gen_op_string_jnz_sub_im[nz][ot](next_eip);                           \
932
    else                                                                      \
933
        gen_op_string_jnz_sub(nz, ot, (long)s->tb);                           \
934
    if (!s->jmp_opt)                                                          \
935
        gen_op_jz_ecx_im[s->aflag](next_eip);                                 \
936
    gen_jmp(s, cur_eip);                                                      \
937
}
938

    
939
GEN_REPZ(movs)
940
GEN_REPZ(stos)
941
GEN_REPZ(lods)
942
GEN_REPZ(ins)
943
GEN_REPZ(outs)
944
GEN_REPZ2(scas)
945
GEN_REPZ2(cmps)
946

    
947
enum {
948
    JCC_O,
949
    JCC_B,
950
    JCC_Z,
951
    JCC_BE,
952
    JCC_S,
953
    JCC_P,
954
    JCC_L,
955
    JCC_LE,
956
};
957

    
958
static GenOpFunc3 *gen_jcc_sub[3][8] = {
959
    [OT_BYTE] = {
960
        NULL,
961
        gen_op_jb_subb,
962
        gen_op_jz_subb,
963
        gen_op_jbe_subb,
964
        gen_op_js_subb,
965
        NULL,
966
        gen_op_jl_subb,
967
        gen_op_jle_subb,
968
    },
969
    [OT_WORD] = {
970
        NULL,
971
        gen_op_jb_subw,
972
        gen_op_jz_subw,
973
        gen_op_jbe_subw,
974
        gen_op_js_subw,
975
        NULL,
976
        gen_op_jl_subw,
977
        gen_op_jle_subw,
978
    },
979
    [OT_LONG] = {
980
        NULL,
981
        gen_op_jb_subl,
982
        gen_op_jz_subl,
983
        gen_op_jbe_subl,
984
        gen_op_js_subl,
985
        NULL,
986
        gen_op_jl_subl,
987
        gen_op_jle_subl,
988
    },
989
};
990
static GenOpFunc2 *gen_op_loop[2][4] = {
991
    [0] = {
992
        gen_op_loopnzw,
993
        gen_op_loopzw,
994
        gen_op_loopw,
995
        gen_op_jecxzw,
996
    },
997
    [1] = {
998
        gen_op_loopnzl,
999
        gen_op_loopzl,
1000
        gen_op_loopl,
1001
        gen_op_jecxzl,
1002
    },
1003
};
1004

    
1005
static GenOpFunc *gen_setcc_slow[8] = {
1006
    gen_op_seto_T0_cc,
1007
    gen_op_setb_T0_cc,
1008
    gen_op_setz_T0_cc,
1009
    gen_op_setbe_T0_cc,
1010
    gen_op_sets_T0_cc,
1011
    gen_op_setp_T0_cc,
1012
    gen_op_setl_T0_cc,
1013
    gen_op_setle_T0_cc,
1014
};
1015

    
1016
static GenOpFunc *gen_setcc_sub[3][8] = {
1017
    [OT_BYTE] = {
1018
        NULL,
1019
        gen_op_setb_T0_subb,
1020
        gen_op_setz_T0_subb,
1021
        gen_op_setbe_T0_subb,
1022
        gen_op_sets_T0_subb,
1023
        NULL,
1024
        gen_op_setl_T0_subb,
1025
        gen_op_setle_T0_subb,
1026
    },
1027
    [OT_WORD] = {
1028
        NULL,
1029
        gen_op_setb_T0_subw,
1030
        gen_op_setz_T0_subw,
1031
        gen_op_setbe_T0_subw,
1032
        gen_op_sets_T0_subw,
1033
        NULL,
1034
        gen_op_setl_T0_subw,
1035
        gen_op_setle_T0_subw,
1036
    },
1037
    [OT_LONG] = {
1038
        NULL,
1039
        gen_op_setb_T0_subl,
1040
        gen_op_setz_T0_subl,
1041
        gen_op_setbe_T0_subl,
1042
        gen_op_sets_T0_subl,
1043
        NULL,
1044
        gen_op_setl_T0_subl,
1045
        gen_op_setle_T0_subl,
1046
    },
1047
};
1048

    
1049
static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1050
    gen_op_fadd_ST0_FT0,
1051
    gen_op_fmul_ST0_FT0,
1052
    gen_op_fcom_ST0_FT0,
1053
    gen_op_fcom_ST0_FT0,
1054
    gen_op_fsub_ST0_FT0,
1055
    gen_op_fsubr_ST0_FT0,
1056
    gen_op_fdiv_ST0_FT0,
1057
    gen_op_fdivr_ST0_FT0,
1058
};
1059

    
1060
/* NOTE the exception in "r" op ordering */
1061
static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1062
    gen_op_fadd_STN_ST0,
1063
    gen_op_fmul_STN_ST0,
1064
    NULL,
1065
    NULL,
1066
    gen_op_fsubr_STN_ST0,
1067
    gen_op_fsub_STN_ST0,
1068
    gen_op_fdivr_STN_ST0,
1069
    gen_op_fdiv_STN_ST0,
1070
};
1071

    
1072
/* if d == OR_TMP0, it means memory operand (address in A0) */
1073
static void gen_op(DisasContext *s1, int op, int ot, int d)
1074
{
1075
    GenOpFunc *gen_update_cc;
1076
    
1077
    if (d != OR_TMP0) {
1078
        gen_op_mov_TN_reg[ot][0][d]();
1079
    } else {
1080
        gen_op_ld_T0_A0[ot + s1->mem_index]();
1081
    }
1082
    switch(op) {
1083
    case OP_ADCL:
1084
    case OP_SBBL:
1085
        if (s1->cc_op != CC_OP_DYNAMIC)
1086
            gen_op_set_cc_op(s1->cc_op);
1087
        if (d != OR_TMP0) {
1088
            gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1089
            gen_op_mov_reg_T0[ot][d]();
1090
        } else {
1091
            gen_op_arithc_mem_T0_T1_cc[ot + s1->mem_index][op - OP_ADCL]();
1092
        }
1093
        s1->cc_op = CC_OP_DYNAMIC;
1094
        goto the_end;
1095
    case OP_ADDL:
1096
        gen_op_addl_T0_T1();
1097
        s1->cc_op = CC_OP_ADDB + ot;
1098
        gen_update_cc = gen_op_update2_cc;
1099
        break;
1100
    case OP_SUBL:
1101
        gen_op_subl_T0_T1();
1102
        s1->cc_op = CC_OP_SUBB + ot;
1103
        gen_update_cc = gen_op_update2_cc;
1104
        break;
1105
    default:
1106
    case OP_ANDL:
1107
    case OP_ORL:
1108
    case OP_XORL:
1109
        gen_op_arith_T0_T1_cc[op]();
1110
        s1->cc_op = CC_OP_LOGICB + ot;
1111
        gen_update_cc = gen_op_update1_cc;
1112
        break;
1113
    case OP_CMPL:
1114
        gen_op_cmpl_T0_T1_cc();
1115
        s1->cc_op = CC_OP_SUBB + ot;
1116
        gen_update_cc = NULL;
1117
        break;
1118
    }
1119
    if (op != OP_CMPL) {
1120
        if (d != OR_TMP0)
1121
            gen_op_mov_reg_T0[ot][d]();
1122
        else
1123
            gen_op_st_T0_A0[ot + s1->mem_index]();
1124
    }
1125
    /* the flags update must happen after the memory write (precise
1126
       exception support) */
1127
    if (gen_update_cc)
1128
        gen_update_cc();
1129
 the_end: ;
1130
}
1131

    
1132
/* if d == OR_TMP0, it means memory operand (address in A0) */
1133
static void gen_inc(DisasContext *s1, int ot, int d, int c)
1134
{
1135
    if (d != OR_TMP0)
1136
        gen_op_mov_TN_reg[ot][0][d]();
1137
    else
1138
        gen_op_ld_T0_A0[ot + s1->mem_index]();
1139
    if (s1->cc_op != CC_OP_DYNAMIC)
1140
        gen_op_set_cc_op(s1->cc_op);
1141
    if (c > 0) {
1142
        gen_op_incl_T0();
1143
        s1->cc_op = CC_OP_INCB + ot;
1144
    } else {
1145
        gen_op_decl_T0();
1146
        s1->cc_op = CC_OP_DECB + ot;
1147
    }
1148
    if (d != OR_TMP0)
1149
        gen_op_mov_reg_T0[ot][d]();
1150
    else
1151
        gen_op_st_T0_A0[ot + s1->mem_index]();
1152
    gen_op_update_inc_cc();
1153
}
1154

    
1155
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1156
{
1157
    if (d != OR_TMP0)
1158
        gen_op_mov_TN_reg[ot][0][d]();
1159
    else
1160
        gen_op_ld_T0_A0[ot + s1->mem_index]();
1161
    if (s != OR_TMP1)
1162
        gen_op_mov_TN_reg[ot][1][s]();
1163
    /* for zero counts, flags are not updated, so must do it dynamically */
1164
    if (s1->cc_op != CC_OP_DYNAMIC)
1165
        gen_op_set_cc_op(s1->cc_op);
1166
    
1167
    if (d != OR_TMP0)
1168
        gen_op_shift_T0_T1_cc[ot][op]();
1169
    else
1170
        gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op]();
1171
    if (d != OR_TMP0)
1172
        gen_op_mov_reg_T0[ot][d]();
1173
    s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1174
}
1175

    
1176
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1177
{
1178
    /* currently not optimized */
1179
    gen_op_movl_T1_im(c);
1180
    gen_shift(s1, op, ot, d, OR_TMP1);
1181
}
1182

    
1183
static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1184
{
1185
    int havesib;
1186
    int base, disp;
1187
    int index;
1188
    int scale;
1189
    int opreg;
1190
    int mod, rm, code, override, must_add_seg;
1191

    
1192
    override = s->override;
1193
    must_add_seg = s->addseg;
1194
    if (override >= 0)
1195
        must_add_seg = 1;
1196
    mod = (modrm >> 6) & 3;
1197
    rm = modrm & 7;
1198

    
1199
    if (s->aflag) {
1200

    
1201
        havesib = 0;
1202
        base = rm;
1203
        index = 0;
1204
        scale = 0;
1205
        
1206
        if (base == 4) {
1207
            havesib = 1;
1208
            code = ldub_code(s->pc++);
1209
            scale = (code >> 6) & 3;
1210
            index = (code >> 3) & 7;
1211
            base = code & 7;
1212
        }
1213

    
1214
        switch (mod) {
1215
        case 0:
1216
            if (base == 5) {
1217
                base = -1;
1218
                disp = ldl_code(s->pc);
1219
                s->pc += 4;
1220
            } else {
1221
                disp = 0;
1222
            }
1223
            break;
1224
        case 1:
1225
            disp = (int8_t)ldub_code(s->pc++);
1226
            break;
1227
        default:
1228
        case 2:
1229
            disp = ldl_code(s->pc);
1230
            s->pc += 4;
1231
            break;
1232
        }
1233
        
1234
        if (base >= 0) {
1235
            /* for correct popl handling with esp */
1236
            if (base == 4 && s->popl_esp_hack)
1237
                disp += s->popl_esp_hack;
1238
            gen_op_movl_A0_reg[base]();
1239
            if (disp != 0)
1240
                gen_op_addl_A0_im(disp);
1241
        } else {
1242
            gen_op_movl_A0_im(disp);
1243
        }
1244
        /* XXX: index == 4 is always invalid */
1245
        if (havesib && (index != 4 || scale != 0)) {
1246
            gen_op_addl_A0_reg_sN[scale][index]();
1247
        }
1248
        if (must_add_seg) {
1249
            if (override < 0) {
1250
                if (base == R_EBP || base == R_ESP)
1251
                    override = R_SS;
1252
                else
1253
                    override = R_DS;
1254
            }
1255
            gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1256
        }
1257
    } else {
1258
        switch (mod) {
1259
        case 0:
1260
            if (rm == 6) {
1261
                disp = lduw_code(s->pc);
1262
                s->pc += 2;
1263
                gen_op_movl_A0_im(disp);
1264
                rm = 0; /* avoid SS override */
1265
                goto no_rm;
1266
            } else {
1267
                disp = 0;
1268
            }
1269
            break;
1270
        case 1:
1271
            disp = (int8_t)ldub_code(s->pc++);
1272
            break;
1273
        default:
1274
        case 2:
1275
            disp = lduw_code(s->pc);
1276
            s->pc += 2;
1277
            break;
1278
        }
1279
        switch(rm) {
1280
        case 0:
1281
            gen_op_movl_A0_reg[R_EBX]();
1282
            gen_op_addl_A0_reg_sN[0][R_ESI]();
1283
            break;
1284
        case 1:
1285
            gen_op_movl_A0_reg[R_EBX]();
1286
            gen_op_addl_A0_reg_sN[0][R_EDI]();
1287
            break;
1288
        case 2:
1289
            gen_op_movl_A0_reg[R_EBP]();
1290
            gen_op_addl_A0_reg_sN[0][R_ESI]();
1291
            break;
1292
        case 3:
1293
            gen_op_movl_A0_reg[R_EBP]();
1294
            gen_op_addl_A0_reg_sN[0][R_EDI]();
1295
            break;
1296
        case 4:
1297
            gen_op_movl_A0_reg[R_ESI]();
1298
            break;
1299
        case 5:
1300
            gen_op_movl_A0_reg[R_EDI]();
1301
            break;
1302
        case 6:
1303
            gen_op_movl_A0_reg[R_EBP]();
1304
            break;
1305
        default:
1306
        case 7:
1307
            gen_op_movl_A0_reg[R_EBX]();
1308
            break;
1309
        }
1310
        if (disp != 0)
1311
            gen_op_addl_A0_im(disp);
1312
        gen_op_andl_A0_ffff();
1313
    no_rm:
1314
        if (must_add_seg) {
1315
            if (override < 0) {
1316
                if (rm == 2 || rm == 3 || rm == 6)
1317
                    override = R_SS;
1318
                else
1319
                    override = R_DS;
1320
            }
1321
            gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1322
        }
1323
    }
1324

    
1325
    opreg = OR_A0;
1326
    disp = 0;
1327
    *reg_ptr = opreg;
1328
    *offset_ptr = disp;
1329
}
1330

    
1331
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1332
   OR_TMP0 */
1333
static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1334
{
1335
    int mod, rm, opreg, disp;
1336

    
1337
    mod = (modrm >> 6) & 3;
1338
    rm = modrm & 7;
1339
    if (mod == 3) {
1340
        if (is_store) {
1341
            if (reg != OR_TMP0)
1342
                gen_op_mov_TN_reg[ot][0][reg]();
1343
            gen_op_mov_reg_T0[ot][rm]();
1344
        } else {
1345
            gen_op_mov_TN_reg[ot][0][rm]();
1346
            if (reg != OR_TMP0)
1347
                gen_op_mov_reg_T0[ot][reg]();
1348
        }
1349
    } else {
1350
        gen_lea_modrm(s, modrm, &opreg, &disp);
1351
        if (is_store) {
1352
            if (reg != OR_TMP0)
1353
                gen_op_mov_TN_reg[ot][0][reg]();
1354
            gen_op_st_T0_A0[ot + s->mem_index]();
1355
        } else {
1356
            gen_op_ld_T0_A0[ot + s->mem_index]();
1357
            if (reg != OR_TMP0)
1358
                gen_op_mov_reg_T0[ot][reg]();
1359
        }
1360
    }
1361
}
1362

    
1363
static inline uint32_t insn_get(DisasContext *s, int ot)
1364
{
1365
    uint32_t ret;
1366

    
1367
    switch(ot) {
1368
    case OT_BYTE:
1369
        ret = ldub_code(s->pc);
1370
        s->pc++;
1371
        break;
1372
    case OT_WORD:
1373
        ret = lduw_code(s->pc);
1374
        s->pc += 2;
1375
        break;
1376
    default:
1377
    case OT_LONG:
1378
        ret = ldl_code(s->pc);
1379
        s->pc += 4;
1380
        break;
1381
    }
1382
    return ret;
1383
}
1384

    
1385
static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1386
{
1387
    TranslationBlock *tb;
1388
    int inv, jcc_op;
1389
    GenOpFunc3 *func;
1390

    
1391
    inv = b & 1;
1392
    jcc_op = (b >> 1) & 7;
1393
    
1394
    if (s->jmp_opt) {
1395
        switch(s->cc_op) {
1396
            /* we optimize the cmp/jcc case */
1397
        case CC_OP_SUBB:
1398
        case CC_OP_SUBW:
1399
        case CC_OP_SUBL:
1400
            func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1401
            break;
1402
            
1403
            /* some jumps are easy to compute */
1404
        case CC_OP_ADDB:
1405
        case CC_OP_ADDW:
1406
        case CC_OP_ADDL:
1407
        case CC_OP_ADCB:
1408
        case CC_OP_ADCW:
1409
        case CC_OP_ADCL:
1410
        case CC_OP_SBBB:
1411
        case CC_OP_SBBW:
1412
        case CC_OP_SBBL:
1413
        case CC_OP_LOGICB:
1414
        case CC_OP_LOGICW:
1415
        case CC_OP_LOGICL:
1416
        case CC_OP_INCB:
1417
        case CC_OP_INCW:
1418
        case CC_OP_INCL:
1419
        case CC_OP_DECB:
1420
        case CC_OP_DECW:
1421
        case CC_OP_DECL:
1422
        case CC_OP_SHLB:
1423
        case CC_OP_SHLW:
1424
        case CC_OP_SHLL:
1425
        case CC_OP_SARB:
1426
        case CC_OP_SARW:
1427
        case CC_OP_SARL:
1428
            switch(jcc_op) {
1429
            case JCC_Z:
1430
                func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1431
                break;
1432
            case JCC_S:
1433
                func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1434
                break;
1435
            default:
1436
                func = NULL;
1437
                break;
1438
            }
1439
            break;
1440
        default:
1441
            func = NULL;
1442
            break;
1443
        }
1444

    
1445
        if (s->cc_op != CC_OP_DYNAMIC)
1446
            gen_op_set_cc_op(s->cc_op);
1447

    
1448
        if (!func) {
1449
            gen_setcc_slow[jcc_op]();
1450
            func = gen_op_jcc;
1451
        }
1452
    
1453
        tb = s->tb;
1454
        if (!inv) {
1455
            func((long)tb, val, next_eip);
1456
        } else {
1457
            func((long)tb, next_eip, val);
1458
        }
1459
        s->is_jmp = 3;
1460
    } else {
1461
        if (s->cc_op != CC_OP_DYNAMIC) {
1462
            gen_op_set_cc_op(s->cc_op);
1463
            s->cc_op = CC_OP_DYNAMIC;
1464
        }
1465
        gen_setcc_slow[jcc_op]();
1466
        if (!inv) {
1467
            gen_op_jcc_im(val, next_eip);
1468
        } else {
1469
            gen_op_jcc_im(next_eip, val);
1470
        }
1471
        gen_eob(s);
1472
    }
1473
}
1474

    
1475
static void gen_setcc(DisasContext *s, int b)
1476
{
1477
    int inv, jcc_op;
1478
    GenOpFunc *func;
1479

    
1480
    inv = b & 1;
1481
    jcc_op = (b >> 1) & 7;
1482
    switch(s->cc_op) {
1483
        /* we optimize the cmp/jcc case */
1484
    case CC_OP_SUBB:
1485
    case CC_OP_SUBW:
1486
    case CC_OP_SUBL:
1487
        func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1488
        if (!func)
1489
            goto slow_jcc;
1490
        break;
1491
        
1492
        /* some jumps are easy to compute */
1493
    case CC_OP_ADDB:
1494
    case CC_OP_ADDW:
1495
    case CC_OP_ADDL:
1496
    case CC_OP_LOGICB:
1497
    case CC_OP_LOGICW:
1498
    case CC_OP_LOGICL:
1499
    case CC_OP_INCB:
1500
    case CC_OP_INCW:
1501
    case CC_OP_INCL:
1502
    case CC_OP_DECB:
1503
    case CC_OP_DECW:
1504
    case CC_OP_DECL:
1505
    case CC_OP_SHLB:
1506
    case CC_OP_SHLW:
1507
    case CC_OP_SHLL:
1508
        switch(jcc_op) {
1509
        case JCC_Z:
1510
            func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1511
            break;
1512
        case JCC_S:
1513
            func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1514
            break;
1515
        default:
1516
            goto slow_jcc;
1517
        }
1518
        break;
1519
    default:
1520
    slow_jcc:
1521
        if (s->cc_op != CC_OP_DYNAMIC)
1522
            gen_op_set_cc_op(s->cc_op);
1523
        func = gen_setcc_slow[jcc_op];
1524
        break;
1525
    }
1526
    func();
1527
    if (inv) {
1528
        gen_op_xor_T0_1();
1529
    }
1530
}
1531

    
1532
/* move T0 to seg_reg and compute if the CPU state may change. Never
1533
   call this function with seg_reg == R_CS */
1534
static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
1535
{
1536
    if (s->pe && !s->vm86) {
1537
        /* XXX: optimize by finding processor state dynamically */
1538
        if (s->cc_op != CC_OP_DYNAMIC)
1539
            gen_op_set_cc_op(s->cc_op);
1540
        gen_op_jmp_im(cur_eip);
1541
        gen_op_movl_seg_T0(seg_reg);
1542
    } else {
1543
        gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1544
    }
1545
    /* abort translation because the register may have a non zero base
1546
       or because ss32 may change. For R_SS, translation must always
1547
       stop as a special handling must be done to disable hardware
1548
       interrupts for the next instruction */
1549
    if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))
1550
        s->is_jmp = 3;
1551
}
1552

    
1553
static inline void gen_stack_update(DisasContext *s, int addend)
1554
{
1555
    if (s->ss32) {
1556
        if (addend == 2)
1557
            gen_op_addl_ESP_2();
1558
        else if (addend == 4)
1559
            gen_op_addl_ESP_4();
1560
        else 
1561
            gen_op_addl_ESP_im(addend);
1562
    } else {
1563
        if (addend == 2)
1564
            gen_op_addw_ESP_2();
1565
        else if (addend == 4)
1566
            gen_op_addw_ESP_4();
1567
        else
1568
            gen_op_addw_ESP_im(addend);
1569
    }
1570
}
1571

    
1572
/* generate a push. It depends on ss32, addseg and dflag */
1573
static void gen_push_T0(DisasContext *s)
1574
{
1575
    gen_op_movl_A0_reg[R_ESP]();
1576
    if (!s->dflag)
1577
        gen_op_subl_A0_2();
1578
    else
1579
        gen_op_subl_A0_4();
1580
    if (s->ss32) {
1581
        if (s->addseg) {
1582
            gen_op_movl_T1_A0();
1583
            gen_op_addl_A0_SS();
1584
        }
1585
    } else {
1586
        gen_op_andl_A0_ffff();
1587
        gen_op_movl_T1_A0();
1588
        gen_op_addl_A0_SS();
1589
    }
1590
    gen_op_st_T0_A0[s->dflag + 1 + s->mem_index]();
1591
    if (s->ss32 && !s->addseg)
1592
        gen_op_movl_ESP_A0();
1593
    else
1594
        gen_op_mov_reg_T1[s->ss32 + 1][R_ESP]();
1595
}
1596

    
1597
/* generate a push. It depends on ss32, addseg and dflag */
1598
/* slower version for T1, only used for call Ev */
1599
static void gen_push_T1(DisasContext *s)
1600
{
1601
    gen_op_movl_A0_reg[R_ESP]();
1602
    if (!s->dflag)
1603
        gen_op_subl_A0_2();
1604
    else
1605
        gen_op_subl_A0_4();
1606
    if (s->ss32) {
1607
        if (s->addseg) {
1608
            gen_op_addl_A0_SS();
1609
        }
1610
    } else {
1611
        gen_op_andl_A0_ffff();
1612
        gen_op_addl_A0_SS();
1613
    }
1614
    gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
1615
    
1616
    if (s->ss32 && !s->addseg)
1617
        gen_op_movl_ESP_A0();
1618
    else
1619
        gen_stack_update(s, (-2) << s->dflag);
1620
}
1621

    
1622
/* two step pop is necessary for precise exceptions */
1623
static void gen_pop_T0(DisasContext *s)
1624
{
1625
    gen_op_movl_A0_reg[R_ESP]();
1626
    if (s->ss32) {
1627
        if (s->addseg)
1628
            gen_op_addl_A0_SS();
1629
    } else {
1630
        gen_op_andl_A0_ffff();
1631
        gen_op_addl_A0_SS();
1632
    }
1633
    gen_op_ld_T0_A0[s->dflag + 1 + s->mem_index]();
1634
}
1635

    
1636
static void gen_pop_update(DisasContext *s)
1637
{
1638
    gen_stack_update(s, 2 << s->dflag);
1639
}
1640

    
1641
static void gen_stack_A0(DisasContext *s)
1642
{
1643
    gen_op_movl_A0_ESP();
1644
    if (!s->ss32)
1645
        gen_op_andl_A0_ffff();
1646
    gen_op_movl_T1_A0();
1647
    if (s->addseg)
1648
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1649
}
1650

    
1651
/* NOTE: wrap around in 16 bit not fully handled */
1652
static void gen_pusha(DisasContext *s)
1653
{
1654
    int i;
1655
    gen_op_movl_A0_ESP();
1656
    gen_op_addl_A0_im(-16 <<  s->dflag);
1657
    if (!s->ss32)
1658
        gen_op_andl_A0_ffff();
1659
    gen_op_movl_T1_A0();
1660
    if (s->addseg)
1661
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1662
    for(i = 0;i < 8; i++) {
1663
        gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1664
        gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1665
        gen_op_addl_A0_im(2 <<  s->dflag);
1666
    }
1667
    gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1668
}
1669

    
1670
/* NOTE: wrap around in 16 bit not fully handled */
1671
static void gen_popa(DisasContext *s)
1672
{
1673
    int i;
1674
    gen_op_movl_A0_ESP();
1675
    if (!s->ss32)
1676
        gen_op_andl_A0_ffff();
1677
    gen_op_movl_T1_A0();
1678
    gen_op_addl_T1_im(16 <<  s->dflag);
1679
    if (s->addseg)
1680
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1681
    for(i = 0;i < 8; i++) {
1682
        /* ESP is not reloaded */
1683
        if (i != 3) {
1684
            gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1685
            gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1686
        }
1687
        gen_op_addl_A0_im(2 <<  s->dflag);
1688
    }
1689
    gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1690
}
1691

    
1692
/* NOTE: wrap around in 16 bit not fully handled */
1693
/* XXX: check this */
1694
static void gen_enter(DisasContext *s, int esp_addend, int level)
1695
{
1696
    int ot, level1, addend, opsize;
1697

    
1698
    ot = s->dflag + OT_WORD;
1699
    level &= 0x1f;
1700
    level1 = level;
1701
    opsize = 2 << s->dflag;
1702

    
1703
    gen_op_movl_A0_ESP();
1704
    gen_op_addl_A0_im(-opsize);
1705
    if (!s->ss32)
1706
        gen_op_andl_A0_ffff();
1707
    gen_op_movl_T1_A0();
1708
    if (s->addseg)
1709
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1710
    /* push bp */
1711
    gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1712
    gen_op_st_T0_A0[ot + s->mem_index]();
1713
    if (level) {
1714
        while (level--) {
1715
            gen_op_addl_A0_im(-opsize);
1716
            gen_op_addl_T0_im(-opsize);
1717
            gen_op_st_T0_A0[ot + s->mem_index]();
1718
        }
1719
        gen_op_addl_A0_im(-opsize);
1720
        gen_op_st_T1_A0[ot + s->mem_index]();
1721
    }
1722
    gen_op_mov_reg_T1[ot][R_EBP]();
1723
    addend = -esp_addend;
1724
    if (level1)
1725
        addend -= opsize * (level1 + 1);
1726
    gen_op_addl_T1_im(addend);
1727
    gen_op_mov_reg_T1[ot][R_ESP]();
1728
}
1729

    
1730
static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1731
{
1732
    if (s->cc_op != CC_OP_DYNAMIC)
1733
        gen_op_set_cc_op(s->cc_op);
1734
    gen_op_jmp_im(cur_eip);
1735
    gen_op_raise_exception(trapno);
1736
    s->is_jmp = 3;
1737
}
1738

    
1739
/* an interrupt is different from an exception because of the
1740
   priviledge checks */
1741
static void gen_interrupt(DisasContext *s, int intno, 
1742
                          unsigned int cur_eip, unsigned int next_eip)
1743
{
1744
    if (s->cc_op != CC_OP_DYNAMIC)
1745
        gen_op_set_cc_op(s->cc_op);
1746
    gen_op_jmp_im(cur_eip);
1747
    gen_op_raise_interrupt(intno, next_eip);
1748
    s->is_jmp = 3;
1749
}
1750

    
1751
static void gen_debug(DisasContext *s, unsigned int cur_eip)
1752
{
1753
    if (s->cc_op != CC_OP_DYNAMIC)
1754
        gen_op_set_cc_op(s->cc_op);
1755
    gen_op_jmp_im(cur_eip);
1756
    gen_op_debug();
1757
    s->is_jmp = 3;
1758
}
1759

    
1760
/* generate a generic end of block. Trace exception is also generated
1761
   if needed */
1762
static void gen_eob(DisasContext *s)
1763
{
1764
    if (s->cc_op != CC_OP_DYNAMIC)
1765
        gen_op_set_cc_op(s->cc_op);
1766
    if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
1767
        gen_op_reset_inhibit_irq();
1768
    }
1769
    if (s->singlestep_enabled) {
1770
        gen_op_debug();
1771
    } else if (s->tf) {
1772
        gen_op_raise_exception(EXCP01_SSTP);
1773
    } else {
1774
        gen_op_movl_T0_0();
1775
        gen_op_exit_tb();
1776
    }
1777
    s->is_jmp = 3;
1778
}
1779

    
1780
/* generate a jump to eip. No segment change must happen before as a
1781
   direct call to the next block may occur */
1782
static void gen_jmp(DisasContext *s, unsigned int eip)
1783
{
1784
    TranslationBlock *tb = s->tb;
1785

    
1786
    if (s->jmp_opt) {
1787
        if (s->cc_op != CC_OP_DYNAMIC)
1788
            gen_op_set_cc_op(s->cc_op);
1789
        gen_op_jmp((long)tb, eip);
1790
        s->is_jmp = 3;
1791
    } else {
1792
        gen_op_jmp_im(eip);
1793
        gen_eob(s);
1794
    }
1795
}
1796

    
1797
/* convert one instruction. s->is_jmp is set if the translation must
1798
   be stopped. Return the next pc value */
1799
static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1800
{
1801
    int b, prefixes, aflag, dflag;
1802
    int shift, ot;
1803
    int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1804
    unsigned int next_eip;
1805

    
1806
    s->pc = pc_start;
1807
    prefixes = 0;
1808
    aflag = s->code32;
1809
    dflag = s->code32;
1810
    s->override = -1;
1811
 next_byte:
1812
    b = ldub_code(s->pc);
1813
    s->pc++;
1814
    /* check prefixes */
1815
    switch (b) {
1816
    case 0xf3:
1817
        prefixes |= PREFIX_REPZ;
1818
        goto next_byte;
1819
    case 0xf2:
1820
        prefixes |= PREFIX_REPNZ;
1821
        goto next_byte;
1822
    case 0xf0:
1823
        prefixes |= PREFIX_LOCK;
1824
        goto next_byte;
1825
    case 0x2e:
1826
        s->override = R_CS;
1827
        goto next_byte;
1828
    case 0x36:
1829
        s->override = R_SS;
1830
        goto next_byte;
1831
    case 0x3e:
1832
        s->override = R_DS;
1833
        goto next_byte;
1834
    case 0x26:
1835
        s->override = R_ES;
1836
        goto next_byte;
1837
    case 0x64:
1838
        s->override = R_FS;
1839
        goto next_byte;
1840
    case 0x65:
1841
        s->override = R_GS;
1842
        goto next_byte;
1843
    case 0x66:
1844
        prefixes |= PREFIX_DATA;
1845
        goto next_byte;
1846
    case 0x67:
1847
        prefixes |= PREFIX_ADR;
1848
        goto next_byte;
1849
    }
1850

    
1851
    if (prefixes & PREFIX_DATA)
1852
        dflag ^= 1;
1853
    if (prefixes & PREFIX_ADR)
1854
        aflag ^= 1;
1855

    
1856
    s->prefix = prefixes;
1857
    s->aflag = aflag;
1858
    s->dflag = dflag;
1859

    
1860
    /* lock generation */
1861
    if (prefixes & PREFIX_LOCK)
1862
        gen_op_lock();
1863

    
1864
    /* now check op code */
1865
 reswitch:
1866
    switch(b) {
1867
    case 0x0f:
1868
        /**************************/
1869
        /* extended op code */
1870
        b = ldub_code(s->pc++) | 0x100;
1871
        goto reswitch;
1872
        
1873
        /**************************/
1874
        /* arith & logic */
1875
    case 0x00 ... 0x05:
1876
    case 0x08 ... 0x0d:
1877
    case 0x10 ... 0x15:
1878
    case 0x18 ... 0x1d:
1879
    case 0x20 ... 0x25:
1880
    case 0x28 ... 0x2d:
1881
    case 0x30 ... 0x35:
1882
    case 0x38 ... 0x3d:
1883
        {
1884
            int op, f, val;
1885
            op = (b >> 3) & 7;
1886
            f = (b >> 1) & 3;
1887

    
1888
            if ((b & 1) == 0)
1889
                ot = OT_BYTE;
1890
            else
1891
                ot = dflag ? OT_LONG : OT_WORD;
1892
            
1893
            switch(f) {
1894
            case 0: /* OP Ev, Gv */
1895
                modrm = ldub_code(s->pc++);
1896
                reg = ((modrm >> 3) & 7);
1897
                mod = (modrm >> 6) & 3;
1898
                rm = modrm & 7;
1899
                if (mod != 3) {
1900
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1901
                    opreg = OR_TMP0;
1902
                } else if (op == OP_XORL && rm == reg) {
1903
                xor_zero:
1904
                    /* xor reg, reg optimisation */
1905
                    gen_op_movl_T0_0();
1906
                    s->cc_op = CC_OP_LOGICB + ot;
1907
                    gen_op_mov_reg_T0[ot][reg]();
1908
                    gen_op_update1_cc();
1909
                    break;
1910
                } else {
1911
                    opreg = rm;
1912
                }
1913
                gen_op_mov_TN_reg[ot][1][reg]();
1914
                gen_op(s, op, ot, opreg);
1915
                break;
1916
            case 1: /* OP Gv, Ev */
1917
                modrm = ldub_code(s->pc++);
1918
                mod = (modrm >> 6) & 3;
1919
                reg = ((modrm >> 3) & 7);
1920
                rm = modrm & 7;
1921
                if (mod != 3) {
1922
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1923
                    gen_op_ld_T1_A0[ot + s->mem_index]();
1924
                } else if (op == OP_XORL && rm == reg) {
1925
                    goto xor_zero;
1926
                } else {
1927
                    gen_op_mov_TN_reg[ot][1][rm]();
1928
                }
1929
                gen_op(s, op, ot, reg);
1930
                break;
1931
            case 2: /* OP A, Iv */
1932
                val = insn_get(s, ot);
1933
                gen_op_movl_T1_im(val);
1934
                gen_op(s, op, ot, OR_EAX);
1935
                break;
1936
            }
1937
        }
1938
        break;
1939

    
1940
    case 0x80: /* GRP1 */
1941
    case 0x81:
1942
    case 0x83:
1943
        {
1944
            int val;
1945

    
1946
            if ((b & 1) == 0)
1947
                ot = OT_BYTE;
1948
            else
1949
                ot = dflag ? OT_LONG : OT_WORD;
1950
            
1951
            modrm = ldub_code(s->pc++);
1952
            mod = (modrm >> 6) & 3;
1953
            rm = modrm & 7;
1954
            op = (modrm >> 3) & 7;
1955
            
1956
            if (mod != 3) {
1957
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1958
                opreg = OR_TMP0;
1959
            } else {
1960
                opreg = rm + OR_EAX;
1961
            }
1962

    
1963
            switch(b) {
1964
            default:
1965
            case 0x80:
1966
            case 0x81:
1967
                val = insn_get(s, ot);
1968
                break;
1969
            case 0x83:
1970
                val = (int8_t)insn_get(s, OT_BYTE);
1971
                break;
1972
            }
1973
            gen_op_movl_T1_im(val);
1974
            gen_op(s, op, ot, opreg);
1975
        }
1976
        break;
1977

    
1978
        /**************************/
1979
        /* inc, dec, and other misc arith */
1980
    case 0x40 ... 0x47: /* inc Gv */
1981
        ot = dflag ? OT_LONG : OT_WORD;
1982
        gen_inc(s, ot, OR_EAX + (b & 7), 1);
1983
        break;
1984
    case 0x48 ... 0x4f: /* dec Gv */
1985
        ot = dflag ? OT_LONG : OT_WORD;
1986
        gen_inc(s, ot, OR_EAX + (b & 7), -1);
1987
        break;
1988
    case 0xf6: /* GRP3 */
1989
    case 0xf7:
1990
        if ((b & 1) == 0)
1991
            ot = OT_BYTE;
1992
        else
1993
            ot = dflag ? OT_LONG : OT_WORD;
1994

    
1995
        modrm = ldub_code(s->pc++);
1996
        mod = (modrm >> 6) & 3;
1997
        rm = modrm & 7;
1998
        op = (modrm >> 3) & 7;
1999
        if (mod != 3) {
2000
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2001
            gen_op_ld_T0_A0[ot + s->mem_index]();
2002
        } else {
2003
            gen_op_mov_TN_reg[ot][0][rm]();
2004
        }
2005

    
2006
        switch(op) {
2007
        case 0: /* test */
2008
            val = insn_get(s, ot);
2009
            gen_op_movl_T1_im(val);
2010
            gen_op_testl_T0_T1_cc();
2011
            s->cc_op = CC_OP_LOGICB + ot;
2012
            break;
2013
        case 2: /* not */
2014
            gen_op_notl_T0();
2015
            if (mod != 3) {
2016
                gen_op_st_T0_A0[ot + s->mem_index]();
2017
            } else {
2018
                gen_op_mov_reg_T0[ot][rm]();
2019
            }
2020
            break;
2021
        case 3: /* neg */
2022
            gen_op_negl_T0();
2023
            if (mod != 3) {
2024
                gen_op_st_T0_A0[ot + s->mem_index]();
2025
            } else {
2026
                gen_op_mov_reg_T0[ot][rm]();
2027
            }
2028
            gen_op_update_neg_cc();
2029
            s->cc_op = CC_OP_SUBB + ot;
2030
            break;
2031
        case 4: /* mul */
2032
            switch(ot) {
2033
            case OT_BYTE:
2034
                gen_op_mulb_AL_T0();
2035
                s->cc_op = CC_OP_MULB;
2036
                break;
2037
            case OT_WORD:
2038
                gen_op_mulw_AX_T0();
2039
                s->cc_op = CC_OP_MULW;
2040
                break;
2041
            default:
2042
            case OT_LONG:
2043
                gen_op_mull_EAX_T0();
2044
                s->cc_op = CC_OP_MULL;
2045
                break;
2046
            }
2047
            break;
2048
        case 5: /* imul */
2049
            switch(ot) {
2050
            case OT_BYTE:
2051
                gen_op_imulb_AL_T0();
2052
                s->cc_op = CC_OP_MULB;
2053
                break;
2054
            case OT_WORD:
2055
                gen_op_imulw_AX_T0();
2056
                s->cc_op = CC_OP_MULW;
2057
                break;
2058
            default:
2059
            case OT_LONG:
2060
                gen_op_imull_EAX_T0();
2061
                s->cc_op = CC_OP_MULL;
2062
                break;
2063
            }
2064
            break;
2065
        case 6: /* div */
2066
            switch(ot) {
2067
            case OT_BYTE:
2068
                gen_op_divb_AL_T0(pc_start - s->cs_base);
2069
                break;
2070
            case OT_WORD:
2071
                gen_op_divw_AX_T0(pc_start - s->cs_base);
2072
                break;
2073
            default:
2074
            case OT_LONG:
2075
                gen_op_divl_EAX_T0(pc_start - s->cs_base);
2076
                break;
2077
            }
2078
            break;
2079
        case 7: /* idiv */
2080
            switch(ot) {
2081
            case OT_BYTE:
2082
                gen_op_idivb_AL_T0(pc_start - s->cs_base);
2083
                break;
2084
            case OT_WORD:
2085
                gen_op_idivw_AX_T0(pc_start - s->cs_base);
2086
                break;
2087
            default:
2088
            case OT_LONG:
2089
                gen_op_idivl_EAX_T0(pc_start - s->cs_base);
2090
                break;
2091
            }
2092
            break;
2093
        default:
2094
            goto illegal_op;
2095
        }
2096
        break;
2097

    
2098
    case 0xfe: /* GRP4 */
2099
    case 0xff: /* GRP5 */
2100
        if ((b & 1) == 0)
2101
            ot = OT_BYTE;
2102
        else
2103
            ot = dflag ? OT_LONG : OT_WORD;
2104

    
2105
        modrm = ldub_code(s->pc++);
2106
        mod = (modrm >> 6) & 3;
2107
        rm = modrm & 7;
2108
        op = (modrm >> 3) & 7;
2109
        if (op >= 2 && b == 0xfe) {
2110
            goto illegal_op;
2111
        }
2112
        if (mod != 3) {
2113
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2114
            if (op >= 2 && op != 3 && op != 5)
2115
                gen_op_ld_T0_A0[ot + s->mem_index]();
2116
        } else {
2117
            gen_op_mov_TN_reg[ot][0][rm]();
2118
        }
2119

    
2120
        switch(op) {
2121
        case 0: /* inc Ev */
2122
            if (mod != 3)
2123
                opreg = OR_TMP0;
2124
            else
2125
                opreg = rm;
2126
            gen_inc(s, ot, opreg, 1);
2127
            break;
2128
        case 1: /* dec Ev */
2129
            if (mod != 3)
2130
                opreg = OR_TMP0;
2131
            else
2132
                opreg = rm;
2133
            gen_inc(s, ot, opreg, -1);
2134
            break;
2135
        case 2: /* call Ev */
2136
            /* XXX: optimize if memory (no 'and' is necessary) */
2137
            if (s->dflag == 0)
2138
                gen_op_andl_T0_ffff();
2139
            next_eip = s->pc - s->cs_base;
2140
            gen_op_movl_T1_im(next_eip);
2141
            gen_push_T1(s);
2142
            gen_op_jmp_T0();
2143
            gen_eob(s);
2144
            break;
2145
        case 3: /* lcall Ev */
2146
            gen_op_ld_T1_A0[ot + s->mem_index]();
2147
            gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2148
            gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2149
        do_lcall:
2150
            if (s->pe && !s->vm86) {
2151
                if (s->cc_op != CC_OP_DYNAMIC)
2152
                    gen_op_set_cc_op(s->cc_op);
2153
                gen_op_jmp_im(pc_start - s->cs_base);
2154
                gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
2155
            } else {
2156
                gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
2157
            }
2158
            gen_eob(s);
2159
            break;
2160
        case 4: /* jmp Ev */
2161
            if (s->dflag == 0)
2162
                gen_op_andl_T0_ffff();
2163
            gen_op_jmp_T0();
2164
            gen_eob(s);
2165
            break;
2166
        case 5: /* ljmp Ev */
2167
            gen_op_ld_T1_A0[ot + s->mem_index]();
2168
            gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2169
            gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2170
        do_ljmp:
2171
            if (s->pe && !s->vm86) {
2172
                if (s->cc_op != CC_OP_DYNAMIC)
2173
                    gen_op_set_cc_op(s->cc_op);
2174
                gen_op_jmp_im(pc_start - s->cs_base);
2175
                gen_op_ljmp_protected_T0_T1(s->pc - s->cs_base);
2176
            } else {
2177
                gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
2178
                gen_op_movl_T0_T1();
2179
                gen_op_jmp_T0();
2180
            }
2181
            gen_eob(s);
2182
            break;
2183
        case 6: /* push Ev */
2184
            gen_push_T0(s);
2185
            break;
2186
        default:
2187
            goto illegal_op;
2188
        }
2189
        break;
2190

    
2191
    case 0x84: /* test Ev, Gv */
2192
    case 0x85: 
2193
        if ((b & 1) == 0)
2194
            ot = OT_BYTE;
2195
        else
2196
            ot = dflag ? OT_LONG : OT_WORD;
2197

    
2198
        modrm = ldub_code(s->pc++);
2199
        mod = (modrm >> 6) & 3;
2200
        rm = modrm & 7;
2201
        reg = (modrm >> 3) & 7;
2202
        
2203
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2204
        gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
2205
        gen_op_testl_T0_T1_cc();
2206
        s->cc_op = CC_OP_LOGICB + ot;
2207
        break;
2208
        
2209
    case 0xa8: /* test eAX, Iv */
2210
    case 0xa9:
2211
        if ((b & 1) == 0)
2212
            ot = OT_BYTE;
2213
        else
2214
            ot = dflag ? OT_LONG : OT_WORD;
2215
        val = insn_get(s, ot);
2216

    
2217
        gen_op_mov_TN_reg[ot][0][OR_EAX]();
2218
        gen_op_movl_T1_im(val);
2219
        gen_op_testl_T0_T1_cc();
2220
        s->cc_op = CC_OP_LOGICB + ot;
2221
        break;
2222
        
2223
    case 0x98: /* CWDE/CBW */
2224
        if (dflag)
2225
            gen_op_movswl_EAX_AX();
2226
        else
2227
            gen_op_movsbw_AX_AL();
2228
        break;
2229
    case 0x99: /* CDQ/CWD */
2230
        if (dflag)
2231
            gen_op_movslq_EDX_EAX();
2232
        else
2233
            gen_op_movswl_DX_AX();
2234
        break;
2235
    case 0x1af: /* imul Gv, Ev */
2236
    case 0x69: /* imul Gv, Ev, I */
2237
    case 0x6b:
2238
        ot = dflag ? OT_LONG : OT_WORD;
2239
        modrm = ldub_code(s->pc++);
2240
        reg = ((modrm >> 3) & 7) + OR_EAX;
2241
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2242
        if (b == 0x69) {
2243
            val = insn_get(s, ot);
2244
            gen_op_movl_T1_im(val);
2245
        } else if (b == 0x6b) {
2246
            val = insn_get(s, OT_BYTE);
2247
            gen_op_movl_T1_im(val);
2248
        } else {
2249
            gen_op_mov_TN_reg[ot][1][reg]();
2250
        }
2251

    
2252
        if (ot == OT_LONG) {
2253
            gen_op_imull_T0_T1();
2254
        } else {
2255
            gen_op_imulw_T0_T1();
2256
        }
2257
        gen_op_mov_reg_T0[ot][reg]();
2258
        s->cc_op = CC_OP_MULB + ot;
2259
        break;
2260
    case 0x1c0:
2261
    case 0x1c1: /* xadd Ev, Gv */
2262
        if ((b & 1) == 0)
2263
            ot = OT_BYTE;
2264
        else
2265
            ot = dflag ? OT_LONG : OT_WORD;
2266
        modrm = ldub_code(s->pc++);
2267
        reg = (modrm >> 3) & 7;
2268
        mod = (modrm >> 6) & 3;
2269
        if (mod == 3) {
2270
            rm = modrm & 7;
2271
            gen_op_mov_TN_reg[ot][0][reg]();
2272
            gen_op_mov_TN_reg[ot][1][rm]();
2273
            gen_op_addl_T0_T1();
2274
            gen_op_mov_reg_T1[ot][reg]();
2275
            gen_op_mov_reg_T0[ot][rm]();
2276
        } else {
2277
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2278
            gen_op_mov_TN_reg[ot][0][reg]();
2279
            gen_op_ld_T1_A0[ot + s->mem_index]();
2280
            gen_op_addl_T0_T1();
2281
            gen_op_st_T0_A0[ot + s->mem_index]();
2282
            gen_op_mov_reg_T1[ot][reg]();
2283
        }
2284
        gen_op_update2_cc();
2285
        s->cc_op = CC_OP_ADDB + ot;
2286
        break;
2287
    case 0x1b0:
2288
    case 0x1b1: /* cmpxchg Ev, Gv */
2289
        if ((b & 1) == 0)
2290
            ot = OT_BYTE;
2291
        else
2292
            ot = dflag ? OT_LONG : OT_WORD;
2293
        modrm = ldub_code(s->pc++);
2294
        reg = (modrm >> 3) & 7;
2295
        mod = (modrm >> 6) & 3;
2296
        gen_op_mov_TN_reg[ot][1][reg]();
2297
        if (mod == 3) {
2298
            rm = modrm & 7;
2299
            gen_op_mov_TN_reg[ot][0][rm]();
2300
            gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
2301
            gen_op_mov_reg_T0[ot][rm]();
2302
        } else {
2303
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2304
            gen_op_ld_T0_A0[ot + s->mem_index]();
2305
            gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot + s->mem_index]();
2306
        }
2307
        s->cc_op = CC_OP_SUBB + ot;
2308
        break;
2309
    case 0x1c7: /* cmpxchg8b */
2310
        modrm = ldub_code(s->pc++);
2311
        mod = (modrm >> 6) & 3;
2312
        if (mod == 3)
2313
            goto illegal_op;
2314
        if (s->cc_op != CC_OP_DYNAMIC)
2315
            gen_op_set_cc_op(s->cc_op);
2316
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2317
        gen_op_cmpxchg8b();
2318
        s->cc_op = CC_OP_EFLAGS;
2319
        break;
2320
        
2321
        /**************************/
2322
        /* push/pop */
2323
    case 0x50 ... 0x57: /* push */
2324
        gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
2325
        gen_push_T0(s);
2326
        break;
2327
    case 0x58 ... 0x5f: /* pop */
2328
        ot = dflag ? OT_LONG : OT_WORD;
2329
        gen_pop_T0(s);
2330
        /* NOTE: order is important for pop %sp */
2331
        gen_pop_update(s);
2332
        gen_op_mov_reg_T0[ot][b & 7]();
2333
        break;
2334
    case 0x60: /* pusha */
2335
        gen_pusha(s);
2336
        break;
2337
    case 0x61: /* popa */
2338
        gen_popa(s);
2339
        break;
2340
    case 0x68: /* push Iv */
2341
    case 0x6a:
2342
        ot = dflag ? OT_LONG : OT_WORD;
2343
        if (b == 0x68)
2344
            val = insn_get(s, ot);
2345
        else
2346
            val = (int8_t)insn_get(s, OT_BYTE);
2347
        gen_op_movl_T0_im(val);
2348
        gen_push_T0(s);
2349
        break;
2350
    case 0x8f: /* pop Ev */
2351
        ot = dflag ? OT_LONG : OT_WORD;
2352
        modrm = ldub_code(s->pc++);
2353
        mod = (modrm >> 6) & 3;
2354
        gen_pop_T0(s);
2355
        if (mod == 3) {
2356
            /* NOTE: order is important for pop %sp */
2357
            gen_pop_update(s);
2358
            rm = modrm & 7;
2359
            gen_op_mov_reg_T0[ot][rm]();
2360
        } else {
2361
            /* NOTE: order is important too for MMU exceptions */
2362
            s->popl_esp_hack = 2 << dflag;
2363
            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2364
            s->popl_esp_hack = 0;
2365
            gen_pop_update(s);
2366
        }
2367
        break;
2368
    case 0xc8: /* enter */
2369
        {
2370
            int level;
2371
            val = lduw_code(s->pc);
2372
            s->pc += 2;
2373
            level = ldub_code(s->pc++);
2374
            gen_enter(s, val, level);
2375
        }
2376
        break;
2377
    case 0xc9: /* leave */
2378
        /* XXX: exception not precise (ESP is updated before potential exception) */
2379
        if (s->ss32) {
2380
            gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2381
            gen_op_mov_reg_T0[OT_LONG][R_ESP]();
2382
        } else {
2383
            gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
2384
            gen_op_mov_reg_T0[OT_WORD][R_ESP]();
2385
        }
2386
        gen_pop_T0(s);
2387
        ot = dflag ? OT_LONG : OT_WORD;
2388
        gen_op_mov_reg_T0[ot][R_EBP]();
2389
        gen_pop_update(s);
2390
        break;
2391
    case 0x06: /* push es */
2392
    case 0x0e: /* push cs */
2393
    case 0x16: /* push ss */
2394
    case 0x1e: /* push ds */
2395
        gen_op_movl_T0_seg(b >> 3);
2396
        gen_push_T0(s);
2397
        break;
2398
    case 0x1a0: /* push fs */
2399
    case 0x1a8: /* push gs */
2400
        gen_op_movl_T0_seg((b >> 3) & 7);
2401
        gen_push_T0(s);
2402
        break;
2403
    case 0x07: /* pop es */
2404
    case 0x17: /* pop ss */
2405
    case 0x1f: /* pop ds */
2406
        reg = b >> 3;
2407
        gen_pop_T0(s);
2408
        gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2409
        gen_pop_update(s);
2410
        if (reg == R_SS) {
2411
            /* if reg == SS, inhibit interrupts/trace. */
2412
            /* If several instructions disable interrupts, only the
2413
               _first_ does it */
2414
            if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2415
                gen_op_set_inhibit_irq();
2416
            s->tf = 0;
2417
        }
2418
        if (s->is_jmp) {
2419
            gen_op_jmp_im(s->pc - s->cs_base);
2420
            gen_eob(s);
2421
        }
2422
        break;
2423
    case 0x1a1: /* pop fs */
2424
    case 0x1a9: /* pop gs */
2425
        gen_pop_T0(s);
2426
        gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
2427
        gen_pop_update(s);
2428
        if (s->is_jmp) {
2429
            gen_op_jmp_im(s->pc - s->cs_base);
2430
            gen_eob(s);
2431
        }
2432
        break;
2433

    
2434
        /**************************/
2435
        /* mov */
2436
    case 0x88:
2437
    case 0x89: /* mov Gv, Ev */
2438
        if ((b & 1) == 0)
2439
            ot = OT_BYTE;
2440
        else
2441
            ot = dflag ? OT_LONG : OT_WORD;
2442
        modrm = ldub_code(s->pc++);
2443
        reg = (modrm >> 3) & 7;
2444
        
2445
        /* generate a generic store */
2446
        gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2447
        break;
2448
    case 0xc6:
2449
    case 0xc7: /* mov Ev, Iv */
2450
        if ((b & 1) == 0)
2451
            ot = OT_BYTE;
2452
        else
2453
            ot = dflag ? OT_LONG : OT_WORD;
2454
        modrm = ldub_code(s->pc++);
2455
        mod = (modrm >> 6) & 3;
2456
        if (mod != 3)
2457
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2458
        val = insn_get(s, ot);
2459
        gen_op_movl_T0_im(val);
2460
        if (mod != 3)
2461
            gen_op_st_T0_A0[ot + s->mem_index]();
2462
        else
2463
            gen_op_mov_reg_T0[ot][modrm & 7]();
2464
        break;
2465
    case 0x8a:
2466
    case 0x8b: /* mov Ev, Gv */
2467
        if ((b & 1) == 0)
2468
            ot = OT_BYTE;
2469
        else
2470
            ot = dflag ? OT_LONG : OT_WORD;
2471
        modrm = ldub_code(s->pc++);
2472
        reg = (modrm >> 3) & 7;
2473
        
2474
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2475
        gen_op_mov_reg_T0[ot][reg]();
2476
        break;
2477
    case 0x8e: /* mov seg, Gv */
2478
        modrm = ldub_code(s->pc++);
2479
        reg = (modrm >> 3) & 7;
2480
        if (reg >= 6 || reg == R_CS)
2481
            goto illegal_op;
2482
        gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2483
        gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2484
        if (reg == R_SS) {
2485
            /* if reg == SS, inhibit interrupts/trace */
2486
            /* If several instructions disable interrupts, only the
2487
               _first_ does it */
2488
            if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2489
                gen_op_set_inhibit_irq();
2490
            s->tf = 0;
2491
        }
2492
        if (s->is_jmp) {
2493
            gen_op_jmp_im(s->pc - s->cs_base);
2494
            gen_eob(s);
2495
        }
2496
        break;
2497
    case 0x8c: /* mov Gv, seg */
2498
        modrm = ldub_code(s->pc++);
2499
        reg = (modrm >> 3) & 7;
2500
        mod = (modrm >> 6) & 3;
2501
        if (reg >= 6)
2502
            goto illegal_op;
2503
        gen_op_movl_T0_seg(reg);
2504
        ot = OT_WORD;
2505
        if (mod == 3 && dflag)
2506
            ot = OT_LONG;
2507
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2508
        break;
2509

    
2510
    case 0x1b6: /* movzbS Gv, Eb */
2511
    case 0x1b7: /* movzwS Gv, Eb */
2512
    case 0x1be: /* movsbS Gv, Eb */
2513
    case 0x1bf: /* movswS Gv, Eb */
2514
        {
2515
            int d_ot;
2516
            /* d_ot is the size of destination */
2517
            d_ot = dflag + OT_WORD;
2518
            /* ot is the size of source */
2519
            ot = (b & 1) + OT_BYTE;
2520
            modrm = ldub_code(s->pc++);
2521
            reg = ((modrm >> 3) & 7) + OR_EAX;
2522
            mod = (modrm >> 6) & 3;
2523
            rm = modrm & 7;
2524
            
2525
            if (mod == 3) {
2526
                gen_op_mov_TN_reg[ot][0][rm]();
2527
                switch(ot | (b & 8)) {
2528
                case OT_BYTE:
2529
                    gen_op_movzbl_T0_T0();
2530
                    break;
2531
                case OT_BYTE | 8:
2532
                    gen_op_movsbl_T0_T0();
2533
                    break;
2534
                case OT_WORD:
2535
                    gen_op_movzwl_T0_T0();
2536
                    break;
2537
                default:
2538
                case OT_WORD | 8:
2539
                    gen_op_movswl_T0_T0();
2540
                    break;
2541
                }
2542
                gen_op_mov_reg_T0[d_ot][reg]();
2543
            } else {
2544
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2545
                if (b & 8) {
2546
                    gen_op_lds_T0_A0[ot + s->mem_index]();
2547
                } else {
2548
                    gen_op_ldu_T0_A0[ot + s->mem_index]();
2549
                }
2550
                gen_op_mov_reg_T0[d_ot][reg]();
2551
            }
2552
        }
2553
        break;
2554

    
2555
    case 0x8d: /* lea */
2556
        ot = dflag ? OT_LONG : OT_WORD;
2557
        modrm = ldub_code(s->pc++);
2558
        mod = (modrm >> 6) & 3;
2559
        if (mod == 3)
2560
            goto illegal_op;
2561
        reg = (modrm >> 3) & 7;
2562
        /* we must ensure that no segment is added */
2563
        s->override = -1;
2564
        val = s->addseg;
2565
        s->addseg = 0;
2566
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2567
        s->addseg = val;
2568
        gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2569
        break;
2570
        
2571
    case 0xa0: /* mov EAX, Ov */
2572
    case 0xa1:
2573
    case 0xa2: /* mov Ov, EAX */
2574
    case 0xa3:
2575
        if ((b & 1) == 0)
2576
            ot = OT_BYTE;
2577
        else
2578
            ot = dflag ? OT_LONG : OT_WORD;
2579
        if (s->aflag)
2580
            offset_addr = insn_get(s, OT_LONG);
2581
        else
2582
            offset_addr = insn_get(s, OT_WORD);
2583
        gen_op_movl_A0_im(offset_addr);
2584
        /* handle override */
2585
        {
2586
            int override, must_add_seg;
2587
            must_add_seg = s->addseg;
2588
            if (s->override >= 0) {
2589
                override = s->override;
2590
                must_add_seg = 1;
2591
            } else {
2592
                override = R_DS;
2593
            }
2594
            if (must_add_seg) {
2595
                gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2596
            }
2597
        }
2598
        if ((b & 2) == 0) {
2599
            gen_op_ld_T0_A0[ot + s->mem_index]();
2600
            gen_op_mov_reg_T0[ot][R_EAX]();
2601
        } else {
2602
            gen_op_mov_TN_reg[ot][0][R_EAX]();
2603
            gen_op_st_T0_A0[ot + s->mem_index]();
2604
        }
2605
        break;
2606
    case 0xd7: /* xlat */
2607
        gen_op_movl_A0_reg[R_EBX]();
2608
        gen_op_addl_A0_AL();
2609
        if (s->aflag == 0)
2610
            gen_op_andl_A0_ffff();
2611
        /* handle override */
2612
        {
2613
            int override, must_add_seg;
2614
            must_add_seg = s->addseg;
2615
            override = R_DS;
2616
            if (s->override >= 0) {
2617
                override = s->override;
2618
                must_add_seg = 1;
2619
            } else {
2620
                override = R_DS;
2621
            }
2622
            if (must_add_seg) {
2623
                gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2624
            }
2625
        }
2626
        gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
2627
        gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2628
        break;
2629
    case 0xb0 ... 0xb7: /* mov R, Ib */
2630
        val = insn_get(s, OT_BYTE);
2631
        gen_op_movl_T0_im(val);
2632
        gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2633
        break;
2634
    case 0xb8 ... 0xbf: /* mov R, Iv */
2635
        ot = dflag ? OT_LONG : OT_WORD;
2636
        val = insn_get(s, ot);
2637
        reg = OR_EAX + (b & 7);
2638
        gen_op_movl_T0_im(val);
2639
        gen_op_mov_reg_T0[ot][reg]();
2640
        break;
2641

    
2642
    case 0x91 ... 0x97: /* xchg R, EAX */
2643
        ot = dflag ? OT_LONG : OT_WORD;
2644
        reg = b & 7;
2645
        rm = R_EAX;
2646
        goto do_xchg_reg;
2647
    case 0x86:
2648
    case 0x87: /* xchg Ev, Gv */
2649
        if ((b & 1) == 0)
2650
            ot = OT_BYTE;
2651
        else
2652
            ot = dflag ? OT_LONG : OT_WORD;
2653
        modrm = ldub_code(s->pc++);
2654
        reg = (modrm >> 3) & 7;
2655
        mod = (modrm >> 6) & 3;
2656
        if (mod == 3) {
2657
            rm = modrm & 7;
2658
        do_xchg_reg:
2659
            gen_op_mov_TN_reg[ot][0][reg]();
2660
            gen_op_mov_TN_reg[ot][1][rm]();
2661
            gen_op_mov_reg_T0[ot][rm]();
2662
            gen_op_mov_reg_T1[ot][reg]();
2663
        } else {
2664
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2665
            gen_op_mov_TN_reg[ot][0][reg]();
2666
            /* for xchg, lock is implicit */
2667
            if (!(prefixes & PREFIX_LOCK))
2668
                gen_op_lock();
2669
            gen_op_ld_T1_A0[ot + s->mem_index]();
2670
            gen_op_st_T0_A0[ot + s->mem_index]();
2671
            if (!(prefixes & PREFIX_LOCK))
2672
                gen_op_unlock();
2673
            gen_op_mov_reg_T1[ot][reg]();
2674
        }
2675
        break;
2676
    case 0xc4: /* les Gv */
2677
        op = R_ES;
2678
        goto do_lxx;
2679
    case 0xc5: /* lds Gv */
2680
        op = R_DS;
2681
        goto do_lxx;
2682
    case 0x1b2: /* lss Gv */
2683
        op = R_SS;
2684
        goto do_lxx;
2685
    case 0x1b4: /* lfs Gv */
2686
        op = R_FS;
2687
        goto do_lxx;
2688
    case 0x1b5: /* lgs Gv */
2689
        op = R_GS;
2690
    do_lxx:
2691
        ot = dflag ? OT_LONG : OT_WORD;
2692
        modrm = ldub_code(s->pc++);
2693
        reg = (modrm >> 3) & 7;
2694
        mod = (modrm >> 6) & 3;
2695
        if (mod == 3)
2696
            goto illegal_op;
2697
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2698
        gen_op_ld_T1_A0[ot + s->mem_index]();
2699
        gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2700
        /* load the segment first to handle exceptions properly */
2701
        gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2702
        gen_movl_seg_T0(s, op, pc_start - s->cs_base);
2703
        /* then put the data */
2704
        gen_op_mov_reg_T1[ot][reg]();
2705
        if (s->is_jmp) {
2706
            gen_op_jmp_im(s->pc - s->cs_base);
2707
            gen_eob(s);
2708
        }
2709
        break;
2710
        
2711
        /************************/
2712
        /* shifts */
2713
    case 0xc0:
2714
    case 0xc1:
2715
        /* shift Ev,Ib */
2716
        shift = 2;
2717
    grp2:
2718
        {
2719
            if ((b & 1) == 0)
2720
                ot = OT_BYTE;
2721
            else
2722
                ot = dflag ? OT_LONG : OT_WORD;
2723
            
2724
            modrm = ldub_code(s->pc++);
2725
            mod = (modrm >> 6) & 3;
2726
            rm = modrm & 7;
2727
            op = (modrm >> 3) & 7;
2728
            
2729
            if (mod != 3) {
2730
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2731
                opreg = OR_TMP0;
2732
            } else {
2733
                opreg = rm + OR_EAX;
2734
            }
2735

    
2736
            /* simpler op */
2737
            if (shift == 0) {
2738
                gen_shift(s, op, ot, opreg, OR_ECX);
2739
            } else {
2740
                if (shift == 2) {
2741
                    shift = ldub_code(s->pc++);
2742
                }
2743
                gen_shifti(s, op, ot, opreg, shift);
2744
            }
2745
        }
2746
        break;
2747
    case 0xd0:
2748
    case 0xd1:
2749
        /* shift Ev,1 */
2750
        shift = 1;
2751
        goto grp2;
2752
    case 0xd2:
2753
    case 0xd3:
2754
        /* shift Ev,cl */
2755
        shift = 0;
2756
        goto grp2;
2757

    
2758
    case 0x1a4: /* shld imm */
2759
        op = 0;
2760
        shift = 1;
2761
        goto do_shiftd;
2762
    case 0x1a5: /* shld cl */
2763
        op = 0;
2764
        shift = 0;
2765
        goto do_shiftd;
2766
    case 0x1ac: /* shrd imm */
2767
        op = 1;
2768
        shift = 1;
2769
        goto do_shiftd;
2770
    case 0x1ad: /* shrd cl */
2771
        op = 1;
2772
        shift = 0;
2773
    do_shiftd:
2774
        ot = dflag ? OT_LONG : OT_WORD;
2775
        modrm = ldub_code(s->pc++);
2776
        mod = (modrm >> 6) & 3;
2777
        rm = modrm & 7;
2778
        reg = (modrm >> 3) & 7;
2779
        
2780
        if (mod != 3) {
2781
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2782
            gen_op_ld_T0_A0[ot + s->mem_index]();
2783
        } else {
2784
            gen_op_mov_TN_reg[ot][0][rm]();
2785
        }
2786
        gen_op_mov_TN_reg[ot][1][reg]();
2787
        
2788
        if (shift) {
2789
            val = ldub_code(s->pc++);
2790
            val &= 0x1f;
2791
            if (val) {
2792
                if (mod == 3)
2793
                    gen_op_shiftd_T0_T1_im_cc[ot][op](val);
2794
                else
2795
                    gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val);
2796
                if (op == 0 && ot != OT_WORD)
2797
                    s->cc_op = CC_OP_SHLB + ot;
2798
                else
2799
                    s->cc_op = CC_OP_SARB + ot;
2800
            }
2801
        } else {
2802
            if (s->cc_op != CC_OP_DYNAMIC)
2803
                gen_op_set_cc_op(s->cc_op);
2804
            if (mod == 3)
2805
                gen_op_shiftd_T0_T1_ECX_cc[ot][op]();
2806
            else
2807
                gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op]();
2808
            s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2809
        }
2810
        if (mod == 3) {
2811
            gen_op_mov_reg_T0[ot][rm]();
2812
        }
2813
        break;
2814

    
2815
        /************************/
2816
        /* floats */
2817
    case 0xd8 ... 0xdf: 
2818
        if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
2819
            /* if CR0.EM or CR0.TS are set, generate an FPU exception */
2820
            /* XXX: what to do if illegal op ? */
2821
            gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2822
            break;
2823
        }
2824
        modrm = ldub_code(s->pc++);
2825
        mod = (modrm >> 6) & 3;
2826
        rm = modrm & 7;
2827
        op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2828
        if (mod != 3) {
2829
            /* memory op */
2830
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2831
            switch(op) {
2832
            case 0x00 ... 0x07: /* fxxxs */
2833
            case 0x10 ... 0x17: /* fixxxl */
2834
            case 0x20 ... 0x27: /* fxxxl */
2835
            case 0x30 ... 0x37: /* fixxx */
2836
                {
2837
                    int op1;
2838
                    op1 = op & 7;
2839

    
2840
                    switch(op >> 4) {
2841
                    case 0:
2842
                        gen_op_flds_FT0_A0();
2843
                        break;
2844
                    case 1:
2845
                        gen_op_fildl_FT0_A0();
2846
                        break;
2847
                    case 2:
2848
                        gen_op_fldl_FT0_A0();
2849
                        break;
2850
                    case 3:
2851
                    default:
2852
                        gen_op_fild_FT0_A0();
2853
                        break;
2854
                    }
2855
                    
2856
                    gen_op_fp_arith_ST0_FT0[op1]();
2857
                    if (op1 == 3) {
2858
                        /* fcomp needs pop */
2859
                        gen_op_fpop();
2860
                    }
2861
                }
2862
                break;
2863
            case 0x08: /* flds */
2864
            case 0x0a: /* fsts */
2865
            case 0x0b: /* fstps */
2866
            case 0x18: /* fildl */
2867
            case 0x1a: /* fistl */
2868
            case 0x1b: /* fistpl */
2869
            case 0x28: /* fldl */
2870
            case 0x2a: /* fstl */
2871
            case 0x2b: /* fstpl */
2872
            case 0x38: /* filds */
2873
            case 0x3a: /* fists */
2874
            case 0x3b: /* fistps */
2875
                
2876
                switch(op & 7) {
2877
                case 0:
2878
                    switch(op >> 4) {
2879
                    case 0:
2880
                        gen_op_flds_ST0_A0();
2881
                        break;
2882
                    case 1:
2883
                        gen_op_fildl_ST0_A0();
2884
                        break;
2885
                    case 2:
2886
                        gen_op_fldl_ST0_A0();
2887
                        break;
2888
                    case 3:
2889
                    default:
2890
                        gen_op_fild_ST0_A0();
2891
                        break;
2892
                    }
2893
                    break;
2894
                default:
2895
                    switch(op >> 4) {
2896
                    case 0:
2897
                        gen_op_fsts_ST0_A0();
2898
                        break;
2899
                    case 1:
2900
                        gen_op_fistl_ST0_A0();
2901
                        break;
2902
                    case 2:
2903
                        gen_op_fstl_ST0_A0();
2904
                        break;
2905
                    case 3:
2906
                    default:
2907
                        gen_op_fist_ST0_A0();
2908
                        break;
2909
                    }
2910
                    if ((op & 7) == 3)
2911
                        gen_op_fpop();
2912
                    break;
2913
                }
2914
                break;
2915
            case 0x0c: /* fldenv mem */
2916
                gen_op_fldenv_A0(s->dflag);
2917
                break;
2918
            case 0x0d: /* fldcw mem */
2919
                gen_op_fldcw_A0();
2920
                break;
2921
            case 0x0e: /* fnstenv mem */
2922
                gen_op_fnstenv_A0(s->dflag);
2923
                break;
2924
            case 0x0f: /* fnstcw mem */
2925
                gen_op_fnstcw_A0();
2926
                break;
2927
            case 0x1d: /* fldt mem */
2928
                gen_op_fldt_ST0_A0();
2929
                break;
2930
            case 0x1f: /* fstpt mem */
2931
                gen_op_fstt_ST0_A0();
2932
                gen_op_fpop();
2933
                break;
2934
            case 0x2c: /* frstor mem */
2935
                gen_op_frstor_A0(s->dflag);
2936
                break;
2937
            case 0x2e: /* fnsave mem */
2938
                gen_op_fnsave_A0(s->dflag);
2939
                break;
2940
            case 0x2f: /* fnstsw mem */
2941
                gen_op_fnstsw_A0();
2942
                break;
2943
            case 0x3c: /* fbld */
2944
                gen_op_fbld_ST0_A0();
2945
                break;
2946
            case 0x3e: /* fbstp */
2947
                gen_op_fbst_ST0_A0();
2948
                gen_op_fpop();
2949
                break;
2950
            case 0x3d: /* fildll */
2951
                gen_op_fildll_ST0_A0();
2952
                break;
2953
            case 0x3f: /* fistpll */
2954
                gen_op_fistll_ST0_A0();
2955
                gen_op_fpop();
2956
                break;
2957
            default:
2958
                goto illegal_op;
2959
            }
2960
        } else {
2961
            /* register float ops */
2962
            opreg = rm;
2963

    
2964
            switch(op) {
2965
            case 0x08: /* fld sti */
2966
                gen_op_fpush();
2967
                gen_op_fmov_ST0_STN((opreg + 1) & 7);
2968
                break;
2969
            case 0x09: /* fxchg sti */
2970
                gen_op_fxchg_ST0_STN(opreg);
2971
                break;
2972
            case 0x0a: /* grp d9/2 */
2973
                switch(rm) {
2974
                case 0: /* fnop */
2975
                    break;
2976
                default:
2977
                    goto illegal_op;
2978
                }
2979
                break;
2980
            case 0x0c: /* grp d9/4 */
2981
                switch(rm) {
2982
                case 0: /* fchs */
2983
                    gen_op_fchs_ST0();
2984
                    break;
2985
                case 1: /* fabs */
2986
                    gen_op_fabs_ST0();
2987
                    break;
2988
                case 4: /* ftst */
2989
                    gen_op_fldz_FT0();
2990
                    gen_op_fcom_ST0_FT0();
2991
                    break;
2992
                case 5: /* fxam */
2993
                    gen_op_fxam_ST0();
2994
                    break;
2995
                default:
2996
                    goto illegal_op;
2997
                }
2998
                break;
2999
            case 0x0d: /* grp d9/5 */
3000
                {
3001
                    switch(rm) {
3002
                    case 0:
3003
                        gen_op_fpush();
3004
                        gen_op_fld1_ST0();
3005
                        break;
3006
                    case 1:
3007
                        gen_op_fpush();
3008
                        gen_op_fldl2t_ST0();
3009
                        break;
3010
                    case 2:
3011
                        gen_op_fpush();
3012
                        gen_op_fldl2e_ST0();
3013
                        break;
3014
                    case 3:
3015
                        gen_op_fpush();
3016
                        gen_op_fldpi_ST0();
3017
                        break;
3018
                    case 4:
3019
                        gen_op_fpush();
3020
                        gen_op_fldlg2_ST0();
3021
                        break;
3022
                    case 5:
3023
                        gen_op_fpush();
3024
                        gen_op_fldln2_ST0();
3025
                        break;
3026
                    case 6:
3027
                        gen_op_fpush();
3028
                        gen_op_fldz_ST0();
3029
                        break;
3030
                    default:
3031
                        goto illegal_op;
3032
                    }
3033
                }
3034
                break;
3035
            case 0x0e: /* grp d9/6 */
3036
                switch(rm) {
3037
                case 0: /* f2xm1 */
3038
                    gen_op_f2xm1();
3039
                    break;
3040
                case 1: /* fyl2x */
3041
                    gen_op_fyl2x();
3042
                    break;
3043
                case 2: /* fptan */
3044
                    gen_op_fptan();
3045
                    break;
3046
                case 3: /* fpatan */
3047
                    gen_op_fpatan();
3048
                    break;
3049
                case 4: /* fxtract */
3050
                    gen_op_fxtract();
3051
                    break;
3052
                case 5: /* fprem1 */
3053
                    gen_op_fprem1();
3054
                    break;
3055
                case 6: /* fdecstp */
3056
                    gen_op_fdecstp();
3057
                    break;
3058
                default:
3059
                case 7: /* fincstp */
3060
                    gen_op_fincstp();
3061
                    break;
3062
                }
3063
                break;
3064
            case 0x0f: /* grp d9/7 */
3065
                switch(rm) {
3066
                case 0: /* fprem */
3067
                    gen_op_fprem();
3068
                    break;
3069
                case 1: /* fyl2xp1 */
3070
                    gen_op_fyl2xp1();
3071
                    break;
3072
                case 2: /* fsqrt */
3073
                    gen_op_fsqrt();
3074
                    break;
3075
                case 3: /* fsincos */
3076
                    gen_op_fsincos();
3077
                    break;
3078
                case 5: /* fscale */
3079
                    gen_op_fscale();
3080
                    break;
3081
                case 4: /* frndint */
3082
                    gen_op_frndint();
3083
                    break;
3084
                case 6: /* fsin */
3085
                    gen_op_fsin();
3086
                    break;
3087
                default:
3088
                case 7: /* fcos */
3089
                    gen_op_fcos();
3090
                    break;
3091
                }
3092
                break;
3093
            case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3094
            case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3095
            case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3096
                {
3097
                    int op1;
3098
                    
3099
                    op1 = op & 7;
3100
                    if (op >= 0x20) {
3101
                        gen_op_fp_arith_STN_ST0[op1](opreg);
3102
                        if (op >= 0x30)
3103
                            gen_op_fpop();
3104
                    } else {
3105
                        gen_op_fmov_FT0_STN(opreg);
3106
                        gen_op_fp_arith_ST0_FT0[op1]();
3107
                    }
3108
                }
3109
                break;
3110
            case 0x02: /* fcom */
3111
                gen_op_fmov_FT0_STN(opreg);
3112
                gen_op_fcom_ST0_FT0();
3113
                break;
3114
            case 0x03: /* fcomp */
3115
                gen_op_fmov_FT0_STN(opreg);
3116
                gen_op_fcom_ST0_FT0();
3117
                gen_op_fpop();
3118
                break;
3119
            case 0x15: /* da/5 */
3120
                switch(rm) {
3121
                case 1: /* fucompp */
3122
                    gen_op_fmov_FT0_STN(1);
3123
                    gen_op_fucom_ST0_FT0();
3124
                    gen_op_fpop();
3125
                    gen_op_fpop();
3126
                    break;
3127
                default:
3128
                    goto illegal_op;
3129
                }
3130
                break;
3131
            case 0x1c:
3132
                switch(rm) {
3133
                case 0: /* feni (287 only, just do nop here) */
3134
                    break;
3135
                case 1: /* fdisi (287 only, just do nop here) */
3136
                    break;
3137
                case 2: /* fclex */
3138
                    gen_op_fclex();
3139
                    break;
3140
                case 3: /* fninit */
3141
                    gen_op_fninit();
3142
                    break;
3143
                case 4: /* fsetpm (287 only, just do nop here) */
3144
                    break;
3145
                default:
3146
                    goto illegal_op;
3147
                }
3148
                break;
3149
            case 0x1d: /* fucomi */
3150
                if (s->cc_op != CC_OP_DYNAMIC)
3151
                    gen_op_set_cc_op(s->cc_op);
3152
                gen_op_fmov_FT0_STN(opreg);
3153
                gen_op_fucomi_ST0_FT0();
3154
                s->cc_op = CC_OP_EFLAGS;
3155
                break;
3156
            case 0x1e: /* fcomi */
3157
                if (s->cc_op != CC_OP_DYNAMIC)
3158
                    gen_op_set_cc_op(s->cc_op);
3159
                gen_op_fmov_FT0_STN(opreg);
3160
                gen_op_fcomi_ST0_FT0();
3161
                s->cc_op = CC_OP_EFLAGS;
3162
                break;
3163
            case 0x2a: /* fst sti */
3164
                gen_op_fmov_STN_ST0(opreg);
3165
                break;
3166
            case 0x2b: /* fstp sti */
3167
                gen_op_fmov_STN_ST0(opreg);
3168
                gen_op_fpop();
3169
                break;
3170
            case 0x2c: /* fucom st(i) */
3171
                gen_op_fmov_FT0_STN(opreg);
3172
                gen_op_fucom_ST0_FT0();
3173
                break;
3174
            case 0x2d: /* fucomp st(i) */
3175
                gen_op_fmov_FT0_STN(opreg);
3176
                gen_op_fucom_ST0_FT0();
3177
                gen_op_fpop();
3178
                break;
3179
            case 0x33: /* de/3 */
3180
                switch(rm) {
3181
                case 1: /* fcompp */
3182
                    gen_op_fmov_FT0_STN(1);
3183
                    gen_op_fcom_ST0_FT0();
3184
                    gen_op_fpop();
3185
                    gen_op_fpop();
3186
                    break;
3187
                default:
3188
                    goto illegal_op;
3189
                }
3190
                break;
3191
            case 0x3c: /* df/4 */
3192
                switch(rm) {
3193
                case 0:
3194
                    gen_op_fnstsw_EAX();
3195
                    break;
3196
                default:
3197
                    goto illegal_op;
3198
                }
3199
                break;
3200
            case 0x3d: /* fucomip */
3201
                if (s->cc_op != CC_OP_DYNAMIC)
3202
                    gen_op_set_cc_op(s->cc_op);
3203
                gen_op_fmov_FT0_STN(opreg);
3204
                gen_op_fucomi_ST0_FT0();
3205
                gen_op_fpop();
3206
                s->cc_op = CC_OP_EFLAGS;
3207
                break;
3208
            case 0x3e: /* fcomip */
3209
                if (s->cc_op != CC_OP_DYNAMIC)
3210
                    gen_op_set_cc_op(s->cc_op);
3211
                gen_op_fmov_FT0_STN(opreg);
3212
                gen_op_fcomi_ST0_FT0();
3213
                gen_op_fpop();
3214
                s->cc_op = CC_OP_EFLAGS;
3215
                break;
3216
            case 0x10 ... 0x13: /* fcmovxx */
3217
            case 0x18 ... 0x1b:
3218
                {
3219
                    int op1;
3220
                    const static uint8_t fcmov_cc[8] = {
3221
                        (JCC_B << 1),
3222
                        (JCC_Z << 1),
3223
                        (JCC_BE << 1),
3224
                        (JCC_P << 1),
3225
                    };
3226
                    op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
3227
                    gen_setcc(s, op1);
3228
                    gen_op_fcmov_ST0_STN_T0(opreg);
3229
                }
3230
                break;
3231
            default:
3232
                goto illegal_op;
3233
            }
3234
        }
3235
#ifdef USE_CODE_COPY
3236
        s->tb->cflags |= CF_TB_FP_USED;
3237
#endif
3238
        break;
3239
        /************************/
3240
        /* string ops */
3241

    
3242
    case 0xa4: /* movsS */
3243
    case 0xa5:
3244
        if ((b & 1) == 0)
3245
            ot = OT_BYTE;
3246
        else
3247
            ot = dflag ? OT_LONG : OT_WORD;
3248

    
3249
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3250
            gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3251
        } else {
3252
            gen_movs(s, ot);
3253
        }
3254
        break;
3255
        
3256
    case 0xaa: /* stosS */
3257
    case 0xab:
3258
        if ((b & 1) == 0)
3259
            ot = OT_BYTE;
3260
        else
3261
            ot = dflag ? OT_LONG : OT_WORD;
3262

    
3263
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3264
            gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3265
        } else {
3266
            gen_stos(s, ot);
3267
        }
3268
        break;
3269
    case 0xac: /* lodsS */
3270
    case 0xad:
3271
        if ((b & 1) == 0)
3272
            ot = OT_BYTE;
3273
        else
3274
            ot = dflag ? OT_LONG : OT_WORD;
3275
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3276
            gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3277
        } else {
3278
            gen_lods(s, ot);
3279
        }
3280
        break;
3281
    case 0xae: /* scasS */
3282
    case 0xaf:
3283
        if ((b & 1) == 0)
3284
            ot = OT_BYTE;
3285
        else
3286
                ot = dflag ? OT_LONG : OT_WORD;
3287
        if (prefixes & PREFIX_REPNZ) {
3288
            gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3289
        } else if (prefixes & PREFIX_REPZ) {
3290
            gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3291
        } else {
3292
            gen_scas(s, ot);
3293
            s->cc_op = CC_OP_SUBB + ot;
3294
        }
3295
        break;
3296

    
3297
    case 0xa6: /* cmpsS */
3298
    case 0xa7:
3299
        if ((b & 1) == 0)
3300
            ot = OT_BYTE;
3301
        else
3302
            ot = dflag ? OT_LONG : OT_WORD;
3303
        if (prefixes & PREFIX_REPNZ) {
3304
            gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3305
        } else if (prefixes & PREFIX_REPZ) {
3306
            gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3307
        } else {
3308
            gen_cmps(s, ot);
3309
            s->cc_op = CC_OP_SUBB + ot;
3310
        }
3311
        break;
3312
    case 0x6c: /* insS */
3313
    case 0x6d:
3314
        if ((b & 1) == 0)
3315
            ot = OT_BYTE;
3316
        else
3317
            ot = dflag ? OT_LONG : OT_WORD;
3318
        gen_check_io(s, ot, 1, pc_start - s->cs_base);
3319
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3320
            gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3321
        } else {
3322
            gen_ins(s, ot);
3323
        }
3324
        break;
3325
    case 0x6e: /* outsS */
3326
    case 0x6f:
3327
        if ((b & 1) == 0)
3328
            ot = OT_BYTE;
3329
        else
3330
            ot = dflag ? OT_LONG : OT_WORD;
3331
        gen_check_io(s, ot, 1, pc_start - s->cs_base);
3332
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3333
            gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3334
        } else {
3335
            gen_outs(s, ot);
3336
        }
3337
        break;
3338

    
3339
        /************************/
3340
        /* port I/O */
3341
    case 0xe4:
3342
    case 0xe5:
3343
        if ((b & 1) == 0)
3344
            ot = OT_BYTE;
3345
        else
3346
            ot = dflag ? OT_LONG : OT_WORD;
3347
        val = ldub_code(s->pc++);
3348
        gen_op_movl_T0_im(val);
3349
        gen_check_io(s, ot, 0, pc_start - s->cs_base);
3350
        gen_op_in[ot]();
3351
        gen_op_mov_reg_T1[ot][R_EAX]();
3352
        break;
3353
    case 0xe6:
3354
    case 0xe7:
3355
        if ((b & 1) == 0)
3356
            ot = OT_BYTE;
3357
        else
3358
            ot = dflag ? OT_LONG : OT_WORD;
3359
        val = ldub_code(s->pc++);
3360
        gen_op_movl_T0_im(val);
3361
        gen_check_io(s, ot, 0, pc_start - s->cs_base);
3362
        gen_op_mov_TN_reg[ot][1][R_EAX]();
3363
        gen_op_out[ot]();
3364
        break;
3365
    case 0xec:
3366
    case 0xed:
3367
        if ((b & 1) == 0)
3368
            ot = OT_BYTE;
3369
        else
3370
            ot = dflag ? OT_LONG : OT_WORD;
3371
        gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3372
        gen_op_andl_T0_ffff();
3373
        gen_check_io(s, ot, 0, pc_start - s->cs_base);
3374
        gen_op_in[ot]();
3375
        gen_op_mov_reg_T1[ot][R_EAX]();
3376
        break;
3377
    case 0xee:
3378
    case 0xef:
3379
        if ((b & 1) == 0)
3380
            ot = OT_BYTE;
3381
        else
3382
            ot = dflag ? OT_LONG : OT_WORD;
3383
        gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3384
        gen_op_andl_T0_ffff();
3385
        gen_check_io(s, ot, 0, pc_start - s->cs_base);
3386
        gen_op_mov_TN_reg[ot][1][R_EAX]();
3387
        gen_op_out[ot]();
3388
        break;
3389

    
3390
        /************************/
3391
        /* control */
3392
    case 0xc2: /* ret im */
3393
        val = ldsw_code(s->pc);
3394
        s->pc += 2;
3395
        gen_pop_T0(s);
3396
        gen_stack_update(s, val + (2 << s->dflag));
3397
        if (s->dflag == 0)
3398
            gen_op_andl_T0_ffff();
3399
        gen_op_jmp_T0();
3400
        gen_eob(s);
3401
        break;
3402
    case 0xc3: /* ret */
3403
        gen_pop_T0(s);
3404
        gen_pop_update(s);
3405
        if (s->dflag == 0)
3406
            gen_op_andl_T0_ffff();
3407
        gen_op_jmp_T0();
3408
        gen_eob(s);
3409
        break;
3410
    case 0xca: /* lret im */
3411
        val = ldsw_code(s->pc);
3412
        s->pc += 2;
3413
    do_lret:
3414
        if (s->pe && !s->vm86) {
3415
            if (s->cc_op != CC_OP_DYNAMIC)
3416
                gen_op_set_cc_op(s->cc_op);
3417
            gen_op_jmp_im(pc_start - s->cs_base);
3418
            gen_op_lret_protected(s->dflag, val);
3419
        } else {
3420
            gen_stack_A0(s);
3421
            /* pop offset */
3422
            gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3423
            if (s->dflag == 0)
3424
                gen_op_andl_T0_ffff();
3425
            /* NOTE: keeping EIP updated is not a problem in case of
3426
               exception */
3427
            gen_op_jmp_T0();
3428
            /* pop selector */
3429
            gen_op_addl_A0_im(2 << s->dflag);
3430
            gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3431
            gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3432
            /* add stack offset */
3433
            gen_stack_update(s, val + (4 << s->dflag));
3434
        }
3435
        gen_eob(s);
3436
        break;
3437
    case 0xcb: /* lret */
3438
        val = 0;
3439
        goto do_lret;
3440
    case 0xcf: /* iret */
3441
        if (!s->pe) {
3442
            /* real mode */
3443
            gen_op_iret_real(s->dflag);
3444
            s->cc_op = CC_OP_EFLAGS;
3445
        } else if (s->vm86) {
3446
            if (s->iopl != 3) {
3447
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3448
            } else {
3449
                gen_op_iret_real(s->dflag);
3450
                s->cc_op = CC_OP_EFLAGS;
3451
            }
3452
        } else {
3453
            if (s->cc_op != CC_OP_DYNAMIC)
3454
                gen_op_set_cc_op(s->cc_op);
3455
            gen_op_jmp_im(pc_start - s->cs_base);
3456
            gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
3457
            s->cc_op = CC_OP_EFLAGS;
3458
        }
3459
        gen_eob(s);
3460
        break;
3461
    case 0xe8: /* call im */
3462
        {
3463
            unsigned int next_eip;
3464
            ot = dflag ? OT_LONG : OT_WORD;
3465
            val = insn_get(s, ot);
3466
            next_eip = s->pc - s->cs_base;
3467
            val += next_eip;
3468
            if (s->dflag == 0)
3469
                val &= 0xffff;
3470
            gen_op_movl_T0_im(next_eip);
3471
            gen_push_T0(s);
3472
            gen_jmp(s, val);
3473
        }
3474
        break;
3475
    case 0x9a: /* lcall im */
3476
        {
3477
            unsigned int selector, offset;
3478

    
3479
            ot = dflag ? OT_LONG : OT_WORD;
3480
            offset = insn_get(s, ot);
3481
            selector = insn_get(s, OT_WORD);
3482
            
3483
            gen_op_movl_T0_im(selector);
3484
            gen_op_movl_T1_im(offset);
3485
        }
3486
        goto do_lcall;
3487
    case 0xe9: /* jmp */
3488
        ot = dflag ? OT_LONG : OT_WORD;
3489
        val = insn_get(s, ot);
3490
        val += s->pc - s->cs_base;
3491
        if (s->dflag == 0)
3492
            val = val & 0xffff;
3493
        gen_jmp(s, val);
3494
        break;
3495
    case 0xea: /* ljmp im */
3496
        {
3497
            unsigned int selector, offset;
3498

    
3499
            ot = dflag ? OT_LONG : OT_WORD;
3500
            offset = insn_get(s, ot);
3501
            selector = insn_get(s, OT_WORD);
3502
            
3503
            gen_op_movl_T0_im(selector);
3504
            gen_op_movl_T1_im(offset);
3505
        }
3506
        goto do_ljmp;
3507
    case 0xeb: /* jmp Jb */
3508
        val = (int8_t)insn_get(s, OT_BYTE);
3509
        val += s->pc - s->cs_base;
3510
        if (s->dflag == 0)
3511
            val = val & 0xffff;
3512
        gen_jmp(s, val);
3513
        break;
3514
    case 0x70 ... 0x7f: /* jcc Jb */
3515
        val = (int8_t)insn_get(s, OT_BYTE);
3516
        goto do_jcc;
3517
    case 0x180 ... 0x18f: /* jcc Jv */
3518
        if (dflag) {
3519
            val = insn_get(s, OT_LONG);
3520
        } else {
3521
            val = (int16_t)insn_get(s, OT_WORD); 
3522
        }
3523
    do_jcc:
3524
        next_eip = s->pc - s->cs_base;
3525
        val += next_eip;
3526
        if (s->dflag == 0)
3527
            val &= 0xffff;
3528
        gen_jcc(s, b, val, next_eip);
3529
        break;
3530

    
3531
    case 0x190 ... 0x19f: /* setcc Gv */
3532
        modrm = ldub_code(s->pc++);
3533
        gen_setcc(s, b);
3534
        gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3535
        break;
3536
    case 0x140 ... 0x14f: /* cmov Gv, Ev */
3537
        ot = dflag ? OT_LONG : OT_WORD;
3538
        modrm = ldub_code(s->pc++);
3539
        reg = (modrm >> 3) & 7;
3540
        mod = (modrm >> 6) & 3;
3541
        gen_setcc(s, b);
3542
        if (mod != 3) {
3543
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3544
            gen_op_ld_T1_A0[ot + s->mem_index]();
3545
        } else {
3546
            rm = modrm & 7;
3547
            gen_op_mov_TN_reg[ot][1][rm]();
3548
        }
3549
        gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3550
        break;
3551
        
3552
        /************************/
3553
        /* flags */
3554
    case 0x9c: /* pushf */
3555
        if (s->vm86 && s->iopl != 3) {
3556
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3557
        } else {
3558
            if (s->cc_op != CC_OP_DYNAMIC)
3559
                gen_op_set_cc_op(s->cc_op);
3560
            gen_op_movl_T0_eflags();
3561
            gen_push_T0(s);
3562
        }
3563
        break;
3564
    case 0x9d: /* popf */
3565
        if (s->vm86 && s->iopl != 3) {
3566
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3567
        } else {
3568
            gen_pop_T0(s);
3569
            if (s->cpl == 0) {
3570
                if (s->dflag) {
3571
                    gen_op_movl_eflags_T0_cpl0();
3572
                } else {
3573
                    gen_op_movw_eflags_T0_cpl0();
3574
                }
3575
            } else {
3576
                if (s->cpl <= s->iopl) {
3577
                    if (s->dflag) {
3578
                        gen_op_movl_eflags_T0_io();
3579
                    } else {
3580
                        gen_op_movw_eflags_T0_io();
3581
                    }
3582
                } else {
3583
                    if (s->dflag) {
3584
                        gen_op_movl_eflags_T0();
3585
                    } else {
3586
                        gen_op_movw_eflags_T0();
3587
                    }
3588
                }
3589
            }
3590
            gen_pop_update(s);
3591
            s->cc_op = CC_OP_EFLAGS;
3592
            /* abort translation because TF flag may change */
3593
            gen_op_jmp_im(s->pc - s->cs_base);
3594
            gen_eob(s);
3595
        }
3596
        break;
3597
    case 0x9e: /* sahf */
3598
        gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3599
        if (s->cc_op != CC_OP_DYNAMIC)
3600
            gen_op_set_cc_op(s->cc_op);
3601
        gen_op_movb_eflags_T0();
3602
        s->cc_op = CC_OP_EFLAGS;
3603
        break;
3604
    case 0x9f: /* lahf */
3605
        if (s->cc_op != CC_OP_DYNAMIC)
3606
            gen_op_set_cc_op(s->cc_op);
3607
        gen_op_movl_T0_eflags();
3608
        gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3609
        break;
3610
    case 0xf5: /* cmc */
3611
        if (s->cc_op != CC_OP_DYNAMIC)
3612
            gen_op_set_cc_op(s->cc_op);
3613
        gen_op_cmc();
3614
        s->cc_op = CC_OP_EFLAGS;
3615
        break;
3616
    case 0xf8: /* clc */
3617
        if (s->cc_op != CC_OP_DYNAMIC)
3618
            gen_op_set_cc_op(s->cc_op);
3619
        gen_op_clc();
3620
        s->cc_op = CC_OP_EFLAGS;
3621
        break;
3622
    case 0xf9: /* stc */
3623
        if (s->cc_op != CC_OP_DYNAMIC)
3624
            gen_op_set_cc_op(s->cc_op);
3625
        gen_op_stc();
3626
        s->cc_op = CC_OP_EFLAGS;
3627
        break;
3628
    case 0xfc: /* cld */
3629
        gen_op_cld();
3630
        break;
3631
    case 0xfd: /* std */
3632
        gen_op_std();
3633
        break;
3634

    
3635
        /************************/
3636
        /* bit operations */
3637
    case 0x1ba: /* bt/bts/btr/btc Gv, im */
3638
        ot = dflag ? OT_LONG : OT_WORD;
3639
        modrm = ldub_code(s->pc++);
3640
        op = (modrm >> 3) & 7;
3641
        mod = (modrm >> 6) & 3;
3642
        rm = modrm & 7;
3643
        if (mod != 3) {
3644
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3645
            gen_op_ld_T0_A0[ot + s->mem_index]();
3646
        } else {
3647
            gen_op_mov_TN_reg[ot][0][rm]();
3648
        }
3649
        /* load shift */
3650
        val = ldub_code(s->pc++);
3651
        gen_op_movl_T1_im(val);
3652
        if (op < 4)
3653
            goto illegal_op;
3654
        op -= 4;
3655
        gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3656
        s->cc_op = CC_OP_SARB + ot;
3657
        if (op != 0) {
3658
            if (mod != 3)
3659
                gen_op_st_T0_A0[ot + s->mem_index]();
3660
            else
3661
                gen_op_mov_reg_T0[ot][rm]();
3662
            gen_op_update_bt_cc();
3663
        }
3664
        break;
3665
    case 0x1a3: /* bt Gv, Ev */
3666
        op = 0;
3667
        goto do_btx;
3668
    case 0x1ab: /* bts */
3669
        op = 1;
3670
        goto do_btx;
3671
    case 0x1b3: /* btr */
3672
        op = 2;
3673
        goto do_btx;
3674
    case 0x1bb: /* btc */
3675
        op = 3;
3676
    do_btx:
3677
        ot = dflag ? OT_LONG : OT_WORD;
3678
        modrm = ldub_code(s->pc++);
3679
        reg = (modrm >> 3) & 7;
3680
        mod = (modrm >> 6) & 3;
3681
        rm = modrm & 7;
3682
        gen_op_mov_TN_reg[OT_LONG][1][reg]();
3683
        if (mod != 3) {
3684
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3685
            /* specific case: we need to add a displacement */
3686
            if (ot == OT_WORD)
3687
                gen_op_add_bitw_A0_T1();
3688
            else
3689
                gen_op_add_bitl_A0_T1();
3690
            gen_op_ld_T0_A0[ot + s->mem_index]();
3691
        } else {
3692
            gen_op_mov_TN_reg[ot][0][rm]();
3693
        }
3694
        gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3695
        s->cc_op = CC_OP_SARB + ot;
3696
        if (op != 0) {
3697
            if (mod != 3)
3698
                gen_op_st_T0_A0[ot + s->mem_index]();
3699
            else
3700
                gen_op_mov_reg_T0[ot][rm]();
3701
            gen_op_update_bt_cc();
3702
        }
3703
        break;
3704
    case 0x1bc: /* bsf */
3705
    case 0x1bd: /* bsr */
3706
        ot = dflag ? OT_LONG : OT_WORD;
3707
        modrm = ldub_code(s->pc++);
3708
        reg = (modrm >> 3) & 7;
3709
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3710
        gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3711
        /* NOTE: we always write back the result. Intel doc says it is
3712
           undefined if T0 == 0 */
3713
        gen_op_mov_reg_T0[ot][reg]();
3714
        s->cc_op = CC_OP_LOGICB + ot;
3715
        break;
3716
        /************************/
3717
        /* bcd */
3718
    case 0x27: /* daa */
3719
        if (s->cc_op != CC_OP_DYNAMIC)
3720
            gen_op_set_cc_op(s->cc_op);
3721
        gen_op_daa();
3722
        s->cc_op = CC_OP_EFLAGS;
3723
        break;
3724
    case 0x2f: /* das */
3725
        if (s->cc_op != CC_OP_DYNAMIC)
3726
            gen_op_set_cc_op(s->cc_op);
3727
        gen_op_das();
3728
        s->cc_op = CC_OP_EFLAGS;
3729
        break;
3730
    case 0x37: /* aaa */
3731
        if (s->cc_op != CC_OP_DYNAMIC)
3732
            gen_op_set_cc_op(s->cc_op);
3733
        gen_op_aaa();
3734
        s->cc_op = CC_OP_EFLAGS;
3735
        break;
3736
    case 0x3f: /* aas */
3737
        if (s->cc_op != CC_OP_DYNAMIC)
3738
            gen_op_set_cc_op(s->cc_op);
3739
        gen_op_aas();
3740
        s->cc_op = CC_OP_EFLAGS;
3741
        break;
3742
    case 0xd4: /* aam */
3743
        val = ldub_code(s->pc++);
3744
        gen_op_aam(val);
3745
        s->cc_op = CC_OP_LOGICB;
3746
        break;
3747
    case 0xd5: /* aad */
3748
        val = ldub_code(s->pc++);
3749
        gen_op_aad(val);
3750
        s->cc_op = CC_OP_LOGICB;
3751
        break;
3752
        /************************/
3753
        /* misc */
3754
    case 0x90: /* nop */
3755
        /* XXX: correct lock test for all insn */
3756
        if (prefixes & PREFIX_LOCK)
3757
            goto illegal_op;
3758
        break;
3759
    case 0x9b: /* fwait */
3760
        if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == 
3761
            (HF_MP_MASK | HF_TS_MASK)) {
3762
            gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3763
        }
3764
        break;
3765
    case 0xcc: /* int3 */
3766
        gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
3767
        break;
3768
    case 0xcd: /* int N */
3769
        val = ldub_code(s->pc++);
3770
        if (s->vm86 && s->iopl != 3) {
3771
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); 
3772
        } else {
3773
            gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3774
        }
3775
        break;
3776
    case 0xce: /* into */
3777
        if (s->cc_op != CC_OP_DYNAMIC)
3778
            gen_op_set_cc_op(s->cc_op);
3779
        gen_op_into(s->pc - s->cs_base);
3780
        break;
3781
    case 0xf1: /* icebp (undocumented, exits to external debugger) */
3782
        gen_debug(s, pc_start - s->cs_base);
3783
        break;
3784
    case 0xfa: /* cli */
3785
        if (!s->vm86) {
3786
            if (s->cpl <= s->iopl) {
3787
                gen_op_cli();
3788
            } else {
3789
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3790
            }
3791
        } else {
3792
            if (s->iopl == 3) {
3793
                gen_op_cli();
3794
            } else {
3795
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3796
            }
3797
        }
3798
        break;
3799
    case 0xfb: /* sti */
3800
        if (!s->vm86) {
3801
            if (s->cpl <= s->iopl) {
3802
            gen_sti:
3803
                gen_op_sti();
3804
                /* interruptions are enabled only the first insn after sti */
3805
                /* If several instructions disable interrupts, only the
3806
                   _first_ does it */
3807
                if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3808
                    gen_op_set_inhibit_irq();
3809
                /* give a chance to handle pending irqs */
3810
                gen_op_jmp_im(s->pc - s->cs_base);
3811
                gen_eob(s);
3812
            } else {
3813
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3814
            }
3815
        } else {
3816
            if (s->iopl == 3) {
3817
                goto gen_sti;
3818
            } else {
3819
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3820
            }
3821
        }
3822
        break;
3823
    case 0x62: /* bound */
3824
        ot = dflag ? OT_LONG : OT_WORD;
3825
        modrm = ldub_code(s->pc++);
3826
        reg = (modrm >> 3) & 7;
3827
        mod = (modrm >> 6) & 3;
3828
        if (mod == 3)
3829
            goto illegal_op;
3830
        gen_op_mov_reg_T0[ot][reg]();
3831
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3832
        if (ot == OT_WORD)
3833
            gen_op_boundw(pc_start - s->cs_base);
3834
        else
3835
            gen_op_boundl(pc_start - s->cs_base);
3836
        break;
3837
    case 0x1c8 ... 0x1cf: /* bswap reg */
3838
        reg = b & 7;
3839
        gen_op_mov_TN_reg[OT_LONG][0][reg]();
3840
        gen_op_bswapl_T0();
3841
        gen_op_mov_reg_T0[OT_LONG][reg]();
3842
        break;
3843
    case 0xd6: /* salc */
3844
        if (s->cc_op != CC_OP_DYNAMIC)
3845
            gen_op_set_cc_op(s->cc_op);
3846
        gen_op_salc();
3847
        break;
3848
    case 0xe0: /* loopnz */
3849
    case 0xe1: /* loopz */
3850
        if (s->cc_op != CC_OP_DYNAMIC)
3851
            gen_op_set_cc_op(s->cc_op);
3852
        /* FALL THRU */
3853
    case 0xe2: /* loop */
3854
    case 0xe3: /* jecxz */
3855
        val = (int8_t)insn_get(s, OT_BYTE);
3856
        next_eip = s->pc - s->cs_base;
3857
        val += next_eip;
3858
        if (s->dflag == 0)
3859
            val &= 0xffff;
3860
        gen_op_loop[s->aflag][b & 3](val, next_eip);
3861
        gen_eob(s);
3862
        break;
3863
    case 0x130: /* wrmsr */
3864
    case 0x132: /* rdmsr */
3865
        if (s->cpl != 0) {
3866
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3867
        } else {
3868
            if (b & 2)
3869
                gen_op_rdmsr();
3870
            else
3871
                gen_op_wrmsr();
3872
        }
3873
        break;
3874
    case 0x131: /* rdtsc */
3875
        gen_op_rdtsc();
3876
        break;
3877
    case 0x1a2: /* cpuid */
3878
        gen_op_cpuid();
3879
        break;
3880
    case 0xf4: /* hlt */
3881
        if (s->cpl != 0) {
3882
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3883
        } else {
3884
            if (s->cc_op != CC_OP_DYNAMIC)
3885
                gen_op_set_cc_op(s->cc_op);
3886
            gen_op_jmp_im(s->pc - s->cs_base);
3887
            gen_op_hlt();
3888
            s->is_jmp = 3;
3889
        }
3890
        break;
3891
    case 0x100:
3892
        modrm = ldub_code(s->pc++);
3893
        mod = (modrm >> 6) & 3;
3894
        op = (modrm >> 3) & 7;
3895
        switch(op) {
3896
        case 0: /* sldt */
3897
            if (!s->pe || s->vm86)
3898
                goto illegal_op;
3899
            gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
3900
            ot = OT_WORD;
3901
            if (mod == 3)
3902
                ot += s->dflag;
3903
            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3904
            break;
3905
        case 2: /* lldt */
3906
            if (!s->pe || s->vm86)
3907
                goto illegal_op;
3908
            if (s->cpl != 0) {
3909
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3910
            } else {
3911
                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3912
                gen_op_jmp_im(pc_start - s->cs_base);
3913
                gen_op_lldt_T0();
3914
            }
3915
            break;
3916
        case 1: /* str */
3917
            if (!s->pe || s->vm86)
3918
                goto illegal_op;
3919
            gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
3920
            ot = OT_WORD;
3921
            if (mod == 3)
3922
                ot += s->dflag;
3923
            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3924
            break;
3925
        case 3: /* ltr */
3926
            if (!s->pe || s->vm86)
3927
                goto illegal_op;
3928
            if (s->cpl != 0) {
3929
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3930
            } else {
3931
                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3932
                gen_op_jmp_im(pc_start - s->cs_base);
3933
                gen_op_ltr_T0();
3934
            }
3935
            break;
3936
        case 4: /* verr */
3937
        case 5: /* verw */
3938
            if (!s->pe || s->vm86)
3939
                goto illegal_op;
3940
            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3941
            if (s->cc_op != CC_OP_DYNAMIC)
3942
                gen_op_set_cc_op(s->cc_op);
3943
            if (op == 4)
3944
                gen_op_verr();
3945
            else
3946
                gen_op_verw();
3947
            s->cc_op = CC_OP_EFLAGS;
3948
            break;
3949
        default:
3950
            goto illegal_op;
3951
        }
3952
        break;
3953
    case 0x101:
3954
        modrm = ldub_code(s->pc++);
3955
        mod = (modrm >> 6) & 3;
3956
        op = (modrm >> 3) & 7;
3957
        switch(op) {
3958
        case 0: /* sgdt */
3959
        case 1: /* sidt */
3960
            if (mod == 3)
3961
                goto illegal_op;
3962
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3963
            if (op == 0)
3964
                gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
3965
            else
3966
                gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
3967
            gen_op_st_T0_A0[OT_WORD + s->mem_index]();
3968
            gen_op_addl_A0_im(2);
3969
            if (op == 0)
3970
                gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
3971
            else
3972
                gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
3973
            if (!s->dflag)
3974
                gen_op_andl_T0_im(0xffffff);
3975
            gen_op_st_T0_A0[OT_LONG + s->mem_index]();
3976
            break;
3977
        case 2: /* lgdt */
3978
        case 3: /* lidt */
3979
            if (mod == 3)
3980
                goto illegal_op;
3981
            if (s->cpl != 0) {
3982
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3983
            } else {
3984
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3985
                gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
3986
                gen_op_addl_A0_im(2);
3987
                gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
3988
                if (!s->dflag)
3989
                    gen_op_andl_T0_im(0xffffff);
3990
                if (op == 2) {
3991
                    gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
3992
                    gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
3993
                } else {
3994
                    gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
3995
                    gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
3996
                }
3997
            }
3998
            break;
3999
        case 4: /* smsw */
4000
            gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
4001
            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
4002
            break;
4003
        case 6: /* lmsw */
4004
            if (s->cpl != 0) {
4005
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4006
            } else {
4007
                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
4008
                gen_op_lmsw_T0();
4009
                gen_op_jmp_im(s->pc - s->cs_base);
4010
                gen_eob(s);
4011
            }
4012
            break;
4013
        case 7: /* invlpg */
4014
            if (s->cpl != 0) {
4015
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4016
            } else {
4017
                if (mod == 3)
4018
                    goto illegal_op;
4019
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4020
                gen_op_invlpg_A0();
4021
                gen_op_jmp_im(s->pc - s->cs_base);
4022
                gen_eob(s);
4023
            }
4024
            break;
4025
        default:
4026
            goto illegal_op;
4027
        }
4028
        break;
4029
    case 0x108: /* invd */
4030
    case 0x109: /* wbinvd */
4031
        if (s->cpl != 0) {
4032
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4033
        } else {
4034
            /* nothing to do */
4035
        }
4036
        break;
4037
    case 0x63: /* arpl */
4038
        if (!s->pe || s->vm86)
4039
            goto illegal_op;
4040
        ot = dflag ? OT_LONG : OT_WORD;
4041
        modrm = ldub_code(s->pc++);
4042
        reg = (modrm >> 3) & 7;
4043
        mod = (modrm >> 6) & 3;
4044
        rm = modrm & 7;
4045
        if (mod != 3) {
4046
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4047
            gen_op_ld_T0_A0[ot + s->mem_index]();
4048
        } else {
4049
            gen_op_mov_TN_reg[ot][0][rm]();
4050
        }
4051
        if (s->cc_op != CC_OP_DYNAMIC)
4052
            gen_op_set_cc_op(s->cc_op);
4053
        gen_op_arpl();
4054
        s->cc_op = CC_OP_EFLAGS;
4055
        if (mod != 3) {
4056
            gen_op_st_T0_A0[ot + s->mem_index]();
4057
        } else {
4058
            gen_op_mov_reg_T0[ot][rm]();
4059
        }
4060
        gen_op_arpl_update();
4061
        break;
4062
    case 0x102: /* lar */
4063
    case 0x103: /* lsl */
4064
        if (!s->pe || s->vm86)
4065
            goto illegal_op;
4066
        ot = dflag ? OT_LONG : OT_WORD;
4067
        modrm = ldub_code(s->pc++);
4068
        reg = (modrm >> 3) & 7;
4069
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4070
        gen_op_mov_TN_reg[ot][1][reg]();
4071
        if (s->cc_op != CC_OP_DYNAMIC)
4072
            gen_op_set_cc_op(s->cc_op);
4073
        if (b == 0x102)
4074
            gen_op_lar();
4075
        else
4076
            gen_op_lsl();
4077
        s->cc_op = CC_OP_EFLAGS;
4078
        gen_op_mov_reg_T1[ot][reg]();
4079
        break;
4080
    case 0x118:
4081
        modrm = ldub_code(s->pc++);
4082
        mod = (modrm >> 6) & 3;
4083
        op = (modrm >> 3) & 7;
4084
        switch(op) {
4085
        case 0: /* prefetchnta */
4086
        case 1: /* prefetchnt0 */
4087
        case 2: /* prefetchnt0 */
4088
        case 3: /* prefetchnt0 */
4089
            if (mod == 3)
4090
                goto illegal_op;
4091
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4092
            /* nothing more to do */
4093
            break;
4094
        default:
4095
            goto illegal_op;
4096
        }
4097
        break;
4098
    case 0x120: /* mov reg, crN */
4099
    case 0x122: /* mov crN, reg */
4100
        if (s->cpl != 0) {
4101
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4102
        } else {
4103
            modrm = ldub_code(s->pc++);
4104
            if ((modrm & 0xc0) != 0xc0)
4105
                goto illegal_op;
4106
            rm = modrm & 7;
4107
            reg = (modrm >> 3) & 7;
4108
            switch(reg) {
4109
            case 0:
4110
            case 2:
4111
            case 3:
4112
            case 4:
4113
                if (b & 2) {
4114
                    gen_op_mov_TN_reg[OT_LONG][0][rm]();
4115
                    gen_op_movl_crN_T0(reg);
4116
                    gen_op_jmp_im(s->pc - s->cs_base);
4117
                    gen_eob(s);
4118
                } else {
4119
                    gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
4120
                    gen_op_mov_reg_T0[OT_LONG][rm]();
4121
                }
4122
                break;
4123
            default:
4124
                goto illegal_op;
4125
            }
4126
        }
4127
        break;
4128
    case 0x121: /* mov reg, drN */
4129
    case 0x123: /* mov drN, reg */
4130
        if (s->cpl != 0) {
4131
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4132
        } else {
4133
            modrm = ldub_code(s->pc++);
4134
            if ((modrm & 0xc0) != 0xc0)
4135
                goto illegal_op;
4136
            rm = modrm & 7;
4137
            reg = (modrm >> 3) & 7;
4138
            /* XXX: do it dynamically with CR4.DE bit */
4139
            if (reg == 4 || reg == 5)
4140
                goto illegal_op;
4141
            if (b & 2) {
4142
                gen_op_mov_TN_reg[OT_LONG][0][rm]();
4143
                gen_op_movl_drN_T0(reg);
4144
                gen_op_jmp_im(s->pc - s->cs_base);
4145
                gen_eob(s);
4146
            } else {
4147
                gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
4148
                gen_op_mov_reg_T0[OT_LONG][rm]();
4149
            }
4150
        }
4151
        break;
4152
    case 0x106: /* clts */
4153
        if (s->cpl != 0) {
4154
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4155
        } else {
4156
            gen_op_clts();
4157
            /* abort block because static cpu state changed */
4158
            gen_op_jmp_im(s->pc - s->cs_base);
4159
            gen_eob(s);
4160
        }
4161
        break;
4162
    default:
4163
        goto illegal_op;
4164
    }
4165
    /* lock generation */
4166
    if (s->prefix & PREFIX_LOCK)
4167
        gen_op_unlock();
4168
    return s->pc;
4169
 illegal_op:
4170
    if (s->prefix & PREFIX_LOCK)
4171
        gen_op_unlock();
4172
    /* XXX: ensure that no lock was generated */
4173
    gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
4174
    return s->pc;
4175
}
4176

    
4177
#define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4178
#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4179

    
4180
/* flags read by an operation */
4181
static uint16_t opc_read_flags[NB_OPS] = { 
4182
    [INDEX_op_aas] = CC_A,
4183
    [INDEX_op_aaa] = CC_A,
4184
    [INDEX_op_das] = CC_A | CC_C,
4185
    [INDEX_op_daa] = CC_A | CC_C,
4186

    
4187
    /* subtle: due to the incl/decl implementation, C is used */
4188
    [INDEX_op_update_inc_cc] = CC_C, 
4189

    
4190
    [INDEX_op_into] = CC_O,
4191

    
4192
    [INDEX_op_jb_subb] = CC_C,
4193
    [INDEX_op_jb_subw] = CC_C,
4194
    [INDEX_op_jb_subl] = CC_C,
4195

    
4196
    [INDEX_op_jz_subb] = CC_Z,
4197
    [INDEX_op_jz_subw] = CC_Z,
4198
    [INDEX_op_jz_subl] = CC_Z,
4199

    
4200
    [INDEX_op_jbe_subb] = CC_Z | CC_C,
4201
    [INDEX_op_jbe_subw] = CC_Z | CC_C,
4202
    [INDEX_op_jbe_subl] = CC_Z | CC_C,
4203

    
4204
    [INDEX_op_js_subb] = CC_S,
4205
    [INDEX_op_js_subw] = CC_S,
4206
    [INDEX_op_js_subl] = CC_S,
4207

    
4208
    [INDEX_op_jl_subb] = CC_O | CC_S,
4209
    [INDEX_op_jl_subw] = CC_O | CC_S,
4210
    [INDEX_op_jl_subl] = CC_O | CC_S,
4211

    
4212
    [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
4213
    [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
4214
    [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
4215

    
4216
    [INDEX_op_loopnzw] = CC_Z,
4217
    [INDEX_op_loopnzl] = CC_Z,
4218
    [INDEX_op_loopzw] = CC_Z,
4219
    [INDEX_op_loopzl] = CC_Z,
4220

    
4221
    [INDEX_op_seto_T0_cc] = CC_O,
4222
    [INDEX_op_setb_T0_cc] = CC_C,
4223
    [INDEX_op_setz_T0_cc] = CC_Z,
4224
    [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
4225
    [INDEX_op_sets_T0_cc] = CC_S,
4226
    [INDEX_op_setp_T0_cc] = CC_P,
4227
    [INDEX_op_setl_T0_cc] = CC_O | CC_S,
4228
    [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
4229

    
4230
    [INDEX_op_setb_T0_subb] = CC_C,
4231
    [INDEX_op_setb_T0_subw] = CC_C,
4232
    [INDEX_op_setb_T0_subl] = CC_C,
4233

    
4234
    [INDEX_op_setz_T0_subb] = CC_Z,
4235
    [INDEX_op_setz_T0_subw] = CC_Z,
4236
    [INDEX_op_setz_T0_subl] = CC_Z,
4237

    
4238
    [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
4239
    [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
4240
    [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
4241

    
4242
    [INDEX_op_sets_T0_subb] = CC_S,
4243
    [INDEX_op_sets_T0_subw] = CC_S,
4244
    [INDEX_op_sets_T0_subl] = CC_S,
4245

    
4246
    [INDEX_op_setl_T0_subb] = CC_O | CC_S,
4247
    [INDEX_op_setl_T0_subw] = CC_O | CC_S,
4248
    [INDEX_op_setl_T0_subl] = CC_O | CC_S,
4249

    
4250
    [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
4251
    [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
4252
    [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
4253

    
4254
    [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
4255
    [INDEX_op_cmc] = CC_C,
4256
    [INDEX_op_salc] = CC_C,
4257

    
4258
    /* needed for correct flag optimisation before string ops */
4259
    [INDEX_op_jz_ecxw] = CC_OSZAPC,
4260
    [INDEX_op_jz_ecxl] = CC_OSZAPC,
4261
    [INDEX_op_jz_ecxw_im] = CC_OSZAPC,
4262
    [INDEX_op_jz_ecxl_im] = CC_OSZAPC,
4263

    
4264
#define DEF_READF(SUFFIX)\
4265
    [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4266
    [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4267
    [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
4268
    [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4269
    [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4270
    [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
4271
\
4272
    [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4273
    [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4274
    [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
4275
    [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4276
    [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4277
    [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,
4278

    
4279

    
4280
    DEF_READF( )
4281
    DEF_READF(_raw)
4282
#ifndef CONFIG_USER_ONLY
4283
    DEF_READF(_kernel)
4284
    DEF_READF(_user)
4285
#endif
4286
};
4287

    
4288
/* flags written by an operation */
4289
static uint16_t opc_write_flags[NB_OPS] = { 
4290
    [INDEX_op_update2_cc] = CC_OSZAPC,
4291
    [INDEX_op_update1_cc] = CC_OSZAPC,
4292
    [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
4293
    [INDEX_op_update_neg_cc] = CC_OSZAPC,
4294
    /* subtle: due to the incl/decl implementation, C is used */
4295
    [INDEX_op_update_inc_cc] = CC_OSZAPC, 
4296
    [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
4297

    
4298
    [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
4299
    [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
4300
    [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
4301
    [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
4302
    [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
4303
    [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
4304
    [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
4305
    [INDEX_op_imull_T0_T1] = CC_OSZAPC,
4306
    
4307
    /* bcd */
4308
    [INDEX_op_aam] = CC_OSZAPC,
4309
    [INDEX_op_aad] = CC_OSZAPC,
4310
    [INDEX_op_aas] = CC_OSZAPC,
4311
    [INDEX_op_aaa] = CC_OSZAPC,
4312
    [INDEX_op_das] = CC_OSZAPC,
4313
    [INDEX_op_daa] = CC_OSZAPC,
4314

    
4315
    [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
4316
    [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
4317
    [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
4318
    [INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
4319
    [INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
4320
    [INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
4321
    [INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
4322
    [INDEX_op_clc] = CC_C,
4323
    [INDEX_op_stc] = CC_C,
4324
    [INDEX_op_cmc] = CC_C,
4325

    
4326
    [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
4327
    [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
4328
    [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
4329
    [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
4330
    [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
4331
    [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
4332
    [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
4333
    [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
4334

    
4335
    [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
4336
    [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
4337
    [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
4338
    [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
4339

    
4340
    [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
4341
    [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
4342
    [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
4343

    
4344
    [INDEX_op_cmpxchg8b] = CC_Z,
4345
    [INDEX_op_lar] = CC_Z,
4346
    [INDEX_op_lsl] = CC_Z,
4347
    [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4348
    [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4349

    
4350
#define DEF_WRITEF(SUFFIX)\
4351
    [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4352
    [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4353
    [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4354
    [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4355
    [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4356
    [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4357
\
4358
    [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4359
    [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4360
    [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4361
    [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4362
    [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4363
    [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4364
\
4365
    [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4366
    [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4367
    [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4368
    [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4369
    [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4370
    [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4371
\
4372
    [INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4373
    [INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4374
    [INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4375
\
4376
    [INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4377
    [INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4378
    [INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4379
\
4380
    [INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4381
    [INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4382
    [INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4383
\
4384
    [INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4385
    [INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4386
    [INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4387
    [INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4388
\
4389
    [INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4390
    [INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4391
    [INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4392
    [INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4393
\
4394
    [INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
4395
    [INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
4396
    [INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,
4397

    
4398

    
4399
    DEF_WRITEF( )
4400
    DEF_WRITEF(_raw)
4401
#ifndef CONFIG_USER_ONLY
4402
    DEF_WRITEF(_kernel)
4403
    DEF_WRITEF(_user)
4404
#endif
4405
};
4406

    
4407
/* simpler form of an operation if no flags need to be generated */
4408
static uint16_t opc_simpler[NB_OPS] = { 
4409
    [INDEX_op_update2_cc] = INDEX_op_nop,
4410
    [INDEX_op_update1_cc] = INDEX_op_nop,
4411
    [INDEX_op_update_neg_cc] = INDEX_op_nop,
4412
#if 0
4413
    /* broken: CC_OP logic must be rewritten */
4414
    [INDEX_op_update_inc_cc] = INDEX_op_nop,
4415
#endif
4416

    
4417
    [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4418
    [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4419
    [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
4420

    
4421
    [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
4422
    [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
4423
    [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
4424

    
4425
    [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
4426
    [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
4427
    [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
4428

    
4429
#define DEF_SIMPLER(SUFFIX)\
4430
    [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
4431
    [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
4432
    [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
4433
\
4434
    [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
4435
    [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
4436
    [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,
4437

    
4438
    DEF_SIMPLER( )
4439
    DEF_SIMPLER(_raw)
4440
#ifndef CONFIG_USER_ONLY
4441
    DEF_SIMPLER(_kernel)
4442
    DEF_SIMPLER(_user)
4443
#endif
4444
};
4445

    
4446
void optimize_flags_init(void)
4447
{
4448
    int i;
4449
    /* put default values in arrays */
4450
    for(i = 0; i < NB_OPS; i++) {
4451
        if (opc_simpler[i] == 0)
4452
            opc_simpler[i] = i;
4453
    }
4454
}
4455

    
4456
/* CPU flags computation optimization: we move backward thru the
4457
   generated code to see which flags are needed. The operation is
4458
   modified if suitable */
4459
static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
4460
{
4461
    uint16_t *opc_ptr;
4462
    int live_flags, write_flags, op;
4463

    
4464
    opc_ptr = opc_buf + opc_buf_len;
4465
    /* live_flags contains the flags needed by the next instructions
4466
       in the code. At the end of the bloc, we consider that all the
4467
       flags are live. */
4468
    live_flags = CC_OSZAPC;
4469
    while (opc_ptr > opc_buf) {
4470
        op = *--opc_ptr;
4471
        /* if none of the flags written by the instruction is used,
4472
           then we can try to find a simpler instruction */
4473
        write_flags = opc_write_flags[op];
4474
        if ((live_flags & write_flags) == 0) {
4475
            *opc_ptr = opc_simpler[op];
4476
        }
4477
        /* compute the live flags before the instruction */
4478
        live_flags &= ~write_flags;
4479
        live_flags |= opc_read_flags[op];
4480
    }
4481
}
4482

    
4483
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4484
   basic block 'tb'. If search_pc is TRUE, also generate PC
4485
   information for each intermediate instruction. */
4486
static inline int gen_intermediate_code_internal(CPUState *env,
4487
                                                 TranslationBlock *tb, 
4488
                                                 int search_pc)
4489
{
4490
    DisasContext dc1, *dc = &dc1;
4491
    uint8_t *pc_ptr;
4492
    uint16_t *gen_opc_end;
4493
    int flags, j, lj;
4494
    uint8_t *pc_start;
4495
    uint8_t *cs_base;
4496
    
4497
    /* generate intermediate code */
4498
    pc_start = (uint8_t *)tb->pc;
4499
    cs_base = (uint8_t *)tb->cs_base;
4500
    flags = tb->flags;
4501

    
4502
    dc->pe = (flags >> HF_PE_SHIFT) & 1;
4503
    dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4504
    dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4505
    dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4506
    dc->f_st = 0;
4507
    dc->vm86 = (flags >> VM_SHIFT) & 1;
4508
    dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4509
    dc->iopl = (flags >> IOPL_SHIFT) & 3;
4510
    dc->tf = (flags >> TF_SHIFT) & 1;
4511
    dc->singlestep_enabled = env->singlestep_enabled;
4512
    dc->cc_op = CC_OP_DYNAMIC;
4513
    dc->cs_base = cs_base;
4514
    dc->tb = tb;
4515
    dc->popl_esp_hack = 0;
4516
    /* select memory access functions */
4517
    dc->mem_index = 0;
4518
    if (flags & HF_SOFTMMU_MASK) {
4519
        if (dc->cpl == 3)
4520
            dc->mem_index = 6;
4521
        else
4522
            dc->mem_index = 3;
4523
    }
4524
    dc->flags = flags;
4525
    dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
4526
                    (flags & HF_INHIBIT_IRQ_MASK)
4527
#ifndef CONFIG_SOFTMMU
4528
                    || (flags & HF_SOFTMMU_MASK)
4529
#endif
4530
                    );
4531
#if 0
4532
    /* check addseg logic */
4533
    if (!dc->addseg && (dc->vm86 || !dc->pe))
4534
        printf("ERROR addseg\n");
4535
#endif
4536

    
4537
    gen_opc_ptr = gen_opc_buf;
4538
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4539
    gen_opparam_ptr = gen_opparam_buf;
4540

    
4541
    dc->is_jmp = DISAS_NEXT;
4542
    pc_ptr = pc_start;
4543
    lj = -1;
4544

    
4545
    for(;;) {
4546
        if (env->nb_breakpoints > 0) {
4547
            for(j = 0; j < env->nb_breakpoints; j++) {
4548
                if (env->breakpoints[j] == (unsigned long)pc_ptr) {
4549
                    gen_debug(dc, pc_ptr - dc->cs_base);
4550
                    break;
4551
                }
4552
            }
4553
        }
4554
        if (search_pc) {
4555
            j = gen_opc_ptr - gen_opc_buf;
4556
            if (lj < j) {
4557
                lj++;
4558
                while (lj < j)
4559
                    gen_opc_instr_start[lj++] = 0;
4560
            }
4561
            gen_opc_pc[lj] = (uint32_t)pc_ptr;
4562
            gen_opc_cc_op[lj] = dc->cc_op;
4563
            gen_opc_instr_start[lj] = 1;
4564
        }
4565
        pc_ptr = disas_insn(dc, pc_ptr);
4566
        /* stop translation if indicated */
4567
        if (dc->is_jmp)
4568
            break;
4569
        /* if single step mode, we generate only one instruction and
4570
           generate an exception */
4571
        /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
4572
           the flag and abort the translation to give the irqs a
4573
           change to be happen */
4574
        if (dc->tf || dc->singlestep_enabled || 
4575
            (flags & HF_INHIBIT_IRQ_MASK)) {
4576
            gen_op_jmp_im(pc_ptr - dc->cs_base);
4577
            gen_eob(dc);
4578
            break;
4579
        }
4580
        /* if too long translation, stop generation too */
4581
        if (gen_opc_ptr >= gen_opc_end ||
4582
            (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
4583
            gen_op_jmp_im(pc_ptr - dc->cs_base);
4584
            gen_eob(dc);
4585
            break;
4586
        }
4587
    }
4588
    *gen_opc_ptr = INDEX_op_end;
4589
    /* we don't forget to fill the last values */
4590
    if (search_pc) {
4591
        j = gen_opc_ptr - gen_opc_buf;
4592
        lj++;
4593
        while (lj <= j)
4594
            gen_opc_instr_start[lj++] = 0;
4595
    }
4596
        
4597
#ifdef DEBUG_DISAS
4598
    if (loglevel & CPU_LOG_TB_IN_ASM) {
4599
        fprintf(logfile, "----------------\n");
4600
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4601
        disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
4602
        fprintf(logfile, "\n");
4603
        if (loglevel & CPU_LOG_TB_OP) {
4604
            fprintf(logfile, "OP:\n");
4605
            dump_ops(gen_opc_buf, gen_opparam_buf);
4606
            fprintf(logfile, "\n");
4607
        }
4608
    }
4609
#endif
4610

    
4611
    /* optimize flag computations */
4612
    optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
4613

    
4614
#ifdef DEBUG_DISAS
4615
    if (loglevel & CPU_LOG_TB_OP_OPT) {
4616
        fprintf(logfile, "AFTER FLAGS OPT:\n");
4617
        dump_ops(gen_opc_buf, gen_opparam_buf);
4618
        fprintf(logfile, "\n");
4619
    }
4620
#endif
4621
    if (!search_pc)
4622
        tb->size = pc_ptr - pc_start;
4623
    return 0;
4624
}
4625

    
4626
int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
4627
{
4628
    return gen_intermediate_code_internal(env, tb, 0);
4629
}
4630

    
4631
int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
4632
{
4633
    return gen_intermediate_code_internal(env, tb, 1);
4634
}
4635