Archipelago » qemu

/*

 *  Alpha emulation cpu definitions for qemu.

 * 

 *  Copyright (c) 2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#if !defined (__CPU_ALPHA_H__)

#define __CPU_ALPHA_H__

#include "config.h"

#define TARGET_LONG_BITS 64

#include "cpu-defs.h"

#include <setjmp.h>

#include "softfloat.h"

/* XXX: put this in a common place */

#define likely(x)   __builtin_expect(!!(x), 1)

#define unlikely(x)   __builtin_expect(!!(x), 0)

#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_ALPHA

#define ICACHE_LINE_SIZE 32

#define DCACHE_LINE_SIZE 32

#define TARGET_PAGE_BITS 12

#define VA_BITS 43

/* Alpha major type */

enum {

    ALPHA_EV3  = 1,

    ALPHA_EV4  = 2,

    ALPHA_SIM  = 3,

    ALPHA_LCA  = 4,

    ALPHA_EV5  = 5, /* 21164 */

    ALPHA_EV45 = 6, /* 21064A */

    ALPHA_EV56 = 7, /* 21164A */

};

/* EV4 minor type */

enum {

    ALPHA_EV4_2 = 0,

    ALPHA_EV4_3 = 1,

};

/* LCA minor type */

enum {

    ALPHA_LCA_1 = 1, /* 21066 */

    ALPHA_LCA_2 = 2, /* 20166 */

    ALPHA_LCA_3 = 3, /* 21068 */

    ALPHA_LCA_4 = 4, /* 21068 */

    ALPHA_LCA_5 = 5, /* 21066A */

    ALPHA_LCA_6 = 6, /* 21068A */

};

/* EV5 minor type */

enum {

    ALPHA_EV5_1 = 1, /* Rev BA, CA */

    ALPHA_EV5_2 = 2, /* Rev DA, EA */

    ALPHA_EV5_3 = 3, /* Pass 3 */

    ALPHA_EV5_4 = 4, /* Pass 3.2 */

    ALPHA_EV5_5 = 5, /* Pass 4 */

};

/* EV45 minor type */

enum {

    ALPHA_EV45_1 = 1, /* Pass 1 */

    ALPHA_EV45_2 = 2, /* Pass 1.1 */

    ALPHA_EV45_3 = 3, /* Pass 2 */

};

/* EV56 minor type */

enum {

    ALPHA_EV56_1 = 1, /* Pass 1 */

    ALPHA_EV56_2 = 2, /* Pass 2 */

};

enum {

    IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */

    IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */

    IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */

    IMPLVER_21364 = 3, /* EV7 & EV79 */

};

enum {

    AMASK_BWX      = 0x00000001,

    AMASK_FIX      = 0x00000002,

    AMASK_CIX      = 0x00000004,

    AMASK_MVI      = 0x00000100,

    AMASK_TRAP     = 0x00000200,

    AMASK_PREFETCH = 0x00001000,

};

enum {

    VAX_ROUND_NORMAL = 0,

    VAX_ROUND_CHOPPED,

};

enum {

    IEEE_ROUND_NORMAL = 0,

    IEEE_ROUND_DYNAMIC,

    IEEE_ROUND_PLUS,

    IEEE_ROUND_MINUS,

    IEEE_ROUND_CHOPPED,

};

/* IEEE floating-point operations encoding */

/* Trap mode */

enum {

    FP_TRAP_I   = 0x0,

    FP_TRAP_U   = 0x1,

    FP_TRAP_S  = 0x4,

    FP_TRAP_SU  = 0x5,

    FP_TRAP_SUI = 0x7,

};

/* Rounding mode */

enum {

    FP_ROUND_CHOPPED = 0x0,

    FP_ROUND_MINUS   = 0x1,

    FP_ROUND_NORMAL  = 0x2,

    FP_ROUND_DYNAMIC = 0x3,

};

/* Internal processor registers */

/* XXX: TOFIX: most of those registers are implementation dependant */

enum {

    /* Ebox IPRs */

    IPR_CC           = 0xC0,

    IPR_CC_CTL       = 0xC1,

    IPR_VA           = 0xC2,

    IPR_VA_CTL       = 0xC4,

    IPR_VA_FORM      = 0xC3,

    /* Ibox IPRs */

    IPR_ITB_TAG      = 0x00,

    IPR_ITB_PTE      = 0x01,

    IPT_ITB_IAP      = 0x02,

    IPT_ITB_IA       = 0x03,

    IPT_ITB_IS       = 0x04,

    IPR_PMPC         = 0x05,

    IPR_EXC_ADDR     = 0x06,

    IPR_IVA_FORM     = 0x07,

    IPR_CM           = 0x09,

    IPR_IER          = 0x0A,

    IPR_SIRR         = 0x0C,

    IPR_ISUM         = 0x0D,

    IPR_HW_INT_CLR   = 0x0E,

    IPR_EXC_SUM      = 0x0F,

    IPR_PAL_BASE     = 0x10,

    IPR_I_CTL        = 0x11,

    IPR_I_STAT       = 0x16,

    IPR_IC_FLUSH     = 0x13,

    IPR_IC_FLUSH_ASM = 0x12,

    IPR_CLR_MAP      = 0x15,

    IPR_SLEEP        = 0x17,

    IPR_PCTX         = 0x40,

    IPR_PCTR_CTL     = 0x14,

    /* Mbox IPRs */

    IPR_DTB_TAG0     = 0x20,

    IPR_DTB_TAG1     = 0xA0,

    IPR_DTB_PTE0     = 0x21,

    IPR_DTB_PTE1     = 0xA1,

    IPR_DTB_ALTMODE  = 0xA6,

    IPR_DTB_IAP      = 0xA2,

    IPR_DTB_IA       = 0xA3,

    IPR_DTB_IS0      = 0x24,

    IPR_DTB_IS1      = 0xA4,

    IPR_DTB_ASN0     = 0x25,

    IPR_DTB_ASN1     = 0xA5,

    IPR_MM_STAT      = 0x27,

    IPR_M_CTL        = 0x28,

    IPR_DC_CTL       = 0x29,

    IPR_DC_STAT      = 0x2A,

    /* Cbox IPRs */

    IPR_C_DATA       = 0x2B,

    IPR_C_SHIFT      = 0x2C,

    IPR_ASN,

    IPR_ASTEN,

    IPR_ASTSR,

    IPR_DATFX,

    IPR_ESP,

    IPR_FEN,

    IPR_IPIR,

    IPR_IPL,

    IPR_KSP,

    IPR_MCES,

    IPR_PERFMON,

    IPR_PCBB,

    IPR_PRBR,

    IPR_PTBR,

    IPR_SCBB,

    IPR_SISR,

    IPR_SSP,

    IPR_SYSPTBR,

    IPR_TBCHK,

    IPR_TBIA,

    IPR_TBIAP,

    IPR_TBIS,

    IPR_TBISD,

    IPR_TBISI,

    IPR_USP,

    IPR_VIRBND,

    IPR_VPTB,

    IPR_WHAMI,

    IPR_ALT_MODE,

    IPR_LAST,

};

typedef struct CPUAlphaState CPUAlphaState;

typedef struct pal_handler_t pal_handler_t;

struct pal_handler_t {

    /* Reset */

    void (*reset)(CPUAlphaState *env);

    /* Uncorrectable hardware error */

    void (*machine_check)(CPUAlphaState *env);

    /* Arithmetic exception */

    void (*arithmetic)(CPUAlphaState *env);

    /* Interrupt / correctable hardware error */

    void (*interrupt)(CPUAlphaState *env);

    /* Data fault */

    void (*dfault)(CPUAlphaState *env);

    /* DTB miss pal */

    void (*dtb_miss_pal)(CPUAlphaState *env);

    /* DTB miss native */

    void (*dtb_miss_native)(CPUAlphaState *env);

    /* Unaligned access */

    void (*unalign)(CPUAlphaState *env);

    /* ITB miss */

    void (*itb_miss)(CPUAlphaState *env);

    /* Instruction stream access violation */

    void (*itb_acv)(CPUAlphaState *env);

    /* Reserved or privileged opcode */

    void (*opcdec)(CPUAlphaState *env);

    /* Floating point exception */

    void (*fen)(CPUAlphaState *env);

    /* Call pal instruction */

    void (*call_pal)(CPUAlphaState *env, uint32_t palcode);

};

struct CPUAlphaState {

    uint64_t ir[31];

    float64  fir[31];

    float_status fp_status;

    uint64_t fpcr;

    uint64_t pc;

    uint64_t lock;

    uint32_t pcc[2];

    uint64_t ipr[IPR_LAST];

    uint64_t ps;

    uint64_t unique;

    int saved_mode; /* Used for HW_LD / HW_ST */

    /* */

    double ft0, ft1, ft2;

    /* Those resources are used only in Qemu core */

    CPU_COMMON

    jmp_buf jmp_env;

    int user_mode_only; /* user mode only simulation */

    uint32_t hflags;

    int halted;

    int exception_index;

    int error_code;

    int interrupt_request;

    uint32_t features;

    uint32_t amask;

    int implver;

    pal_handler_t *pal_handler;

};

#include "cpu-all.h"

enum {

    FEATURE_ASN    = 0x00000001,

    FEATURE_SPS    = 0x00000002,

    FEATURE_VIRBND = 0x00000004,

    FEATURE_TBCHK  = 0x00000008,

};

enum {

    EXCP_RESET            = 0x0000,

    EXCP_MCHK             = 0x0020,

    EXCP_ARITH            = 0x0060,

    EXCP_HW_INTERRUPT     = 0x00E0,

    EXCP_DFAULT           = 0x01E0,

    EXCP_DTB_MISS_PAL     = 0x09E0,

    EXCP_ITB_MISS         = 0x03E0,

    EXCP_ITB_ACV          = 0x07E0,

    EXCP_DTB_MISS_NATIVE  = 0x08E0,

    EXCP_UNALIGN          = 0x11E0,

    EXCP_OPCDEC           = 0x13E0,

    EXCP_FEN              = 0x17E0,

    EXCP_CALL_PAL         = 0x2000,

    EXCP_CALL_PALP        = 0x3000,

    EXCP_CALL_PALE        = 0x4000,

    /* Pseudo exception for console */

    EXCP_CONSOLE_DISPATCH = 0x4001,

    EXCP_CONSOLE_FIXUP    = 0x4002,

};

/* Arithmetic exception */

enum {

    EXCP_ARITH_OVERFLOW,

};

enum {

    PALCODE_CALL = 0x00000000,

    PALCODE_LD   = 0x01000000,

    PALCODE_ST   = 0x02000000,

    PALCODE_MFPR = 0x03000000,

    PALCODE_MTPR = 0x04000000,

    PALCODE_REI  = 0x05000000,

    PALCODE_INIT = 0xF0000000,

};

enum {

    IR_V0   = 0,

    IR_T0   = 1,

    IR_T1   = 2,

    IR_T2   = 3,

    IR_T3   = 4,

    IR_T4   = 5,

    IR_T5   = 6,

    IR_T6   = 7,

    IR_T7   = 8,

    IR_S0   = 9,

    IR_S1   = 10,

    IR_S2   = 11,

    IR_S3   = 12,

    IR_S4   = 13,

    IR_S5   = 14,

    IR_S6   = 15,

#define IR_FP IR_S6

    IR_A0   = 16,

    IR_A1   = 17,

    IR_A2   = 18,

    IR_A3   = 19,

    IR_A4   = 20,

    IR_A5   = 21,

    IR_T8   = 22,

    IR_T9   = 23,

    IR_T10  = 24,

    IR_T11  = 25,

    IR_RA   = 26,

    IR_T12  = 27,

#define IR_PV IR_T12

    IR_AT   = 28,

    IR_GP   = 29,

    IR_SP   = 30,

    IR_ZERO = 31,

};

int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);

int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);

void cpu_loop_exit (void);

void pal_init (CPUState *env);

void call_pal (CPUState *env, int palcode);

#endif /* !defined (__CPU_ALPHA_H__) */

/*

 *  Alpha emulation cpu run-time definitions for qemu.

 * 

 *  Copyright (c) 2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#if !defined (__ALPHA_EXEC_H__)

#define __ALPHA_EXEC_H__

#include "config.h"

#include "dyngen-exec.h"

#define TARGET_LONG_BITS 64

register struct CPUAlphaState *env asm(AREG0);

#if TARGET_LONG_BITS > HOST_LONG_BITS

/* no registers can be used */

#define T0 (env->t0)

#define T1 (env->t1)

#define T2 (env->t2)

#else

register uint64_t T0 asm(AREG1);

register uint64_t T1 asm(AREG2);

register uint64_t T2 asm(AREG3);

#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

#define PARAM(n) ((uint64_t)PARAM##n)

#define SPARAM(n) ((int32_t)PARAM##n)

#define FT0 (env->ft0)

#define FT1 (env->ft1)

#define FT2 (env->ft2)

#define FP_STATUS (env->fp_status)

#if defined (DEBUG_OP)

#define RETURN() __asm__ __volatile__("nop" : : : "memory");

#else

#define RETURN() __asm__ __volatile__("" : : : "memory");

#endif

#include "cpu.h"

#include "exec-all.h"

#if !defined(CONFIG_USER_ONLY)

#include "softmmu_exec.h"

#endif /* !defined(CONFIG_USER_ONLY) */

static inline void env_to_regs(void)

{

}

static inline void regs_to_env(void)

{

}

int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,

                                int is_user, int is_softmmu);

int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);

int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);

void do_interrupt (CPUState *env);

#endif /* !defined (__ALPHA_EXEC_H__) */

/*

 *  Alpha emulation cpu helpers for qemu.

 * 

 *  Copyright (c) 2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdint.h>

#include <stdlib.h>

#include <stdio.h>

#include "cpu.h"

#include "exec-all.h"

#if defined(CONFIG_USER_ONLY) 

int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                                int is_user, int is_softmmu)

{

    if (rw == 2)

        env->exception_index = EXCP_ITB_MISS;

    else

        env->exception_index = EXCP_DFAULT;

    env->ipr[IPR_EXC_ADDR] = address;

    return 1;

}

target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr)

{

    return addr;

}

void do_interrupt (CPUState *env)

{

    env->exception_index = -1;

}

#else

target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr)

{

    return -1;

}

int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                                int is_user, int is_softmmu)

{

    uint32_t opc;

    if (rw == 2) {

        /* Instruction translation buffer miss */

        env->exception_index = EXCP_ITB_MISS;

    } else {

        if (env->ipr[IPR_EXC_ADDR] & 1)

            env->exception_index = EXCP_DTB_MISS_PAL;

        else

            env->exception_index = EXCP_DTB_MISS_NATIVE;

        opc = (ldl_code(env->pc) >> 21) << 4;

        if (rw) {

            opc |= 0x9;

        } else {

            opc |= 0x4;

        }

        env->ipr[IPR_MM_STAT] = opc;

    }

    return 1;

}

int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp)

{

    uint64_t hwpcb;

    int ret = 0;

    hwpcb = env->ipr[IPR_PCBB];

    switch (iprn) {

    case IPR_ASN:

        if (env->features & FEATURE_ASN)

            *valp = env->ipr[IPR_ASN];

        else

            *valp = 0;

        break;

    case IPR_ASTEN:

        *valp = ((int64_t)(env->ipr[IPR_ASTEN] << 60)) >> 60;

        break;

    case IPR_ASTSR:

        *valp = ((int64_t)(env->ipr[IPR_ASTSR] << 60)) >> 60;

        break;

    case IPR_DATFX:

        /* Write only */

        ret = -1;

        break;

    case IPR_ESP:

        if (env->features & FEATURE_SPS)

            *valp = env->ipr[IPR_ESP];

        else

            *valp = ldq_raw(hwpcb + 8);

        break;

    case IPR_FEN:

        *valp = ((int64_t)(env->ipr[IPR_FEN] << 63)) >> 63;

        break;

    case IPR_IPIR:

        /* Write-only */

        ret = -1;

        break;

    case IPR_IPL:

        *valp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;

        break;

    case IPR_KSP:

        if (!(env->ipr[IPR_EXC_ADDR] & 1)) {

            ret = -1;

        } else {

            if (env->features & FEATURE_SPS)

                *valp = env->ipr[IPR_KSP];

            else

                *valp = ldq_raw(hwpcb + 0);

        }

        break;

    case IPR_MCES:

        *valp = ((int64_t)(env->ipr[IPR_MCES] << 59)) >> 59;

        break;

    case IPR_PERFMON:

        /* Implementation specific */

        *valp = 0;

        break;

    case IPR_PCBB:

        *valp = ((int64_t)env->ipr[IPR_PCBB] << 16) >> 16;

        break;

    case IPR_PRBR:

        *valp = env->ipr[IPR_PRBR];

        break;

    case IPR_PTBR:

        *valp = env->ipr[IPR_PTBR];

        break;

    case IPR_SCBB:

        *valp = (int64_t)((int32_t)env->ipr[IPR_SCBB]);

        break;

    case IPR_SIRR:

        /* Write-only */

        ret = -1;

        break;

    case IPR_SISR:

        *valp = (int64_t)((int16_t)env->ipr[IPR_SISR]);

    case IPR_SSP:

        if (env->features & FEATURE_SPS)

            *valp = env->ipr[IPR_SSP];

        else

            *valp = ldq_raw(hwpcb + 16);

        break;

    case IPR_SYSPTBR:

        if (env->features & FEATURE_VIRBND)

            *valp = env->ipr[IPR_SYSPTBR];

        else

            ret = -1;

        break;

    case IPR_TBCHK:

        if ((env->features & FEATURE_TBCHK)) {

            /* XXX: TODO */

            *valp = 0;

            ret = -1;

        } else {

            ret = -1;

        }

        break;

    case IPR_TBIA:

        /* Write-only */

        ret = -1;

        break;

    case IPR_TBIAP:

        /* Write-only */

        ret = -1;

        break;

    case IPR_TBIS:

        /* Write-only */

        ret = -1;

        break;

    case IPR_TBISD:

        /* Write-only */

        ret = -1;

        break;

    case IPR_TBISI:

        /* Write-only */

        ret = -1;

        break;

    case IPR_USP:

        if (env->features & FEATURE_SPS)

            *valp = env->ipr[IPR_USP];

        else

            *valp = ldq_raw(hwpcb + 24);

        break;

    case IPR_VIRBND:

        if (env->features & FEATURE_VIRBND)

            *valp = env->ipr[IPR_VIRBND];

        else

            ret = -1;

        break;

    case IPR_VPTB:

        *valp = env->ipr[IPR_VPTB];

        break;

    case IPR_WHAMI:

        *valp = env->ipr[IPR_WHAMI];

        break;

    default:

        /* Invalid */

        ret = -1;

        break;

    }

    return ret;

}

int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp)

{

    uint64_t hwpcb, tmp64;

    uint8_t tmp8;

    int ret = 0;

    hwpcb = env->ipr[IPR_PCBB];

    switch (iprn) {

    case IPR_ASN:

        /* Read-only */

        ret = -1;

        break;

    case IPR_ASTEN:

        tmp8 = ((int8_t)(env->ipr[IPR_ASTEN] << 4)) >> 4;

        *oldvalp = tmp8;

        tmp8 &= val & 0xF;

        tmp8 |= (val >> 4) & 0xF;

        env->ipr[IPR_ASTEN] &= ~0xF;

        env->ipr[IPR_ASTEN] |= tmp8;

        ret = 1;

        break;

    case IPR_ASTSR:

        tmp8 = ((int8_t)(env->ipr[IPR_ASTSR] << 4)) >> 4;

        *oldvalp = tmp8;

        tmp8 &= val & 0xF;

        tmp8 |= (val >> 4) & 0xF;

        env->ipr[IPR_ASTSR] &= ~0xF;

        env->ipr[IPR_ASTSR] |= tmp8;

        ret = 1;

    case IPR_DATFX:

        env->ipr[IPR_DATFX] &= ~0x1;

        env->ipr[IPR_DATFX] |= val & 1;

        tmp64 = ldq_raw(hwpcb + 56);

        tmp64 &= ~0x8000000000000000ULL;

        tmp64 |= (val & 1) << 63;

        stq_raw(hwpcb + 56, tmp64);

        break;

    case IPR_ESP:

        if (env->features & FEATURE_SPS)

            env->ipr[IPR_ESP] = val;

        else

            stq_raw(hwpcb + 8, val);

        break;

    case IPR_FEN:

        env->ipr[IPR_FEN] = val & 1;

        tmp64 = ldq_raw(hwpcb + 56);

        tmp64 &= ~1;

        tmp64 |= val & 1;

        stq_raw(hwpcb + 56, tmp64);

        break;

    case IPR_IPIR:

        /* XXX: TODO: Send IRQ to CPU #ir[16] */

        break;

    case IPR_IPL:

        *oldvalp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;

        env->ipr[IPR_IPL] &= ~0x1F;

        env->ipr[IPR_IPL] |= val & 0x1F;

        /* XXX: may issue an interrupt or ASR _now_ */

        ret = 1;

        break;

    case IPR_KSP:

        if (!(env->ipr[IPR_EXC_ADDR] & 1)) {

            ret = -1;

        } else {

            if (env->features & FEATURE_SPS)

                env->ipr[IPR_KSP] = val;

            else

                stq_raw(hwpcb + 0, val);

        }

        break;

    case IPR_MCES:

        env->ipr[IPR_MCES] &= ~((val & 0x7) | 0x18);

        env->ipr[IPR_MCES] |= val & 0x18;

        break;

    case IPR_PERFMON:

        /* Implementation specific */

        *oldvalp = 0;

        ret = 1;

        break;

    case IPR_PCBB:

        /* Read-only */

        ret = -1;

        break;

    case IPR_PRBR:

        env->ipr[IPR_PRBR] = val;

        break;

    case IPR_PTBR:

        /* Read-only */

        ret = -1;

        break;

    case IPR_SCBB:

        env->ipr[IPR_SCBB] = (uint32_t)val;

        break;

    case IPR_SIRR:

        if (val & 0xF) {

            env->ipr[IPR_SISR] |= 1 << (val & 0xF);

            /* XXX: request a software interrupt _now_ */

        }

        break;

    case IPR_SISR:

        /* Read-only */

        ret = -1;

        break;

    case IPR_SSP:

        if (env->features & FEATURE_SPS)

            env->ipr[IPR_SSP] = val;

        else

            stq_raw(hwpcb + 16, val);

        break;

    case IPR_SYSPTBR:

        if (env->features & FEATURE_VIRBND)

            env->ipr[IPR_SYSPTBR] = val;

        else

            ret = -1;

    case IPR_TBCHK:

        /* Read-only */

        ret = -1;

        break;

    case IPR_TBIA:

        tlb_flush(env, 1);

        break;

    case IPR_TBIAP:

        tlb_flush(env, 1);

        break;

    case IPR_TBIS:

        tlb_flush_page(env, val);

        break;

    case IPR_TBISD:

        tlb_flush_page(env, val);

        break;

    case IPR_TBISI:

        tlb_flush_page(env, val);

        break;

    case IPR_USP:

        if (env->features & FEATURE_SPS)

            env->ipr[IPR_USP] = val;

        else

            stq_raw(hwpcb + 24, val);

        break;

    case IPR_VIRBND:

        if (env->features & FEATURE_VIRBND)

            env->ipr[IPR_VIRBND] = val;

        else

            ret = -1;

        break;

    case IPR_VPTB:

        env->ipr[IPR_VPTB] = val;

        break;

    case IPR_WHAMI:

        /* Read-only */

        ret = -1;

        break;

    default:

        /* Invalid */

        ret = -1;

        break;

    }

    return ret;

}

void do_interrupt (CPUState *env)

{

    int excp;

    env->ipr[IPR_EXC_ADDR] = env->pc | 1;

    excp = env->exception_index;

    env->exception_index = 0;

    env->error_code = 0;

    /* XXX: disable interrupts and memory mapping */

    if (env->ipr[IPR_PAL_BASE] != -1ULL) {

        /* We use native PALcode */

        env->pc = env->ipr[IPR_PAL_BASE] + excp;

    } else {

        /* We use emulated PALcode */

        call_pal(env);

        /* Emulate REI */

        env->pc = env->ipr[IPR_EXC_ADDR] & ~7;

        env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;

        /* XXX: re-enable interrupts and memory mapping */

    }

}

#endif

void cpu_dump_state (CPUState *env, FILE *f, 

                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),

                     int flags)

{

    static unsigned char *linux_reg_names[] = {

        "v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",

        "t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",

        "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",

        "t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",

    };

    int i;

    cpu_fprintf(f, "     PC  " TARGET_FMT_lx "      PS  " TARGET_FMT_lx "\n",

                env->pc, env->ps);

    for (i = 0; i < 31; i++) {

        cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,

                    linux_reg_names[i], env->ir[i]);

        if ((i % 3) == 2)

            cpu_fprintf(f, "\n");

    }

    cpu_fprintf(f, "\n");

    for (i = 0; i < 31; i++) {

        cpu_fprintf(f, "FIR%02d    " TARGET_FMT_lx " ", i,

                    *((uint64_t *)(&env->fir[i])));

        if ((i % 3) == 2)

            cpu_fprintf(f, "\n");

    }

    cpu_fprintf(f, "FT " TARGET_FMT_lx " " TARGET_FMT_lx " " TARGET_FMT_lx,

                *((uint64_t *)(&env->ft0)), *((uint64_t *)(&env->ft1)),

                *((uint64_t *)(&env->ft2)));

    cpu_fprintf(f, "\nMEM " TARGET_FMT_lx " %d %d\n",

                ldq_raw(0x000000004007df60ULL),

                (uint8_t *)(&env->ft0), (uint8_t *)(&env->fir[0]));

}

void cpu_dump_EA (target_ulong EA)

{

    FILE *f;

    if (logfile)

        f = logfile;

    else

        f = stdout;

    fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA);

}

/*

 *  Alpha emulation cpu micro-operations for qemu.

 * 

 *  Copyright (c) 2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#define DEBUG_OP

#include "config.h"

#include "exec.h"

#include "op_helper.h"

#define REG 0

#include "op_template.h"

#define REG 1

#include "op_template.h"

#define REG 2

#include "op_template.h"

#define REG 3

#include "op_template.h"

#define REG 4

#include "op_template.h"

#define REG 5

#include "op_template.h"

#define REG 6

#include "op_template.h"

#define REG 7

#include "op_template.h"

#define REG 8

#include "op_template.h"

#define REG 9

#include "op_template.h"

#define REG 10

#include "op_template.h"

#define REG 11

#include "op_template.h"

#define REG 12

#include "op_template.h"

#define REG 13

#include "op_template.h"

#define REG 14

#include "op_template.h"

#define REG 15

#include "op_template.h"

#define REG 16

#include "op_template.h"

#define REG 17

#include "op_template.h"

#define REG 18

#include "op_template.h"

#define REG 19

#include "op_template.h"

#define REG 20

#include "op_template.h"

#define REG 21

#include "op_template.h"

#define REG 22

#include "op_template.h"

#define REG 23

#include "op_template.h"

#define REG 24

#include "op_template.h"

#define REG 25

#include "op_template.h"

#define REG 26

#include "op_template.h"

#define REG 27

#include "op_template.h"

#define REG 28

#include "op_template.h"

#define REG 29

#include "op_template.h"

#define REG 30

#include "op_template.h"

#define REG 31

#include "op_template.h"

/* Debug stuff */

void OPPROTO op_no_op (void)

{

#if !defined (DEBUG_OP)

    __asm__ __volatile__("nop" : : : "memory");

#endif

    RETURN();

}

void OPPROTO op_tb_flush (void)

{

    helper_tb_flush();

    RETURN();

}

/* Load and stores */

#define MEMSUFFIX _raw

#include "op_mem.h"

#if !defined(CONFIG_USER_ONLY)

#define MEMSUFFIX _user

#include "op_mem.h"

#define MEMSUFFIX _kernel

#include "op_mem.h"

/* Those are used for supervisor, executive and pal modes */

#define MEMSUFFIX _data

#include "op_mem.h"

#endif

/* Special operation for load and store */

void OPPROTO op_n7 (void)

{

    T0 &= ~(uint64_t)0x7;

    RETURN();

}

/* Misc */

void OPPROTO op_excp (void)

{

    helper_excp(PARAM(1), PARAM(2));

    RETURN();

}

void OPPROTO op_load_amask (void)

{

    helper_amask();

    RETURN();

}

void OPPROTO op_load_pcc (void)

{

    helper_load_pcc();

    RETURN();

}

void OPPROTO op_load_implver (void)

{

    helper_load_implver();

    RETURN();

}

void OPPROTO op_load_fpcr (void)

{

    helper_load_fpcr();

    RETURN();

}

void OPPROTO op_store_fpcr (void)

{

    helper_store_fpcr();

    RETURN();

}

void OPPROTO op_load_irf (void)

{

    helper_load_irf();

    RETURN();

}

void OPPROTO op_set_irf (void)

{

    helper_set_irf();

    RETURN();

}

void OPPROTO op_clear_irf (void)

{

    helper_clear_irf();

    RETURN();

}

void OPPROTO op_exit_tb (void)

{

    EXIT_TB();

}

/* Arithmetic */

void OPPROTO op_addq (void)

{

    T0 += T1;

    RETURN();

}

void OPPROTO op_addqv (void)

{

    helper_addqv();

    RETURN();

}

void OPPROTO op_addl (void)

{

    T0 = (int64_t)((int32_t)(T0 + T1));

    RETURN();

}

void OPPROTO op_addlv (void)

{

    helper_addlv();

    RETURN();

}

void OPPROTO op_subq (void)

{

    T0 -= T1;

    RETURN();

}

void OPPROTO op_subqv (void)

{

    helper_subqv();

    RETURN();

}

void OPPROTO op_subl (void)

{

    T0 = (int64_t)((int32_t)(T0 - T1));

    RETURN();

}

void OPPROTO op_sublv (void)

{

    helper_sublv();

    RETURN();

}

void OPPROTO op_s4 (void)

{

    T0 <<= 2;

    RETURN();

}

void OPPROTO op_s8 (void)

{

    T0 <<= 3;

    RETURN();

}

void OPPROTO op_mull (void)

{

    T0 = (int64_t)((int32_t)T0 * (int32_t)T1);

    RETURN();

}

void OPPROTO op_mullv (void)

{

    helper_mullv();

    RETURN();

}

void OPPROTO op_mulq (void)

{

    T0 *= T1;

    RETURN();

}

void OPPROTO op_mulqv (void)

{

    helper_mulqv();

    RETURN();

}

void OPPROTO op_umulh (void)

{

    helper_umulh();

    RETURN();

}

/* Logical */

void OPPROTO op_and (void)

{

    T0 &= T1;

    RETURN();

}

void OPPROTO op_bic (void)

{

    T0 &= ~T1;

    RETURN();

}

void OPPROTO op_bis (void)

{

    T0 |= T1;

    RETURN();

}

void OPPROTO op_eqv (void)

{

    T0 ^= ~T1;

    RETURN();

}

void OPPROTO op_ornot (void)

{

    T0 |= ~T1;

    RETURN();

}

void OPPROTO op_xor (void)

{

    T0 ^= T1;

    RETURN();

}

void OPPROTO op_sll (void)

{

    T0 <<= T1;

    RETURN();

}

void OPPROTO op_srl (void)

{

    T0 >>= T1;

    RETURN();

}

void OPPROTO op_sra (void)

{

    T0 = (int64_t)T0 >> T1;

    RETURN();

}

void OPPROTO op_sextb (void)

{

    T0 = (int64_t)((int8_t)T0);

    RETURN();

}

void OPPROTO op_sextw (void)

{

    T0 = (int64_t)((int16_t)T0);

    RETURN();

}

void OPPROTO op_ctpop (void)

{

    helper_ctpop();

    RETURN();

}

void OPPROTO op_ctlz (void)

{

    helper_ctlz();

    RETURN();

}

void OPPROTO op_cttz (void)

{

    helper_cttz();

    RETURN();

}

void OPPROTO op_mskbl (void)

{

    helper_mskbl();

    RETURN();

}

void OPPROTO op_extbl (void)

{

    helper_extbl();

    RETURN();

}

void OPPROTO op_insbl (void)

{

    helper_insbl();

    RETURN();

}

void OPPROTO op_mskwl (void)

{

    helper_mskwl();

    RETURN();

}

void OPPROTO op_extwl (void)

{

    helper_extwl();

    RETURN();

}

void OPPROTO op_inswl (void)

{

    helper_inswl();

    RETURN();

}

void OPPROTO op_mskll (void)

{

    helper_mskll();

    RETURN();

}

void OPPROTO op_extll (void)

{

    helper_extll();

    RETURN();

}

void OPPROTO op_insll (void)

{

    helper_insll();

    RETURN();

}

void OPPROTO op_zap (void)

{

    helper_zap();

    RETURN();

}

void OPPROTO op_zapnot (void)

{

    helper_zapnot();

    RETURN();

}

void OPPROTO op_mskql (void)

{

    helper_mskql();

    RETURN();

}

void OPPROTO op_extql (void)

{

    helper_extql();

    RETURN();

}

void OPPROTO op_insql (void)

{

    helper_insql();

    RETURN();

}

void OPPROTO op_mskwh (void)

{

    helper_mskwh();

    RETURN();

}

void OPPROTO op_inswh (void)

{

    helper_inswh();

    RETURN();

}

void OPPROTO op_extwh (void)

{

    helper_extwh();

    RETURN();

}

void OPPROTO op_msklh (void)

{

    helper_msklh();

    RETURN();

}

void OPPROTO op_inslh (void)

{

    helper_inslh();

    RETURN();

}

void OPPROTO op_extlh (void)

{

    helper_extlh();

    RETURN();

}

void OPPROTO op_mskqh (void)

{

    helper_mskqh();

    RETURN();

}

void OPPROTO op_insqh (void)

{

    helper_insqh();

    RETURN();

}

void OPPROTO op_extqh (void)

{

    helper_extqh();

    RETURN();

}

/* Tests */

void OPPROTO op_cmpult (void)

{

    if (T0 < T1)

        T0 = 1;

    else

        T0 = 0;

    RETURN();

}

void OPPROTO op_cmpule (void)

{

    if (T0 <= T1)

        T0 = 1;