/ - Diff - qemu - Greek Research and Technology Network's projects

b/hw/integratorcp.c
99	99	return 0;
100	100	default:
101	101	cpu_abort (cpu_single_env,
102		"integratorcm_read: Unimplemented offset 0x%x\n", offset);
	102	"integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
103	103	return 0;
104	104	}
105	105	}
...	...
207	207	break;
208	208	default:
209	209	cpu_abort (cpu_single_env,
210		"integratorcm_write: Unimplemented offset 0x%x\n", offset);
	210	"integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
211	211	break;
212	212	}
213	213	}
...	...
414	414	case 3: /* CP_DECODE */
415	415	return 0x11;
416	416	default:
417		cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset);
	417	cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
	418	(int)offset);
418	419	return 0;
419	420	}
420	421	}
...	...
431	432	/* Nothing interesting implemented yet. */
432	433	break;
433	434	default:
434		cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset);
	435	cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
	436	(int)offset);
435	437	}
436	438	}
437	439	static CPUReadMemoryFunc *icp_control_readfn[] = {

b/hw/pl011.c
99	99	case 18: /* UARTDMACR */
100	100	return s->dmacr;
101	101	default:
102		cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", offset);
	102	cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
103	103	return 0;
104	104	}
105	105	}
...	...
172	172	cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
173	173	break;
174	174	default:
175		cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", offset);
	175	cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
176	176	}
177	177	}
178	178

b/hw/pl050.c
79	79	case 4: /* KMIIR */
80	80	return s->pending \| 2;
81	81	default:
82		cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", offset);
	82	cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", (int)offset);
83	83	return 0;
84	84	}
85	85	}
...	...
108	108	s->clk = value;
109	109	return;
110	110	default:
111		cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", offset);
	111	cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", (int)offset);
112	112	}
113	113	}
114	114	static CPUReadMemoryFunc *pl050_readfn[] = {

b/hw/pl080.c
243	243	return s->sync;
244	244	default:
245	245	bad_offset:
246		cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", offset);
	246	cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", (int)offset);
247	247	return 0;
248	248	}
249	249	}
...	...
305	305	break;
306	306	default:
307	307	bad_offset:
308		cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", offset);
	308	cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", (int)offset);
309	309	}
310	310	pl080_update(s);
311	311	}

b/hw/pl110.c
326	326	case 12: /* LCDLPCURR */
327	327	return s->lpbase;
328	328	default:
329		cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset);
	329	cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
330	330	return 0;
331	331	}
332	332	}
...	...
393	393	pl110_update(s);
394	394	break;
395	395	default:
396		cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset);
	396	cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
397	397	}
398	398	}
399	399

b/hw/pl181.c
333	333	return value;
334	334	}
335	335	default:
336		cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", offset);
	336	cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", (int)offset);
337	337	return 0;
338	338	}
339	339	}
...	...
405	405	}
406	406	break;
407	407	default:
408		cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", offset);
	408	cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", (int)offset);
409	409	}
410	410	pl181_update(s);
411	411	}

         case 13: /* DEFVECTADDR */
             return s->vect_addr[16];
         default:
             cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", offset);
             cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", (int)offset);
             return 0;
+        }
+    }
-...
                 cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
             break;
         default:
             cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", offset);
             cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", (int)offset);
             return;
+        }
         pl190_update(s);

b/hw/smc91c111.c
413	413	break;
414	414	}
415	415	cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n",
416		s->bank, offset);
	416	s->bank, (int)offset);
417	417	}
418	418
419	419	static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
...	...
555	555	break;
556	556	}
557	557	cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n",
558		s->bank, offset);
	558	s->bank, (int)offset);
559	559	return 0;
560	560	}
561	561

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