Revision 4d2c2b77
| ID | 4d2c2b77f3d0c59642dd2ce799a0fb4c2a91aca8 |
Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save
and load all MXCC registers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Files
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