root / hw / usb / hcd-xhci.c @ 4d5b97da
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/*
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* USB xHCI controller emulation
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*
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* Copyright (c) 2011 Securiforest
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* Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
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* Based on usb-ohci.c, emulates Renesas NEC USB 3.0
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h" |
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#include "qemu-timer.h" |
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#include "hw/usb.h" |
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#include "hw/pci.h" |
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#include "hw/msi.h" |
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#include "hw/msix.h" |
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#include "trace.h" |
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|
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//#define DEBUG_XHCI
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//#define DEBUG_DATA
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|
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#ifdef DEBUG_XHCI
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#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
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#else
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#define DPRINTF(...) do {} while (0) |
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#endif
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#define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ |
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__func__, __LINE__); abort(); } while (0) |
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|
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#define MAXPORTS_2 15 |
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#define MAXPORTS_3 15 |
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#define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
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#define MAXSLOTS 64 |
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#define MAXINTRS 16 |
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|
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#define TD_QUEUE 24 |
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|
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/* Very pessimistic, let's hope it's enough for all cases */
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#define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) |
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/* Do not deliver ER Full events. NEC's driver does some things not bound
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* to the specs when it gets them */
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#define ER_FULL_HACK
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|
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#define LEN_CAP 0x40 |
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#define LEN_OPER (0x400 + 0x10 * MAXPORTS) |
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#define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) |
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#define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) |
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|
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#define OFF_OPER LEN_CAP
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#define OFF_RUNTIME 0x1000 |
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#define OFF_DOORBELL 0x2000 |
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#define OFF_MSIX_TABLE 0x3000 |
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#define OFF_MSIX_PBA 0x3800 |
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/* must be power of 2 */
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#define LEN_REGS 0x4000 |
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|
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#if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
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#error Increase OFF_RUNTIME
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#endif
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#if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
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#error Increase OFF_DOORBELL
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#endif
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#if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
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# error Increase LEN_REGS
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#endif
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|
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/* bit definitions */
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#define USBCMD_RS (1<<0) |
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#define USBCMD_HCRST (1<<1) |
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#define USBCMD_INTE (1<<2) |
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#define USBCMD_HSEE (1<<3) |
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#define USBCMD_LHCRST (1<<7) |
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#define USBCMD_CSS (1<<8) |
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#define USBCMD_CRS (1<<9) |
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#define USBCMD_EWE (1<<10) |
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#define USBCMD_EU3S (1<<11) |
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|
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#define USBSTS_HCH (1<<0) |
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#define USBSTS_HSE (1<<2) |
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#define USBSTS_EINT (1<<3) |
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#define USBSTS_PCD (1<<4) |
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#define USBSTS_SSS (1<<8) |
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#define USBSTS_RSS (1<<9) |
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#define USBSTS_SRE (1<<10) |
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#define USBSTS_CNR (1<<11) |
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#define USBSTS_HCE (1<<12) |
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|
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#define PORTSC_CCS (1<<0) |
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#define PORTSC_PED (1<<1) |
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#define PORTSC_OCA (1<<3) |
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#define PORTSC_PR (1<<4) |
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#define PORTSC_PLS_SHIFT 5 |
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#define PORTSC_PLS_MASK 0xf |
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#define PORTSC_PP (1<<9) |
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#define PORTSC_SPEED_SHIFT 10 |
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#define PORTSC_SPEED_MASK 0xf |
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#define PORTSC_SPEED_FULL (1<<10) |
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#define PORTSC_SPEED_LOW (2<<10) |
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#define PORTSC_SPEED_HIGH (3<<10) |
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#define PORTSC_SPEED_SUPER (4<<10) |
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#define PORTSC_PIC_SHIFT 14 |
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#define PORTSC_PIC_MASK 0x3 |
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#define PORTSC_LWS (1<<16) |
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#define PORTSC_CSC (1<<17) |
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#define PORTSC_PEC (1<<18) |
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#define PORTSC_WRC (1<<19) |
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#define PORTSC_OCC (1<<20) |
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#define PORTSC_PRC (1<<21) |
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#define PORTSC_PLC (1<<22) |
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#define PORTSC_CEC (1<<23) |
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#define PORTSC_CAS (1<<24) |
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#define PORTSC_WCE (1<<25) |
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#define PORTSC_WDE (1<<26) |
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#define PORTSC_WOE (1<<27) |
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#define PORTSC_DR (1<<30) |
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#define PORTSC_WPR (1<<31) |
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|
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#define CRCR_RCS (1<<0) |
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#define CRCR_CS (1<<1) |
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#define CRCR_CA (1<<2) |
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#define CRCR_CRR (1<<3) |
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|
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#define IMAN_IP (1<<0) |
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#define IMAN_IE (1<<1) |
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|
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#define ERDP_EHB (1<<3) |
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#define TRB_SIZE 16 |
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typedef struct XHCITRB { |
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uint64_t parameter; |
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uint32_t status; |
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uint32_t control; |
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dma_addr_t addr; |
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bool ccs;
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} XHCITRB; |
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typedef enum TRBType { |
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TRB_RESERVED = 0,
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TR_NORMAL, |
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TR_SETUP, |
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TR_DATA, |
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TR_STATUS, |
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TR_ISOCH, |
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TR_LINK, |
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TR_EVDATA, |
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TR_NOOP, |
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CR_ENABLE_SLOT, |
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CR_DISABLE_SLOT, |
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CR_ADDRESS_DEVICE, |
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CR_CONFIGURE_ENDPOINT, |
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CR_EVALUATE_CONTEXT, |
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CR_RESET_ENDPOINT, |
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CR_STOP_ENDPOINT, |
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CR_SET_TR_DEQUEUE, |
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CR_RESET_DEVICE, |
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CR_FORCE_EVENT, |
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CR_NEGOTIATE_BW, |
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CR_SET_LATENCY_TOLERANCE, |
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CR_GET_PORT_BANDWIDTH, |
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CR_FORCE_HEADER, |
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CR_NOOP, |
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ER_TRANSFER = 32,
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ER_COMMAND_COMPLETE, |
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ER_PORT_STATUS_CHANGE, |
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ER_BANDWIDTH_REQUEST, |
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ER_DOORBELL, |
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ER_HOST_CONTROLLER, |
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ER_DEVICE_NOTIFICATION, |
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ER_MFINDEX_WRAP, |
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/* vendor specific bits */
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CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
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CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
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CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
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} TRBType; |
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|
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#define CR_LINK TR_LINK
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typedef enum TRBCCode { |
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CC_INVALID = 0,
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CC_SUCCESS, |
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CC_DATA_BUFFER_ERROR, |
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CC_BABBLE_DETECTED, |
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CC_USB_TRANSACTION_ERROR, |
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CC_TRB_ERROR, |
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CC_STALL_ERROR, |
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CC_RESOURCE_ERROR, |
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CC_BANDWIDTH_ERROR, |
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CC_NO_SLOTS_ERROR, |
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CC_INVALID_STREAM_TYPE_ERROR, |
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CC_SLOT_NOT_ENABLED_ERROR, |
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CC_EP_NOT_ENABLED_ERROR, |
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CC_SHORT_PACKET, |
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CC_RING_UNDERRUN, |
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CC_RING_OVERRUN, |
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CC_VF_ER_FULL, |
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CC_PARAMETER_ERROR, |
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CC_BANDWIDTH_OVERRUN, |
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CC_CONTEXT_STATE_ERROR, |
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CC_NO_PING_RESPONSE_ERROR, |
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CC_EVENT_RING_FULL_ERROR, |
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CC_INCOMPATIBLE_DEVICE_ERROR, |
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CC_MISSED_SERVICE_ERROR, |
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CC_COMMAND_RING_STOPPED, |
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CC_COMMAND_ABORTED, |
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CC_STOPPED, |
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CC_STOPPED_LENGTH_INVALID, |
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CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
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CC_ISOCH_BUFFER_OVERRUN = 31,
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CC_EVENT_LOST_ERROR, |
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CC_UNDEFINED_ERROR, |
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CC_INVALID_STREAM_ID_ERROR, |
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CC_SECONDARY_BANDWIDTH_ERROR, |
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CC_SPLIT_TRANSACTION_ERROR |
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} TRBCCode; |
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|
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#define TRB_C (1<<0) |
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#define TRB_TYPE_SHIFT 10 |
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#define TRB_TYPE_MASK 0x3f |
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#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
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|
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#define TRB_EV_ED (1<<2) |
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|
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#define TRB_TR_ENT (1<<1) |
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#define TRB_TR_ISP (1<<2) |
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#define TRB_TR_NS (1<<3) |
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#define TRB_TR_CH (1<<4) |
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#define TRB_TR_IOC (1<<5) |
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#define TRB_TR_IDT (1<<6) |
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#define TRB_TR_TBC_SHIFT 7 |
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#define TRB_TR_TBC_MASK 0x3 |
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#define TRB_TR_BEI (1<<9) |
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#define TRB_TR_TLBPC_SHIFT 16 |
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#define TRB_TR_TLBPC_MASK 0xf |
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#define TRB_TR_FRAMEID_SHIFT 20 |
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#define TRB_TR_FRAMEID_MASK 0x7ff |
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#define TRB_TR_SIA (1<<31) |
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|
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#define TRB_TR_DIR (1<<16) |
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|
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#define TRB_CR_SLOTID_SHIFT 24 |
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#define TRB_CR_SLOTID_MASK 0xff |
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#define TRB_CR_EPID_SHIFT 16 |
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#define TRB_CR_EPID_MASK 0x1f |
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|
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#define TRB_CR_BSR (1<<9) |
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#define TRB_CR_DC (1<<9) |
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|
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#define TRB_LK_TC (1<<1) |
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|
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#define TRB_INTR_SHIFT 22 |
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#define TRB_INTR_MASK 0x3ff |
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#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
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|
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#define EP_TYPE_MASK 0x7 |
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#define EP_TYPE_SHIFT 3 |
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|
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#define EP_STATE_MASK 0x7 |
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#define EP_DISABLED (0<<0) |
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#define EP_RUNNING (1<<0) |
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#define EP_HALTED (2<<0) |
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#define EP_STOPPED (3<<0) |
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#define EP_ERROR (4<<0) |
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|
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#define SLOT_STATE_MASK 0x1f |
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#define SLOT_STATE_SHIFT 27 |
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#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
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#define SLOT_ENABLED 0 |
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#define SLOT_DEFAULT 1 |
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#define SLOT_ADDRESSED 2 |
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#define SLOT_CONFIGURED 3 |
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|
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#define SLOT_CONTEXT_ENTRIES_MASK 0x1f |
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#define SLOT_CONTEXT_ENTRIES_SHIFT 27 |
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|
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typedef struct XHCIState XHCIState; |
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|
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typedef enum EPType { |
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ET_INVALID = 0,
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ET_ISO_OUT, |
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ET_BULK_OUT, |
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ET_INTR_OUT, |
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ET_CONTROL, |
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ET_ISO_IN, |
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ET_BULK_IN, |
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ET_INTR_IN, |
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} EPType; |
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|
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typedef struct XHCIRing { |
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dma_addr_t base; |
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dma_addr_t dequeue; |
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bool ccs;
|
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} XHCIRing; |
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|
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typedef struct XHCIPort { |
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XHCIState *xhci; |
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uint32_t portsc; |
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uint32_t portnr; |
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USBPort *uport; |
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uint32_t speedmask; |
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char name[16]; |
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MemoryRegion mem; |
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} XHCIPort; |
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|
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typedef struct XHCITransfer { |
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XHCIState *xhci; |
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USBPacket packet; |
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QEMUSGList sgl; |
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bool running_async;
|
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bool running_retry;
|
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bool cancelled;
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bool complete;
|
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unsigned int iso_pkts; |
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unsigned int slotid; |
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unsigned int epid; |
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bool in_xfer;
|
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bool iso_xfer;
|
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|
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unsigned int trb_count; |
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unsigned int trb_alloced; |
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XHCITRB *trbs; |
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|
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TRBCCode status; |
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|
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unsigned int pkts; |
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unsigned int pktsize; |
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unsigned int cur_pkt; |
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|
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uint64_t mfindex_kick; |
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} XHCITransfer; |
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|
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typedef struct XHCIEPContext { |
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XHCIState *xhci; |
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unsigned int slotid; |
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unsigned int epid; |
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|
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XHCIRing ring; |
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unsigned int next_xfer; |
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unsigned int comp_xfer; |
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XHCITransfer transfers[TD_QUEUE]; |
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XHCITransfer *retry; |
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EPType type; |
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dma_addr_t pctx; |
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unsigned int max_psize; |
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uint32_t state; |
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|
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/* iso xfer scheduling */
|
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unsigned int interval; |
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int64_t mfindex_last; |
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QEMUTimer *kick_timer; |
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} XHCIEPContext; |
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|
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typedef struct XHCISlot { |
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bool enabled;
|
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dma_addr_t ctx; |
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USBPort *uport; |
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unsigned int devaddr; |
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XHCIEPContext * eps[31];
|
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} XHCISlot; |
| 372 |
|
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typedef struct XHCIEvent { |
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TRBType type; |
| 375 |
TRBCCode ccode; |
| 376 |
uint64_t ptr; |
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uint32_t length; |
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uint32_t flags; |
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uint8_t slotid; |
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uint8_t epid; |
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} XHCIEvent; |
| 382 |
|
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typedef struct XHCIInterrupter { |
| 384 |
uint32_t iman; |
| 385 |
uint32_t imod; |
| 386 |
uint32_t erstsz; |
| 387 |
uint32_t erstba_low; |
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uint32_t erstba_high; |
| 389 |
uint32_t erdp_low; |
| 390 |
uint32_t erdp_high; |
| 391 |
|
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bool msix_used, er_pcs, er_full;
|
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|
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dma_addr_t er_start; |
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uint32_t er_size; |
| 396 |
unsigned int er_ep_idx; |
| 397 |
|
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XHCIEvent ev_buffer[EV_QUEUE]; |
| 399 |
unsigned int ev_buffer_put; |
| 400 |
unsigned int ev_buffer_get; |
| 401 |
|
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} XHCIInterrupter; |
| 403 |
|
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struct XHCIState {
|
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PCIDevice pci_dev; |
| 406 |
USBBus bus; |
| 407 |
qemu_irq irq; |
| 408 |
MemoryRegion mem; |
| 409 |
MemoryRegion mem_cap; |
| 410 |
MemoryRegion mem_oper; |
| 411 |
MemoryRegion mem_runtime; |
| 412 |
MemoryRegion mem_doorbell; |
| 413 |
const char *name; |
| 414 |
unsigned int devaddr; |
| 415 |
|
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/* properties */
|
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uint32_t numports_2; |
| 418 |
uint32_t numports_3; |
| 419 |
uint32_t flags; |
| 420 |
|
| 421 |
/* Operational Registers */
|
| 422 |
uint32_t usbcmd; |
| 423 |
uint32_t usbsts; |
| 424 |
uint32_t dnctrl; |
| 425 |
uint32_t crcr_low; |
| 426 |
uint32_t crcr_high; |
| 427 |
uint32_t dcbaap_low; |
| 428 |
uint32_t dcbaap_high; |
| 429 |
uint32_t config; |
| 430 |
|
| 431 |
USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; |
| 432 |
XHCIPort ports[MAXPORTS]; |
| 433 |
XHCISlot slots[MAXSLOTS]; |
| 434 |
uint32_t numports; |
| 435 |
|
| 436 |
/* Runtime Registers */
|
| 437 |
int64_t mfindex_start; |
| 438 |
QEMUTimer *mfwrap_timer; |
| 439 |
XHCIInterrupter intr[MAXINTRS]; |
| 440 |
|
| 441 |
XHCIRing cmd_ring; |
| 442 |
}; |
| 443 |
|
| 444 |
typedef struct XHCIEvRingSeg { |
| 445 |
uint32_t addr_low; |
| 446 |
uint32_t addr_high; |
| 447 |
uint32_t size; |
| 448 |
uint32_t rsvd; |
| 449 |
} XHCIEvRingSeg; |
| 450 |
|
| 451 |
enum xhci_flags {
|
| 452 |
XHCI_FLAG_USE_MSI = 1,
|
| 453 |
XHCI_FLAG_USE_MSI_X, |
| 454 |
}; |
| 455 |
|
| 456 |
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
| 457 |
unsigned int epid); |
| 458 |
static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); |
| 459 |
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); |
| 460 |
|
| 461 |
static const char *TRBType_names[] = { |
| 462 |
[TRB_RESERVED] = "TRB_RESERVED",
|
| 463 |
[TR_NORMAL] = "TR_NORMAL",
|
| 464 |
[TR_SETUP] = "TR_SETUP",
|
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[TR_DATA] = "TR_DATA",
|
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[TR_STATUS] = "TR_STATUS",
|
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[TR_ISOCH] = "TR_ISOCH",
|
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[TR_LINK] = "TR_LINK",
|
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[TR_EVDATA] = "TR_EVDATA",
|
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[TR_NOOP] = "TR_NOOP",
|
| 471 |
[CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
|
| 472 |
[CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
|
| 473 |
[CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
|
| 474 |
[CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
|
| 475 |
[CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
|
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[CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
|
| 477 |
[CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
|
| 478 |
[CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
|
| 479 |
[CR_RESET_DEVICE] = "CR_RESET_DEVICE",
|
| 480 |
[CR_FORCE_EVENT] = "CR_FORCE_EVENT",
|
| 481 |
[CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
|
| 482 |
[CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
|
| 483 |
[CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
|
| 484 |
[CR_FORCE_HEADER] = "CR_FORCE_HEADER",
|
| 485 |
[CR_NOOP] = "CR_NOOP",
|
| 486 |
[ER_TRANSFER] = "ER_TRANSFER",
|
| 487 |
[ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
|
| 488 |
[ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
|
| 489 |
[ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
|
| 490 |
[ER_DOORBELL] = "ER_DOORBELL",
|
| 491 |
[ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
|
| 492 |
[ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
|
| 493 |
[ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
|
| 494 |
[CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
|
| 495 |
[CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
|
| 496 |
[CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
|
| 497 |
}; |
| 498 |
|
| 499 |
static const char *TRBCCode_names[] = { |
| 500 |
[CC_INVALID] = "CC_INVALID",
|
| 501 |
[CC_SUCCESS] = "CC_SUCCESS",
|
| 502 |
[CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
|
| 503 |
[CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
|
| 504 |
[CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
|
| 505 |
[CC_TRB_ERROR] = "CC_TRB_ERROR",
|
| 506 |
[CC_STALL_ERROR] = "CC_STALL_ERROR",
|
| 507 |
[CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
|
| 508 |
[CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
|
| 509 |
[CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
|
| 510 |
[CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
|
| 511 |
[CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
|
| 512 |
[CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
|
| 513 |
[CC_SHORT_PACKET] = "CC_SHORT_PACKET",
|
| 514 |
[CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
|
| 515 |
[CC_RING_OVERRUN] = "CC_RING_OVERRUN",
|
| 516 |
[CC_VF_ER_FULL] = "CC_VF_ER_FULL",
|
| 517 |
[CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
|
| 518 |
[CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
|
| 519 |
[CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
|
| 520 |
[CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
|
| 521 |
[CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
|
| 522 |
[CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
|
| 523 |
[CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
|
| 524 |
[CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
|
| 525 |
[CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
|
| 526 |
[CC_STOPPED] = "CC_STOPPED",
|
| 527 |
[CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
|
| 528 |
[CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] |
| 529 |
= "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
|
| 530 |
[CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
|
| 531 |
[CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
|
| 532 |
[CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
|
| 533 |
[CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
|
| 534 |
[CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
|
| 535 |
[CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
|
| 536 |
}; |
| 537 |
|
| 538 |
static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) |
| 539 |
{
|
| 540 |
if (index >= llen || list[index] == NULL) { |
| 541 |
return "???"; |
| 542 |
} |
| 543 |
return list[index];
|
| 544 |
} |
| 545 |
|
| 546 |
static const char *trb_name(XHCITRB *trb) |
| 547 |
{
|
| 548 |
return lookup_name(TRB_TYPE(*trb), TRBType_names,
|
| 549 |
ARRAY_SIZE(TRBType_names)); |
| 550 |
} |
| 551 |
|
| 552 |
static const char *event_name(XHCIEvent *event) |
| 553 |
{
|
| 554 |
return lookup_name(event->ccode, TRBCCode_names,
|
| 555 |
ARRAY_SIZE(TRBCCode_names)); |
| 556 |
} |
| 557 |
|
| 558 |
static uint64_t xhci_mfindex_get(XHCIState *xhci)
|
| 559 |
{
|
| 560 |
int64_t now = qemu_get_clock_ns(vm_clock); |
| 561 |
return (now - xhci->mfindex_start) / 125000; |
| 562 |
} |
| 563 |
|
| 564 |
static void xhci_mfwrap_update(XHCIState *xhci) |
| 565 |
{
|
| 566 |
const uint32_t bits = USBCMD_RS | USBCMD_EWE;
|
| 567 |
uint32_t mfindex, left; |
| 568 |
int64_t now; |
| 569 |
|
| 570 |
if ((xhci->usbcmd & bits) == bits) {
|
| 571 |
now = qemu_get_clock_ns(vm_clock); |
| 572 |
mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; |
| 573 |
left = 0x4000 - mfindex;
|
| 574 |
qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
|
| 575 |
} else {
|
| 576 |
qemu_del_timer(xhci->mfwrap_timer); |
| 577 |
} |
| 578 |
} |
| 579 |
|
| 580 |
static void xhci_mfwrap_timer(void *opaque) |
| 581 |
{
|
| 582 |
XHCIState *xhci = opaque; |
| 583 |
XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
|
| 584 |
|
| 585 |
xhci_event(xhci, &wrap, 0);
|
| 586 |
xhci_mfwrap_update(xhci); |
| 587 |
} |
| 588 |
|
| 589 |
static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) |
| 590 |
{
|
| 591 |
if (sizeof(dma_addr_t) == 4) { |
| 592 |
return low;
|
| 593 |
} else {
|
| 594 |
return low | (((dma_addr_t)high << 16) << 16); |
| 595 |
} |
| 596 |
} |
| 597 |
|
| 598 |
static inline dma_addr_t xhci_mask64(uint64_t addr) |
| 599 |
{
|
| 600 |
if (sizeof(dma_addr_t) == 4) { |
| 601 |
return addr & 0xffffffff; |
| 602 |
} else {
|
| 603 |
return addr;
|
| 604 |
} |
| 605 |
} |
| 606 |
|
| 607 |
static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) |
| 608 |
{
|
| 609 |
int index;
|
| 610 |
|
| 611 |
if (!uport->dev) {
|
| 612 |
return NULL; |
| 613 |
} |
| 614 |
switch (uport->dev->speed) {
|
| 615 |
case USB_SPEED_LOW:
|
| 616 |
case USB_SPEED_FULL:
|
| 617 |
case USB_SPEED_HIGH:
|
| 618 |
index = uport->index; |
| 619 |
break;
|
| 620 |
case USB_SPEED_SUPER:
|
| 621 |
index = uport->index + xhci->numports_2; |
| 622 |
break;
|
| 623 |
default:
|
| 624 |
return NULL; |
| 625 |
} |
| 626 |
return &xhci->ports[index];
|
| 627 |
} |
| 628 |
|
| 629 |
static void xhci_intx_update(XHCIState *xhci) |
| 630 |
{
|
| 631 |
int level = 0; |
| 632 |
|
| 633 |
if (msix_enabled(&xhci->pci_dev) ||
|
| 634 |
msi_enabled(&xhci->pci_dev)) {
|
| 635 |
return;
|
| 636 |
} |
| 637 |
|
| 638 |
if (xhci->intr[0].iman & IMAN_IP && |
| 639 |
xhci->intr[0].iman & IMAN_IE &&
|
| 640 |
xhci->usbcmd & USBCMD_INTE) {
|
| 641 |
level = 1;
|
| 642 |
} |
| 643 |
|
| 644 |
trace_usb_xhci_irq_intx(level); |
| 645 |
qemu_set_irq(xhci->irq, level); |
| 646 |
} |
| 647 |
|
| 648 |
static void xhci_msix_update(XHCIState *xhci, int v) |
| 649 |
{
|
| 650 |
bool enabled;
|
| 651 |
|
| 652 |
if (!msix_enabled(&xhci->pci_dev)) {
|
| 653 |
return;
|
| 654 |
} |
| 655 |
|
| 656 |
enabled = xhci->intr[v].iman & IMAN_IE; |
| 657 |
if (enabled == xhci->intr[v].msix_used) {
|
| 658 |
return;
|
| 659 |
} |
| 660 |
|
| 661 |
if (enabled) {
|
| 662 |
trace_usb_xhci_irq_msix_use(v); |
| 663 |
msix_vector_use(&xhci->pci_dev, v); |
| 664 |
xhci->intr[v].msix_used = true;
|
| 665 |
} else {
|
| 666 |
trace_usb_xhci_irq_msix_unuse(v); |
| 667 |
msix_vector_unuse(&xhci->pci_dev, v); |
| 668 |
xhci->intr[v].msix_used = false;
|
| 669 |
} |
| 670 |
} |
| 671 |
|
| 672 |
static void xhci_intr_raise(XHCIState *xhci, int v) |
| 673 |
{
|
| 674 |
xhci->intr[v].erdp_low |= ERDP_EHB; |
| 675 |
xhci->intr[v].iman |= IMAN_IP; |
| 676 |
xhci->usbsts |= USBSTS_EINT; |
| 677 |
|
| 678 |
if (!(xhci->intr[v].iman & IMAN_IE)) {
|
| 679 |
return;
|
| 680 |
} |
| 681 |
|
| 682 |
if (!(xhci->usbcmd & USBCMD_INTE)) {
|
| 683 |
return;
|
| 684 |
} |
| 685 |
|
| 686 |
if (msix_enabled(&xhci->pci_dev)) {
|
| 687 |
trace_usb_xhci_irq_msix(v); |
| 688 |
msix_notify(&xhci->pci_dev, v); |
| 689 |
return;
|
| 690 |
} |
| 691 |
|
| 692 |
if (msi_enabled(&xhci->pci_dev)) {
|
| 693 |
trace_usb_xhci_irq_msi(v); |
| 694 |
msi_notify(&xhci->pci_dev, v); |
| 695 |
return;
|
| 696 |
} |
| 697 |
|
| 698 |
if (v == 0) { |
| 699 |
trace_usb_xhci_irq_intx(1);
|
| 700 |
qemu_set_irq(xhci->irq, 1);
|
| 701 |
} |
| 702 |
} |
| 703 |
|
| 704 |
static inline int xhci_running(XHCIState *xhci) |
| 705 |
{
|
| 706 |
return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; |
| 707 |
} |
| 708 |
|
| 709 |
static void xhci_die(XHCIState *xhci) |
| 710 |
{
|
| 711 |
xhci->usbsts |= USBSTS_HCE; |
| 712 |
fprintf(stderr, "xhci: asserted controller error\n");
|
| 713 |
} |
| 714 |
|
| 715 |
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) |
| 716 |
{
|
| 717 |
XHCIInterrupter *intr = &xhci->intr[v]; |
| 718 |
XHCITRB ev_trb; |
| 719 |
dma_addr_t addr; |
| 720 |
|
| 721 |
ev_trb.parameter = cpu_to_le64(event->ptr); |
| 722 |
ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
|
| 723 |
ev_trb.control = (event->slotid << 24) | (event->epid << 16) | |
| 724 |
event->flags | (event->type << TRB_TYPE_SHIFT); |
| 725 |
if (intr->er_pcs) {
|
| 726 |
ev_trb.control |= TRB_C; |
| 727 |
} |
| 728 |
ev_trb.control = cpu_to_le32(ev_trb.control); |
| 729 |
|
| 730 |
trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), |
| 731 |
event_name(event), ev_trb.parameter, |
| 732 |
ev_trb.status, ev_trb.control); |
| 733 |
|
| 734 |
addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; |
| 735 |
pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); |
| 736 |
|
| 737 |
intr->er_ep_idx++; |
| 738 |
if (intr->er_ep_idx >= intr->er_size) {
|
| 739 |
intr->er_ep_idx = 0;
|
| 740 |
intr->er_pcs = !intr->er_pcs; |
| 741 |
} |
| 742 |
} |
| 743 |
|
| 744 |
static void xhci_events_update(XHCIState *xhci, int v) |
| 745 |
{
|
| 746 |
XHCIInterrupter *intr = &xhci->intr[v]; |
| 747 |
dma_addr_t erdp; |
| 748 |
unsigned int dp_idx; |
| 749 |
bool do_irq = 0; |
| 750 |
|
| 751 |
if (xhci->usbsts & USBSTS_HCH) {
|
| 752 |
return;
|
| 753 |
} |
| 754 |
|
| 755 |
erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); |
| 756 |
if (erdp < intr->er_start ||
|
| 757 |
erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
|
| 758 |
fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
| 759 |
fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", |
| 760 |
v, intr->er_start, intr->er_size); |
| 761 |
xhci_die(xhci); |
| 762 |
return;
|
| 763 |
} |
| 764 |
dp_idx = (erdp - intr->er_start) / TRB_SIZE; |
| 765 |
assert(dp_idx < intr->er_size); |
| 766 |
|
| 767 |
/* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
|
| 768 |
* deadlocks when the ER is full. Hack it by holding off events until
|
| 769 |
* the driver decides to free at least half of the ring */
|
| 770 |
if (intr->er_full) {
|
| 771 |
int er_free = dp_idx - intr->er_ep_idx;
|
| 772 |
if (er_free <= 0) { |
| 773 |
er_free += intr->er_size; |
| 774 |
} |
| 775 |
if (er_free < (intr->er_size/2)) { |
| 776 |
DPRINTF("xhci_events_update(): event ring still "
|
| 777 |
"more than half full (hack)\n");
|
| 778 |
return;
|
| 779 |
} |
| 780 |
} |
| 781 |
|
| 782 |
while (intr->ev_buffer_put != intr->ev_buffer_get) {
|
| 783 |
assert(intr->er_full); |
| 784 |
if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { |
| 785 |
DPRINTF("xhci_events_update(): event ring full again\n");
|
| 786 |
#ifndef ER_FULL_HACK
|
| 787 |
XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
|
| 788 |
xhci_write_event(xhci, &full, v); |
| 789 |
#endif
|
| 790 |
do_irq = 1;
|
| 791 |
break;
|
| 792 |
} |
| 793 |
XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; |
| 794 |
xhci_write_event(xhci, event, v); |
| 795 |
intr->ev_buffer_get++; |
| 796 |
do_irq = 1;
|
| 797 |
if (intr->ev_buffer_get == EV_QUEUE) {
|
| 798 |
intr->ev_buffer_get = 0;
|
| 799 |
} |
| 800 |
} |
| 801 |
|
| 802 |
if (do_irq) {
|
| 803 |
xhci_intr_raise(xhci, v); |
| 804 |
} |
| 805 |
|
| 806 |
if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
|
| 807 |
DPRINTF("xhci_events_update(): event ring no longer full\n");
|
| 808 |
intr->er_full = 0;
|
| 809 |
} |
| 810 |
} |
| 811 |
|
| 812 |
static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) |
| 813 |
{
|
| 814 |
XHCIInterrupter *intr; |
| 815 |
dma_addr_t erdp; |
| 816 |
unsigned int dp_idx; |
| 817 |
|
| 818 |
if (v >= MAXINTRS) {
|
| 819 |
DPRINTF("intr nr out of range (%d >= %d)\n", v, MAXINTRS);
|
| 820 |
return;
|
| 821 |
} |
| 822 |
intr = &xhci->intr[v]; |
| 823 |
|
| 824 |
if (intr->er_full) {
|
| 825 |
DPRINTF("xhci_event(): ER full, queueing\n");
|
| 826 |
if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { |
| 827 |
fprintf(stderr, "xhci: event queue full, dropping event!\n");
|
| 828 |
return;
|
| 829 |
} |
| 830 |
intr->ev_buffer[intr->ev_buffer_put++] = *event; |
| 831 |
if (intr->ev_buffer_put == EV_QUEUE) {
|
| 832 |
intr->ev_buffer_put = 0;
|
| 833 |
} |
| 834 |
return;
|
| 835 |
} |
| 836 |
|
| 837 |
erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); |
| 838 |
if (erdp < intr->er_start ||
|
| 839 |
erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
|
| 840 |
fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
| 841 |
fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", |
| 842 |
v, intr->er_start, intr->er_size); |
| 843 |
xhci_die(xhci); |
| 844 |
return;
|
| 845 |
} |
| 846 |
|
| 847 |
dp_idx = (erdp - intr->er_start) / TRB_SIZE; |
| 848 |
assert(dp_idx < intr->er_size); |
| 849 |
|
| 850 |
if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { |
| 851 |
DPRINTF("xhci_event(): ER full, queueing\n");
|
| 852 |
#ifndef ER_FULL_HACK
|
| 853 |
XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
|
| 854 |
xhci_write_event(xhci, &full); |
| 855 |
#endif
|
| 856 |
intr->er_full = 1;
|
| 857 |
if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { |
| 858 |
fprintf(stderr, "xhci: event queue full, dropping event!\n");
|
| 859 |
return;
|
| 860 |
} |
| 861 |
intr->ev_buffer[intr->ev_buffer_put++] = *event; |
| 862 |
if (intr->ev_buffer_put == EV_QUEUE) {
|
| 863 |
intr->ev_buffer_put = 0;
|
| 864 |
} |
| 865 |
} else {
|
| 866 |
xhci_write_event(xhci, event, v); |
| 867 |
} |
| 868 |
|
| 869 |
xhci_intr_raise(xhci, v); |
| 870 |
} |
| 871 |
|
| 872 |
static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, |
| 873 |
dma_addr_t base) |
| 874 |
{
|
| 875 |
ring->base = base; |
| 876 |
ring->dequeue = base; |
| 877 |
ring->ccs = 1;
|
| 878 |
} |
| 879 |
|
| 880 |
static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
|
| 881 |
dma_addr_t *addr) |
| 882 |
{
|
| 883 |
while (1) { |
| 884 |
TRBType type; |
| 885 |
pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); |
| 886 |
trb->addr = ring->dequeue; |
| 887 |
trb->ccs = ring->ccs; |
| 888 |
le64_to_cpus(&trb->parameter); |
| 889 |
le32_to_cpus(&trb->status); |
| 890 |
le32_to_cpus(&trb->control); |
| 891 |
|
| 892 |
trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), |
| 893 |
trb->parameter, trb->status, trb->control); |
| 894 |
|
| 895 |
if ((trb->control & TRB_C) != ring->ccs) {
|
| 896 |
return 0; |
| 897 |
} |
| 898 |
|
| 899 |
type = TRB_TYPE(*trb); |
| 900 |
|
| 901 |
if (type != TR_LINK) {
|
| 902 |
if (addr) {
|
| 903 |
*addr = ring->dequeue; |
| 904 |
} |
| 905 |
ring->dequeue += TRB_SIZE; |
| 906 |
return type;
|
| 907 |
} else {
|
| 908 |
ring->dequeue = xhci_mask64(trb->parameter); |
| 909 |
if (trb->control & TRB_LK_TC) {
|
| 910 |
ring->ccs = !ring->ccs; |
| 911 |
} |
| 912 |
} |
| 913 |
} |
| 914 |
} |
| 915 |
|
| 916 |
static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) |
| 917 |
{
|
| 918 |
XHCITRB trb; |
| 919 |
int length = 0; |
| 920 |
dma_addr_t dequeue = ring->dequeue; |
| 921 |
bool ccs = ring->ccs;
|
| 922 |
/* hack to bundle together the two/three TDs that make a setup transfer */
|
| 923 |
bool control_td_set = 0; |
| 924 |
|
| 925 |
while (1) { |
| 926 |
TRBType type; |
| 927 |
pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); |
| 928 |
le64_to_cpus(&trb.parameter); |
| 929 |
le32_to_cpus(&trb.status); |
| 930 |
le32_to_cpus(&trb.control); |
| 931 |
|
| 932 |
if ((trb.control & TRB_C) != ccs) {
|
| 933 |
return -length;
|
| 934 |
} |
| 935 |
|
| 936 |
type = TRB_TYPE(trb); |
| 937 |
|
| 938 |
if (type == TR_LINK) {
|
| 939 |
dequeue = xhci_mask64(trb.parameter); |
| 940 |
if (trb.control & TRB_LK_TC) {
|
| 941 |
ccs = !ccs; |
| 942 |
} |
| 943 |
continue;
|
| 944 |
} |
| 945 |
|
| 946 |
length += 1;
|
| 947 |
dequeue += TRB_SIZE; |
| 948 |
|
| 949 |
if (type == TR_SETUP) {
|
| 950 |
control_td_set = 1;
|
| 951 |
} else if (type == TR_STATUS) { |
| 952 |
control_td_set = 0;
|
| 953 |
} |
| 954 |
|
| 955 |
if (!control_td_set && !(trb.control & TRB_TR_CH)) {
|
| 956 |
return length;
|
| 957 |
} |
| 958 |
} |
| 959 |
} |
| 960 |
|
| 961 |
static void xhci_er_reset(XHCIState *xhci, int v) |
| 962 |
{
|
| 963 |
XHCIInterrupter *intr = &xhci->intr[v]; |
| 964 |
XHCIEvRingSeg seg; |
| 965 |
|
| 966 |
/* cache the (sole) event ring segment location */
|
| 967 |
if (intr->erstsz != 1) { |
| 968 |
fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
|
| 969 |
xhci_die(xhci); |
| 970 |
return;
|
| 971 |
} |
| 972 |
dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); |
| 973 |
pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
|
| 974 |
le32_to_cpus(&seg.addr_low); |
| 975 |
le32_to_cpus(&seg.addr_high); |
| 976 |
le32_to_cpus(&seg.size); |
| 977 |
if (seg.size < 16 || seg.size > 4096) { |
| 978 |
fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
|
| 979 |
xhci_die(xhci); |
| 980 |
return;
|
| 981 |
} |
| 982 |
intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); |
| 983 |
intr->er_size = seg.size; |
| 984 |
|
| 985 |
intr->er_ep_idx = 0;
|
| 986 |
intr->er_pcs = 1;
|
| 987 |
intr->er_full = 0;
|
| 988 |
|
| 989 |
DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", |
| 990 |
v, intr->er_start, intr->er_size); |
| 991 |
} |
| 992 |
|
| 993 |
static void xhci_run(XHCIState *xhci) |
| 994 |
{
|
| 995 |
trace_usb_xhci_run(); |
| 996 |
xhci->usbsts &= ~USBSTS_HCH; |
| 997 |
xhci->mfindex_start = qemu_get_clock_ns(vm_clock); |
| 998 |
} |
| 999 |
|
| 1000 |
static void xhci_stop(XHCIState *xhci) |
| 1001 |
{
|
| 1002 |
trace_usb_xhci_stop(); |
| 1003 |
xhci->usbsts |= USBSTS_HCH; |
| 1004 |
xhci->crcr_low &= ~CRCR_CRR; |
| 1005 |
} |
| 1006 |
|
| 1007 |
static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, |
| 1008 |
uint32_t state) |
| 1009 |
{
|
| 1010 |
uint32_t ctx[5];
|
| 1011 |
if (epctx->state == state) {
|
| 1012 |
return;
|
| 1013 |
} |
| 1014 |
|
| 1015 |
pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
|
| 1016 |
ctx[0] &= ~EP_STATE_MASK;
|
| 1017 |
ctx[0] |= state;
|
| 1018 |
ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
|
| 1019 |
ctx[3] = (epctx->ring.dequeue >> 16) >> 16; |
| 1020 |
DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", |
| 1021 |
epctx->pctx, state, ctx[3], ctx[2]); |
| 1022 |
pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
|
| 1023 |
epctx->state = state; |
| 1024 |
} |
| 1025 |
|
| 1026 |
static void xhci_ep_kick_timer(void *opaque) |
| 1027 |
{
|
| 1028 |
XHCIEPContext *epctx = opaque; |
| 1029 |
xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); |
| 1030 |
} |
| 1031 |
|
| 1032 |
static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, |
| 1033 |
unsigned int epid, dma_addr_t pctx, |
| 1034 |
uint32_t *ctx) |
| 1035 |
{
|
| 1036 |
XHCISlot *slot; |
| 1037 |
XHCIEPContext *epctx; |
| 1038 |
dma_addr_t dequeue; |
| 1039 |
int i;
|
| 1040 |
|
| 1041 |
trace_usb_xhci_ep_enable(slotid, epid); |
| 1042 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1043 |
assert(epid >= 1 && epid <= 31); |
| 1044 |
|
| 1045 |
slot = &xhci->slots[slotid-1];
|
| 1046 |
if (slot->eps[epid-1]) { |
| 1047 |
fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
|
| 1048 |
return CC_TRB_ERROR;
|
| 1049 |
} |
| 1050 |
|
| 1051 |
epctx = g_malloc(sizeof(XHCIEPContext));
|
| 1052 |
memset(epctx, 0, sizeof(XHCIEPContext)); |
| 1053 |
epctx->xhci = xhci; |
| 1054 |
epctx->slotid = slotid; |
| 1055 |
epctx->epid = epid; |
| 1056 |
|
| 1057 |
slot->eps[epid-1] = epctx;
|
| 1058 |
|
| 1059 |
dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); |
| 1060 |
xhci_ring_init(xhci, &epctx->ring, dequeue); |
| 1061 |
epctx->ring.ccs = ctx[2] & 1; |
| 1062 |
|
| 1063 |
epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
|
| 1064 |
DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); |
| 1065 |
epctx->pctx = pctx; |
| 1066 |
epctx->max_psize = ctx[1]>>16; |
| 1067 |
epctx->max_psize *= 1+((ctx[1]>>8)&0xff); |
| 1068 |
DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
|
| 1069 |
epid/2, epid%2, epctx->max_psize); |
| 1070 |
for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { |
| 1071 |
usb_packet_init(&epctx->transfers[i].packet); |
| 1072 |
} |
| 1073 |
|
| 1074 |
epctx->interval = 1 << (ctx[0] >> 16) & 0xff; |
| 1075 |
epctx->mfindex_last = 0;
|
| 1076 |
epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); |
| 1077 |
|
| 1078 |
epctx->state = EP_RUNNING; |
| 1079 |
ctx[0] &= ~EP_STATE_MASK;
|
| 1080 |
ctx[0] |= EP_RUNNING;
|
| 1081 |
|
| 1082 |
return CC_SUCCESS;
|
| 1083 |
} |
| 1084 |
|
| 1085 |
static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, |
| 1086 |
unsigned int epid) |
| 1087 |
{
|
| 1088 |
XHCISlot *slot; |
| 1089 |
XHCIEPContext *epctx; |
| 1090 |
int i, xferi, killed = 0; |
| 1091 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1092 |
assert(epid >= 1 && epid <= 31); |
| 1093 |
|
| 1094 |
DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
|
| 1095 |
|
| 1096 |
slot = &xhci->slots[slotid-1];
|
| 1097 |
|
| 1098 |
if (!slot->eps[epid-1]) { |
| 1099 |
return 0; |
| 1100 |
} |
| 1101 |
|
| 1102 |
epctx = slot->eps[epid-1];
|
| 1103 |
|
| 1104 |
xferi = epctx->next_xfer; |
| 1105 |
for (i = 0; i < TD_QUEUE; i++) { |
| 1106 |
XHCITransfer *t = &epctx->transfers[xferi]; |
| 1107 |
if (t->running_async) {
|
| 1108 |
usb_cancel_packet(&t->packet); |
| 1109 |
t->running_async = 0;
|
| 1110 |
t->cancelled = 1;
|
| 1111 |
DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
|
| 1112 |
killed++; |
| 1113 |
} |
| 1114 |
if (t->running_retry) {
|
| 1115 |
t->running_retry = 0;
|
| 1116 |
epctx->retry = NULL;
|
| 1117 |
qemu_del_timer(epctx->kick_timer); |
| 1118 |
} |
| 1119 |
if (t->trbs) {
|
| 1120 |
g_free(t->trbs); |
| 1121 |
} |
| 1122 |
|
| 1123 |
t->trbs = NULL;
|
| 1124 |
t->trb_count = t->trb_alloced = 0;
|
| 1125 |
xferi = (xferi + 1) % TD_QUEUE;
|
| 1126 |
} |
| 1127 |
return killed;
|
| 1128 |
} |
| 1129 |
|
| 1130 |
static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, |
| 1131 |
unsigned int epid) |
| 1132 |
{
|
| 1133 |
XHCISlot *slot; |
| 1134 |
XHCIEPContext *epctx; |
| 1135 |
|
| 1136 |
trace_usb_xhci_ep_disable(slotid, epid); |
| 1137 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1138 |
assert(epid >= 1 && epid <= 31); |
| 1139 |
|
| 1140 |
slot = &xhci->slots[slotid-1];
|
| 1141 |
|
| 1142 |
if (!slot->eps[epid-1]) { |
| 1143 |
DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
|
| 1144 |
return CC_SUCCESS;
|
| 1145 |
} |
| 1146 |
|
| 1147 |
xhci_ep_nuke_xfers(xhci, slotid, epid); |
| 1148 |
|
| 1149 |
epctx = slot->eps[epid-1];
|
| 1150 |
|
| 1151 |
xhci_set_ep_state(xhci, epctx, EP_DISABLED); |
| 1152 |
|
| 1153 |
qemu_free_timer(epctx->kick_timer); |
| 1154 |
g_free(epctx); |
| 1155 |
slot->eps[epid-1] = NULL; |
| 1156 |
|
| 1157 |
return CC_SUCCESS;
|
| 1158 |
} |
| 1159 |
|
| 1160 |
static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, |
| 1161 |
unsigned int epid) |
| 1162 |
{
|
| 1163 |
XHCISlot *slot; |
| 1164 |
XHCIEPContext *epctx; |
| 1165 |
|
| 1166 |
trace_usb_xhci_ep_stop(slotid, epid); |
| 1167 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1168 |
|
| 1169 |
if (epid < 1 || epid > 31) { |
| 1170 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
| 1171 |
return CC_TRB_ERROR;
|
| 1172 |
} |
| 1173 |
|
| 1174 |
slot = &xhci->slots[slotid-1];
|
| 1175 |
|
| 1176 |
if (!slot->eps[epid-1]) { |
| 1177 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
| 1178 |
return CC_EP_NOT_ENABLED_ERROR;
|
| 1179 |
} |
| 1180 |
|
| 1181 |
if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { |
| 1182 |
fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
|
| 1183 |
"data might be lost\n");
|
| 1184 |
} |
| 1185 |
|
| 1186 |
epctx = slot->eps[epid-1];
|
| 1187 |
|
| 1188 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
| 1189 |
|
| 1190 |
return CC_SUCCESS;
|
| 1191 |
} |
| 1192 |
|
| 1193 |
static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, |
| 1194 |
unsigned int epid) |
| 1195 |
{
|
| 1196 |
XHCISlot *slot; |
| 1197 |
XHCIEPContext *epctx; |
| 1198 |
USBDevice *dev; |
| 1199 |
|
| 1200 |
trace_usb_xhci_ep_reset(slotid, epid); |
| 1201 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1202 |
|
| 1203 |
if (epid < 1 || epid > 31) { |
| 1204 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
| 1205 |
return CC_TRB_ERROR;
|
| 1206 |
} |
| 1207 |
|
| 1208 |
slot = &xhci->slots[slotid-1];
|
| 1209 |
|
| 1210 |
if (!slot->eps[epid-1]) { |
| 1211 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
| 1212 |
return CC_EP_NOT_ENABLED_ERROR;
|
| 1213 |
} |
| 1214 |
|
| 1215 |
epctx = slot->eps[epid-1];
|
| 1216 |
|
| 1217 |
if (epctx->state != EP_HALTED) {
|
| 1218 |
fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
|
| 1219 |
epid, epctx->state); |
| 1220 |
return CC_CONTEXT_STATE_ERROR;
|
| 1221 |
} |
| 1222 |
|
| 1223 |
if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { |
| 1224 |
fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
|
| 1225 |
"data might be lost\n");
|
| 1226 |
} |
| 1227 |
|
| 1228 |
uint8_t ep = epid>>1;
|
| 1229 |
|
| 1230 |
if (epid & 1) { |
| 1231 |
ep |= 0x80;
|
| 1232 |
} |
| 1233 |
|
| 1234 |
dev = xhci->slots[slotid-1].uport->dev;
|
| 1235 |
if (!dev) {
|
| 1236 |
return CC_USB_TRANSACTION_ERROR;
|
| 1237 |
} |
| 1238 |
|
| 1239 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
| 1240 |
|
| 1241 |
return CC_SUCCESS;
|
| 1242 |
} |
| 1243 |
|
| 1244 |
static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, |
| 1245 |
unsigned int epid, uint64_t pdequeue) |
| 1246 |
{
|
| 1247 |
XHCISlot *slot; |
| 1248 |
XHCIEPContext *epctx; |
| 1249 |
dma_addr_t dequeue; |
| 1250 |
|
| 1251 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1252 |
|
| 1253 |
if (epid < 1 || epid > 31) { |
| 1254 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
| 1255 |
return CC_TRB_ERROR;
|
| 1256 |
} |
| 1257 |
|
| 1258 |
trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); |
| 1259 |
dequeue = xhci_mask64(pdequeue); |
| 1260 |
|
| 1261 |
slot = &xhci->slots[slotid-1];
|
| 1262 |
|
| 1263 |
if (!slot->eps[epid-1]) { |
| 1264 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
| 1265 |
return CC_EP_NOT_ENABLED_ERROR;
|
| 1266 |
} |
| 1267 |
|
| 1268 |
epctx = slot->eps[epid-1];
|
| 1269 |
|
| 1270 |
|
| 1271 |
if (epctx->state != EP_STOPPED) {
|
| 1272 |
fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
|
| 1273 |
return CC_CONTEXT_STATE_ERROR;
|
| 1274 |
} |
| 1275 |
|
| 1276 |
xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
|
| 1277 |
epctx->ring.ccs = dequeue & 1;
|
| 1278 |
|
| 1279 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
| 1280 |
|
| 1281 |
return CC_SUCCESS;
|
| 1282 |
} |
| 1283 |
|
| 1284 |
static int xhci_xfer_map(XHCITransfer *xfer) |
| 1285 |
{
|
| 1286 |
int in_xfer = (xfer->packet.pid == USB_TOKEN_IN);
|
| 1287 |
XHCIState *xhci = xfer->xhci; |
| 1288 |
int i;
|
| 1289 |
|
| 1290 |
pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); |
| 1291 |
for (i = 0; i < xfer->trb_count; i++) { |
| 1292 |
XHCITRB *trb = &xfer->trbs[i]; |
| 1293 |
dma_addr_t addr; |
| 1294 |
unsigned int chunk = 0; |
| 1295 |
|
| 1296 |
switch (TRB_TYPE(*trb)) {
|
| 1297 |
case TR_DATA:
|
| 1298 |
if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
|
| 1299 |
fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
|
| 1300 |
goto err;
|
| 1301 |
} |
| 1302 |
/* fallthrough */
|
| 1303 |
case TR_NORMAL:
|
| 1304 |
case TR_ISOCH:
|
| 1305 |
addr = xhci_mask64(trb->parameter); |
| 1306 |
chunk = trb->status & 0x1ffff;
|
| 1307 |
if (trb->control & TRB_TR_IDT) {
|
| 1308 |
if (chunk > 8 || in_xfer) { |
| 1309 |
fprintf(stderr, "xhci: invalid immediate data TRB\n");
|
| 1310 |
goto err;
|
| 1311 |
} |
| 1312 |
qemu_sglist_add(&xfer->sgl, trb->addr, chunk); |
| 1313 |
} else {
|
| 1314 |
qemu_sglist_add(&xfer->sgl, addr, chunk); |
| 1315 |
} |
| 1316 |
break;
|
| 1317 |
} |
| 1318 |
} |
| 1319 |
|
| 1320 |
usb_packet_map(&xfer->packet, &xfer->sgl); |
| 1321 |
return 0; |
| 1322 |
|
| 1323 |
err:
|
| 1324 |
qemu_sglist_destroy(&xfer->sgl); |
| 1325 |
xhci_die(xhci); |
| 1326 |
return -1; |
| 1327 |
} |
| 1328 |
|
| 1329 |
static void xhci_xfer_unmap(XHCITransfer *xfer) |
| 1330 |
{
|
| 1331 |
usb_packet_unmap(&xfer->packet, &xfer->sgl); |
| 1332 |
qemu_sglist_destroy(&xfer->sgl); |
| 1333 |
} |
| 1334 |
|
| 1335 |
static void xhci_xfer_report(XHCITransfer *xfer) |
| 1336 |
{
|
| 1337 |
uint32_t edtla = 0;
|
| 1338 |
unsigned int left; |
| 1339 |
bool reported = 0; |
| 1340 |
bool shortpkt = 0; |
| 1341 |
XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
|
| 1342 |
XHCIState *xhci = xfer->xhci; |
| 1343 |
int i;
|
| 1344 |
|
| 1345 |
left = xfer->packet.result < 0 ? 0 : xfer->packet.result; |
| 1346 |
|
| 1347 |
for (i = 0; i < xfer->trb_count; i++) { |
| 1348 |
XHCITRB *trb = &xfer->trbs[i]; |
| 1349 |
unsigned int chunk = 0; |
| 1350 |
|
| 1351 |
switch (TRB_TYPE(*trb)) {
|
| 1352 |
case TR_DATA:
|
| 1353 |
case TR_NORMAL:
|
| 1354 |
case TR_ISOCH:
|
| 1355 |
chunk = trb->status & 0x1ffff;
|
| 1356 |
if (chunk > left) {
|
| 1357 |
chunk = left; |
| 1358 |
if (xfer->status == CC_SUCCESS) {
|
| 1359 |
shortpkt = 1;
|
| 1360 |
} |
| 1361 |
} |
| 1362 |
left -= chunk; |
| 1363 |
edtla += chunk; |
| 1364 |
break;
|
| 1365 |
case TR_STATUS:
|
| 1366 |
reported = 0;
|
| 1367 |
shortpkt = 0;
|
| 1368 |
break;
|
| 1369 |
} |
| 1370 |
|
| 1371 |
if (!reported && ((trb->control & TRB_TR_IOC) ||
|
| 1372 |
(shortpkt && (trb->control & TRB_TR_ISP)) || |
| 1373 |
(xfer->status != CC_SUCCESS))) {
|
| 1374 |
event.slotid = xfer->slotid; |
| 1375 |
event.epid = xfer->epid; |
| 1376 |
event.length = (trb->status & 0x1ffff) - chunk;
|
| 1377 |
event.flags = 0;
|
| 1378 |
event.ptr = trb->addr; |
| 1379 |
if (xfer->status == CC_SUCCESS) {
|
| 1380 |
event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; |
| 1381 |
} else {
|
| 1382 |
event.ccode = xfer->status; |
| 1383 |
} |
| 1384 |
if (TRB_TYPE(*trb) == TR_EVDATA) {
|
| 1385 |
event.ptr = trb->parameter; |
| 1386 |
event.flags |= TRB_EV_ED; |
| 1387 |
event.length = edtla & 0xffffff;
|
| 1388 |
DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
|
| 1389 |
edtla = 0;
|
| 1390 |
} |
| 1391 |
xhci_event(xhci, &event, TRB_INTR(*trb)); |
| 1392 |
reported = 1;
|
| 1393 |
if (xfer->status != CC_SUCCESS) {
|
| 1394 |
return;
|
| 1395 |
} |
| 1396 |
} |
| 1397 |
} |
| 1398 |
} |
| 1399 |
|
| 1400 |
static void xhci_stall_ep(XHCITransfer *xfer) |
| 1401 |
{
|
| 1402 |
XHCIState *xhci = xfer->xhci; |
| 1403 |
XHCISlot *slot = &xhci->slots[xfer->slotid-1];
|
| 1404 |
XHCIEPContext *epctx = slot->eps[xfer->epid-1];
|
| 1405 |
|
| 1406 |
epctx->ring.dequeue = xfer->trbs[0].addr;
|
| 1407 |
epctx->ring.ccs = xfer->trbs[0].ccs;
|
| 1408 |
xhci_set_ep_state(xhci, epctx, EP_HALTED); |
| 1409 |
DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
|
| 1410 |
DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); |
| 1411 |
} |
| 1412 |
|
| 1413 |
static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, |
| 1414 |
XHCIEPContext *epctx); |
| 1415 |
|
| 1416 |
static int xhci_setup_packet(XHCITransfer *xfer) |
| 1417 |
{
|
| 1418 |
XHCIState *xhci = xfer->xhci; |
| 1419 |
USBDevice *dev; |
| 1420 |
USBEndpoint *ep; |
| 1421 |
int dir;
|
| 1422 |
|
| 1423 |
dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; |
| 1424 |
|
| 1425 |
if (xfer->packet.ep) {
|
| 1426 |
ep = xfer->packet.ep; |
| 1427 |
dev = ep->dev; |
| 1428 |
} else {
|
| 1429 |
if (!xhci->slots[xfer->slotid-1].uport) { |
| 1430 |
fprintf(stderr, "xhci: slot %d has no device\n",
|
| 1431 |
xfer->slotid); |
| 1432 |
return -1; |
| 1433 |
} |
| 1434 |
dev = xhci->slots[xfer->slotid-1].uport->dev;
|
| 1435 |
ep = usb_ep_get(dev, dir, xfer->epid >> 1);
|
| 1436 |
} |
| 1437 |
|
| 1438 |
usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr);
|
| 1439 |
xhci_xfer_map(xfer); |
| 1440 |
DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
|
| 1441 |
xfer->packet.pid, dev->addr, ep->nr); |
| 1442 |
return 0; |
| 1443 |
} |
| 1444 |
|
| 1445 |
static int xhci_complete_packet(XHCITransfer *xfer, int ret) |
| 1446 |
{
|
| 1447 |
if (ret == USB_RET_ASYNC) {
|
| 1448 |
trace_usb_xhci_xfer_async(xfer); |
| 1449 |
xfer->running_async = 1;
|
| 1450 |
xfer->running_retry = 0;
|
| 1451 |
xfer->complete = 0;
|
| 1452 |
xfer->cancelled = 0;
|
| 1453 |
return 0; |
| 1454 |
} else if (ret == USB_RET_NAK) { |
| 1455 |
trace_usb_xhci_xfer_nak(xfer); |
| 1456 |
xfer->running_async = 0;
|
| 1457 |
xfer->running_retry = 1;
|
| 1458 |
xfer->complete = 0;
|
| 1459 |
xfer->cancelled = 0;
|
| 1460 |
return 0; |
| 1461 |
} else {
|
| 1462 |
xfer->running_async = 0;
|
| 1463 |
xfer->running_retry = 0;
|
| 1464 |
xfer->complete = 1;
|
| 1465 |
xhci_xfer_unmap(xfer); |
| 1466 |
} |
| 1467 |
|
| 1468 |
if (ret >= 0) { |
| 1469 |
trace_usb_xhci_xfer_success(xfer, ret); |
| 1470 |
xfer->status = CC_SUCCESS; |
| 1471 |
xhci_xfer_report(xfer); |
| 1472 |
return 0; |
| 1473 |
} |
| 1474 |
|
| 1475 |
/* error */
|
| 1476 |
trace_usb_xhci_xfer_error(xfer, ret); |
| 1477 |
switch (ret) {
|
| 1478 |
case USB_RET_NODEV:
|
| 1479 |
xfer->status = CC_USB_TRANSACTION_ERROR; |
| 1480 |
xhci_xfer_report(xfer); |
| 1481 |
xhci_stall_ep(xfer); |
| 1482 |
break;
|
| 1483 |
case USB_RET_STALL:
|
| 1484 |
xfer->status = CC_STALL_ERROR; |
| 1485 |
xhci_xfer_report(xfer); |
| 1486 |
xhci_stall_ep(xfer); |
| 1487 |
break;
|
| 1488 |
default:
|
| 1489 |
fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
|
| 1490 |
FIXME(); |
| 1491 |
} |
| 1492 |
return 0; |
| 1493 |
} |
| 1494 |
|
| 1495 |
static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) |
| 1496 |
{
|
| 1497 |
XHCITRB *trb_setup, *trb_status; |
| 1498 |
uint8_t bmRequestType; |
| 1499 |
int ret;
|
| 1500 |
|
| 1501 |
trb_setup = &xfer->trbs[0];
|
| 1502 |
trb_status = &xfer->trbs[xfer->trb_count-1];
|
| 1503 |
|
| 1504 |
trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); |
| 1505 |
|
| 1506 |
/* at most one Event Data TRB allowed after STATUS */
|
| 1507 |
if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { |
| 1508 |
trb_status--; |
| 1509 |
} |
| 1510 |
|
| 1511 |
/* do some sanity checks */
|
| 1512 |
if (TRB_TYPE(*trb_setup) != TR_SETUP) {
|
| 1513 |
fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
|
| 1514 |
TRB_TYPE(*trb_setup)); |
| 1515 |
return -1; |
| 1516 |
} |
| 1517 |
if (TRB_TYPE(*trb_status) != TR_STATUS) {
|
| 1518 |
fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
|
| 1519 |
TRB_TYPE(*trb_status)); |
| 1520 |
return -1; |
| 1521 |
} |
| 1522 |
if (!(trb_setup->control & TRB_TR_IDT)) {
|
| 1523 |
fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
|
| 1524 |
return -1; |
| 1525 |
} |
| 1526 |
if ((trb_setup->status & 0x1ffff) != 8) { |
| 1527 |
fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
|
| 1528 |
(trb_setup->status & 0x1ffff));
|
| 1529 |
return -1; |
| 1530 |
} |
| 1531 |
|
| 1532 |
bmRequestType = trb_setup->parameter; |
| 1533 |
|
| 1534 |
xfer->in_xfer = bmRequestType & USB_DIR_IN; |
| 1535 |
xfer->iso_xfer = false;
|
| 1536 |
|
| 1537 |
if (xhci_setup_packet(xfer) < 0) { |
| 1538 |
return -1; |
| 1539 |
} |
| 1540 |
xfer->packet.parameter = trb_setup->parameter; |
| 1541 |
|
| 1542 |
ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
| 1543 |
|
| 1544 |
xhci_complete_packet(xfer, ret); |
| 1545 |
if (!xfer->running_async && !xfer->running_retry) {
|
| 1546 |
xhci_kick_ep(xhci, xfer->slotid, xfer->epid); |
| 1547 |
} |
| 1548 |
return 0; |
| 1549 |
} |
| 1550 |
|
| 1551 |
static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
| 1552 |
XHCIEPContext *epctx, uint64_t mfindex) |
| 1553 |
{
|
| 1554 |
if (xfer->trbs[0].control & TRB_TR_SIA) { |
| 1555 |
uint64_t asap = ((mfindex + epctx->interval - 1) &
|
| 1556 |
~(epctx->interval-1));
|
| 1557 |
if (asap >= epctx->mfindex_last &&
|
| 1558 |
asap <= epctx->mfindex_last + epctx->interval * 4) {
|
| 1559 |
xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; |
| 1560 |
} else {
|
| 1561 |
xfer->mfindex_kick = asap; |
| 1562 |
} |
| 1563 |
} else {
|
| 1564 |
xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
|
| 1565 |
& TRB_TR_FRAMEID_MASK; |
| 1566 |
xfer->mfindex_kick |= mfindex & ~0x3fff;
|
| 1567 |
if (xfer->mfindex_kick < mfindex) {
|
| 1568 |
xfer->mfindex_kick += 0x4000;
|
| 1569 |
} |
| 1570 |
} |
| 1571 |
} |
| 1572 |
|
| 1573 |
static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
| 1574 |
XHCIEPContext *epctx, uint64_t mfindex) |
| 1575 |
{
|
| 1576 |
if (xfer->mfindex_kick > mfindex) {
|
| 1577 |
qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + |
| 1578 |
(xfer->mfindex_kick - mfindex) * 125000);
|
| 1579 |
xfer->running_retry = 1;
|
| 1580 |
} else {
|
| 1581 |
epctx->mfindex_last = xfer->mfindex_kick; |
| 1582 |
qemu_del_timer(epctx->kick_timer); |
| 1583 |
xfer->running_retry = 0;
|
| 1584 |
} |
| 1585 |
} |
| 1586 |
|
| 1587 |
|
| 1588 |
static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
| 1589 |
{
|
| 1590 |
uint64_t mfindex; |
| 1591 |
int ret;
|
| 1592 |
|
| 1593 |
DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
|
| 1594 |
|
| 1595 |
xfer->in_xfer = epctx->type>>2;
|
| 1596 |
|
| 1597 |
switch(epctx->type) {
|
| 1598 |
case ET_INTR_OUT:
|
| 1599 |
case ET_INTR_IN:
|
| 1600 |
case ET_BULK_OUT:
|
| 1601 |
case ET_BULK_IN:
|
| 1602 |
xfer->pkts = 0;
|
| 1603 |
xfer->iso_xfer = false;
|
| 1604 |
break;
|
| 1605 |
case ET_ISO_OUT:
|
| 1606 |
case ET_ISO_IN:
|
| 1607 |
xfer->pkts = 1;
|
| 1608 |
xfer->iso_xfer = true;
|
| 1609 |
mfindex = xhci_mfindex_get(xhci); |
| 1610 |
xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); |
| 1611 |
xhci_check_iso_kick(xhci, xfer, epctx, mfindex); |
| 1612 |
if (xfer->running_retry) {
|
| 1613 |
return -1; |
| 1614 |
} |
| 1615 |
break;
|
| 1616 |
default:
|
| 1617 |
fprintf(stderr, "xhci: unknown or unhandled EP "
|
| 1618 |
"(type %d, in %d, ep %02x)\n",
|
| 1619 |
epctx->type, xfer->in_xfer, xfer->epid); |
| 1620 |
return -1; |
| 1621 |
} |
| 1622 |
|
| 1623 |
if (xhci_setup_packet(xfer) < 0) { |
| 1624 |
return -1; |
| 1625 |
} |
| 1626 |
ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
| 1627 |
|
| 1628 |
xhci_complete_packet(xfer, ret); |
| 1629 |
if (!xfer->running_async && !xfer->running_retry) {
|
| 1630 |
xhci_kick_ep(xhci, xfer->slotid, xfer->epid); |
| 1631 |
} |
| 1632 |
return 0; |
| 1633 |
} |
| 1634 |
|
| 1635 |
static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
| 1636 |
{
|
| 1637 |
trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); |
| 1638 |
return xhci_submit(xhci, xfer, epctx);
|
| 1639 |
} |
| 1640 |
|
| 1641 |
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) |
| 1642 |
{
|
| 1643 |
XHCIEPContext *epctx; |
| 1644 |
uint64_t mfindex; |
| 1645 |
int length;
|
| 1646 |
int i;
|
| 1647 |
|
| 1648 |
trace_usb_xhci_ep_kick(slotid, epid); |
| 1649 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1650 |
assert(epid >= 1 && epid <= 31); |
| 1651 |
|
| 1652 |
if (!xhci->slots[slotid-1].enabled) { |
| 1653 |
fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
|
| 1654 |
return;
|
| 1655 |
} |
| 1656 |
epctx = xhci->slots[slotid-1].eps[epid-1]; |
| 1657 |
if (!epctx) {
|
| 1658 |
fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
|
| 1659 |
epid, slotid); |
| 1660 |
return;
|
| 1661 |
} |
| 1662 |
|
| 1663 |
if (epctx->retry) {
|
| 1664 |
XHCITransfer *xfer = epctx->retry; |
| 1665 |
int result;
|
| 1666 |
|
| 1667 |
trace_usb_xhci_xfer_retry(xfer); |
| 1668 |
assert(xfer->running_retry); |
| 1669 |
if (xfer->iso_xfer) {
|
| 1670 |
/* retry delayed iso transfer */
|
| 1671 |
mfindex = xhci_mfindex_get(xhci); |
| 1672 |
xhci_check_iso_kick(xhci, xfer, epctx, mfindex); |
| 1673 |
if (xfer->running_retry) {
|
| 1674 |
return;
|
| 1675 |
} |
| 1676 |
if (xhci_setup_packet(xfer) < 0) { |
| 1677 |
return;
|
| 1678 |
} |
| 1679 |
result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
| 1680 |
assert(result != USB_RET_NAK); |
| 1681 |
xhci_complete_packet(xfer, result); |
| 1682 |
} else {
|
| 1683 |
/* retry nak'ed transfer */
|
| 1684 |
if (xhci_setup_packet(xfer) < 0) { |
| 1685 |
return;
|
| 1686 |
} |
| 1687 |
result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
| 1688 |
if (result == USB_RET_NAK) {
|
| 1689 |
return;
|
| 1690 |
} |
| 1691 |
xhci_complete_packet(xfer, result); |
| 1692 |
} |
| 1693 |
assert(!xfer->running_retry); |
| 1694 |
epctx->retry = NULL;
|
| 1695 |
} |
| 1696 |
|
| 1697 |
if (epctx->state == EP_HALTED) {
|
| 1698 |
DPRINTF("xhci: ep halted, not running schedule\n");
|
| 1699 |
return;
|
| 1700 |
} |
| 1701 |
|
| 1702 |
xhci_set_ep_state(xhci, epctx, EP_RUNNING); |
| 1703 |
|
| 1704 |
while (1) { |
| 1705 |
XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; |
| 1706 |
if (xfer->running_async || xfer->running_retry) {
|
| 1707 |
break;
|
| 1708 |
} |
| 1709 |
length = xhci_ring_chain_length(xhci, &epctx->ring); |
| 1710 |
if (length < 0) { |
| 1711 |
break;
|
| 1712 |
} else if (length == 0) { |
| 1713 |
break;
|
| 1714 |
} |
| 1715 |
if (xfer->trbs && xfer->trb_alloced < length) {
|
| 1716 |
xfer->trb_count = 0;
|
| 1717 |
xfer->trb_alloced = 0;
|
| 1718 |
g_free(xfer->trbs); |
| 1719 |
xfer->trbs = NULL;
|
| 1720 |
} |
| 1721 |
if (!xfer->trbs) {
|
| 1722 |
xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
|
| 1723 |
xfer->trb_alloced = length; |
| 1724 |
} |
| 1725 |
xfer->trb_count = length; |
| 1726 |
|
| 1727 |
for (i = 0; i < length; i++) { |
| 1728 |
assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
|
| 1729 |
} |
| 1730 |
xfer->xhci = xhci; |
| 1731 |
xfer->epid = epid; |
| 1732 |
xfer->slotid = slotid; |
| 1733 |
|
| 1734 |
if (epid == 1) { |
| 1735 |
if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { |
| 1736 |
epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
|
| 1737 |
} else {
|
| 1738 |
fprintf(stderr, "xhci: error firing CTL transfer\n");
|
| 1739 |
} |
| 1740 |
} else {
|
| 1741 |
if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { |
| 1742 |
epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
|
| 1743 |
} else {
|
| 1744 |
if (!xfer->iso_xfer) {
|
| 1745 |
fprintf(stderr, "xhci: error firing data transfer\n");
|
| 1746 |
} |
| 1747 |
} |
| 1748 |
} |
| 1749 |
|
| 1750 |
if (epctx->state == EP_HALTED) {
|
| 1751 |
break;
|
| 1752 |
} |
| 1753 |
if (xfer->running_retry) {
|
| 1754 |
DPRINTF("xhci: xfer nacked, stopping schedule\n");
|
| 1755 |
epctx->retry = xfer; |
| 1756 |
break;
|
| 1757 |
} |
| 1758 |
} |
| 1759 |
} |
| 1760 |
|
| 1761 |
static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) |
| 1762 |
{
|
| 1763 |
trace_usb_xhci_slot_enable(slotid); |
| 1764 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1765 |
xhci->slots[slotid-1].enabled = 1; |
| 1766 |
xhci->slots[slotid-1].uport = NULL; |
| 1767 |
memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); |
| 1768 |
|
| 1769 |
return CC_SUCCESS;
|
| 1770 |
} |
| 1771 |
|
| 1772 |
static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) |
| 1773 |
{
|
| 1774 |
int i;
|
| 1775 |
|
| 1776 |
trace_usb_xhci_slot_disable(slotid); |
| 1777 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1778 |
|
| 1779 |
for (i = 1; i <= 31; i++) { |
| 1780 |
if (xhci->slots[slotid-1].eps[i-1]) { |
| 1781 |
xhci_disable_ep(xhci, slotid, i); |
| 1782 |
} |
| 1783 |
} |
| 1784 |
|
| 1785 |
xhci->slots[slotid-1].enabled = 0; |
| 1786 |
return CC_SUCCESS;
|
| 1787 |
} |
| 1788 |
|
| 1789 |
static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
|
| 1790 |
{
|
| 1791 |
USBPort *uport; |
| 1792 |
char path[32]; |
| 1793 |
int i, pos, port;
|
| 1794 |
|
| 1795 |
port = (slot_ctx[1]>>16) & 0xFF; |
| 1796 |
port = xhci->ports[port-1].uport->index+1; |
| 1797 |
pos = snprintf(path, sizeof(path), "%d", port); |
| 1798 |
for (i = 0; i < 5; i++) { |
| 1799 |
port = (slot_ctx[0] >> 4*i) & 0x0f; |
| 1800 |
if (!port) {
|
| 1801 |
break;
|
| 1802 |
} |
| 1803 |
pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); |
| 1804 |
} |
| 1805 |
|
| 1806 |
QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
|
| 1807 |
if (strcmp(uport->path, path) == 0) { |
| 1808 |
return uport;
|
| 1809 |
} |
| 1810 |
} |
| 1811 |
return NULL; |
| 1812 |
} |
| 1813 |
|
| 1814 |
static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, |
| 1815 |
uint64_t pictx, bool bsr)
|
| 1816 |
{
|
| 1817 |
XHCISlot *slot; |
| 1818 |
USBPort *uport; |
| 1819 |
USBDevice *dev; |
| 1820 |
dma_addr_t ictx, octx, dcbaap; |
| 1821 |
uint64_t poctx; |
| 1822 |
uint32_t ictl_ctx[2];
|
| 1823 |
uint32_t slot_ctx[4];
|
| 1824 |
uint32_t ep0_ctx[5];
|
| 1825 |
int i;
|
| 1826 |
TRBCCode res; |
| 1827 |
|
| 1828 |
trace_usb_xhci_slot_address(slotid); |
| 1829 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1830 |
|
| 1831 |
dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); |
| 1832 |
pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); |
| 1833 |
ictx = xhci_mask64(pictx); |
| 1834 |
octx = xhci_mask64(le64_to_cpu(poctx)); |
| 1835 |
|
| 1836 |
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
| 1837 |
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
| 1838 |
|
| 1839 |
pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
|
| 1840 |
|
| 1841 |
if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { |
| 1842 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
| 1843 |
ictl_ctx[0], ictl_ctx[1]); |
| 1844 |
return CC_TRB_ERROR;
|
| 1845 |
} |
| 1846 |
|
| 1847 |
pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); |
| 1848 |
pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); |
| 1849 |
|
| 1850 |
DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
|
| 1851 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
| 1852 |
|
| 1853 |
DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
|
| 1854 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
| 1855 |
|
| 1856 |
uport = xhci_lookup_uport(xhci, slot_ctx); |
| 1857 |
if (uport == NULL) { |
| 1858 |
fprintf(stderr, "xhci: port not found\n");
|
| 1859 |
return CC_TRB_ERROR;
|
| 1860 |
} |
| 1861 |
|
| 1862 |
dev = uport->dev; |
| 1863 |
if (!dev) {
|
| 1864 |
fprintf(stderr, "xhci: port %s not connected\n", uport->path);
|
| 1865 |
return CC_USB_TRANSACTION_ERROR;
|
| 1866 |
} |
| 1867 |
|
| 1868 |
for (i = 0; i < MAXSLOTS; i++) { |
| 1869 |
if (xhci->slots[i].uport == uport) {
|
| 1870 |
fprintf(stderr, "xhci: port %s already assigned to slot %d\n",
|
| 1871 |
uport->path, i+1);
|
| 1872 |
return CC_TRB_ERROR;
|
| 1873 |
} |
| 1874 |
} |
| 1875 |
|
| 1876 |
slot = &xhci->slots[slotid-1];
|
| 1877 |
slot->uport = uport; |
| 1878 |
slot->ctx = octx; |
| 1879 |
|
| 1880 |
if (bsr) {
|
| 1881 |
slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
|
| 1882 |
} else {
|
| 1883 |
slot->devaddr = xhci->devaddr++; |
| 1884 |
slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
|
| 1885 |
DPRINTF("xhci: device address is %d\n", slot->devaddr);
|
| 1886 |
usb_device_handle_control(dev, NULL,
|
| 1887 |
DeviceOutRequest | USB_REQ_SET_ADDRESS, |
| 1888 |
slot->devaddr, 0, 0, NULL); |
| 1889 |
} |
| 1890 |
|
| 1891 |
res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); |
| 1892 |
|
| 1893 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
| 1894 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
| 1895 |
DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
|
| 1896 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
| 1897 |
|
| 1898 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 1899 |
pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
| 1900 |
|
| 1901 |
return res;
|
| 1902 |
} |
| 1903 |
|
| 1904 |
|
| 1905 |
static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, |
| 1906 |
uint64_t pictx, bool dc)
|
| 1907 |
{
|
| 1908 |
dma_addr_t ictx, octx; |
| 1909 |
uint32_t ictl_ctx[2];
|
| 1910 |
uint32_t slot_ctx[4];
|
| 1911 |
uint32_t islot_ctx[4];
|
| 1912 |
uint32_t ep_ctx[5];
|
| 1913 |
int i;
|
| 1914 |
TRBCCode res; |
| 1915 |
|
| 1916 |
trace_usb_xhci_slot_configure(slotid); |
| 1917 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 1918 |
|
| 1919 |
ictx = xhci_mask64(pictx); |
| 1920 |
octx = xhci->slots[slotid-1].ctx;
|
| 1921 |
|
| 1922 |
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
| 1923 |
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
| 1924 |
|
| 1925 |
if (dc) {
|
| 1926 |
for (i = 2; i <= 31; i++) { |
| 1927 |
if (xhci->slots[slotid-1].eps[i-1]) { |
| 1928 |
xhci_disable_ep(xhci, slotid, i); |
| 1929 |
} |
| 1930 |
} |
| 1931 |
|
| 1932 |
pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 1933 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
| 1934 |
slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
|
| 1935 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
| 1936 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
| 1937 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 1938 |
|
| 1939 |
return CC_SUCCESS;
|
| 1940 |
} |
| 1941 |
|
| 1942 |
pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
|
| 1943 |
|
| 1944 |
if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { |
| 1945 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
| 1946 |
ictl_ctx[0], ictl_ctx[1]); |
| 1947 |
return CC_TRB_ERROR;
|
| 1948 |
} |
| 1949 |
|
| 1950 |
pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); |
| 1951 |
pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 1952 |
|
| 1953 |
if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { |
| 1954 |
fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); |
| 1955 |
return CC_CONTEXT_STATE_ERROR;
|
| 1956 |
} |
| 1957 |
|
| 1958 |
for (i = 2; i <= 31; i++) { |
| 1959 |
if (ictl_ctx[0] & (1<<i)) { |
| 1960 |
xhci_disable_ep(xhci, slotid, i); |
| 1961 |
} |
| 1962 |
if (ictl_ctx[1] & (1<<i)) { |
| 1963 |
pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, |
| 1964 |
sizeof(ep_ctx));
|
| 1965 |
DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
|
| 1966 |
i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], |
| 1967 |
ep_ctx[3], ep_ctx[4]); |
| 1968 |
xhci_disable_ep(xhci, slotid, i); |
| 1969 |
res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
|
| 1970 |
if (res != CC_SUCCESS) {
|
| 1971 |
return res;
|
| 1972 |
} |
| 1973 |
DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
|
| 1974 |
i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], |
| 1975 |
ep_ctx[3], ep_ctx[4]); |
| 1976 |
pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); |
| 1977 |
} |
| 1978 |
} |
| 1979 |
|
| 1980 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
| 1981 |
slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
|
| 1982 |
slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
|
| 1983 |
slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << |
| 1984 |
SLOT_CONTEXT_ENTRIES_SHIFT); |
| 1985 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
| 1986 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
| 1987 |
|
| 1988 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 1989 |
|
| 1990 |
return CC_SUCCESS;
|
| 1991 |
} |
| 1992 |
|
| 1993 |
|
| 1994 |
static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, |
| 1995 |
uint64_t pictx) |
| 1996 |
{
|
| 1997 |
dma_addr_t ictx, octx; |
| 1998 |
uint32_t ictl_ctx[2];
|
| 1999 |
uint32_t iep0_ctx[5];
|
| 2000 |
uint32_t ep0_ctx[5];
|
| 2001 |
uint32_t islot_ctx[4];
|
| 2002 |
uint32_t slot_ctx[4];
|
| 2003 |
|
| 2004 |
trace_usb_xhci_slot_evaluate(slotid); |
| 2005 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 2006 |
|
| 2007 |
ictx = xhci_mask64(pictx); |
| 2008 |
octx = xhci->slots[slotid-1].ctx;
|
| 2009 |
|
| 2010 |
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
| 2011 |
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
| 2012 |
|
| 2013 |
pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
|
| 2014 |
|
| 2015 |
if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { |
| 2016 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
| 2017 |
ictl_ctx[0], ictl_ctx[1]); |
| 2018 |
return CC_TRB_ERROR;
|
| 2019 |
} |
| 2020 |
|
| 2021 |
if (ictl_ctx[1] & 0x1) { |
| 2022 |
pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); |
| 2023 |
|
| 2024 |
DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
|
| 2025 |
islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); |
| 2026 |
|
| 2027 |
pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 2028 |
|
| 2029 |
slot_ctx[1] &= ~0xFFFF; /* max exit latency */ |
| 2030 |
slot_ctx[1] |= islot_ctx[1] & 0xFFFF; |
| 2031 |
slot_ctx[2] &= ~0xFF00000; /* interrupter target */ |
| 2032 |
slot_ctx[2] |= islot_ctx[2] & 0xFF000000; |
| 2033 |
|
| 2034 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
| 2035 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
| 2036 |
|
| 2037 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 2038 |
} |
| 2039 |
|
| 2040 |
if (ictl_ctx[1] & 0x2) { |
| 2041 |
pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); |
| 2042 |
|
| 2043 |
DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
|
| 2044 |
iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], |
| 2045 |
iep0_ctx[3], iep0_ctx[4]); |
| 2046 |
|
| 2047 |
pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
| 2048 |
|
| 2049 |
ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ |
| 2050 |
ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; |
| 2051 |
|
| 2052 |
DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
|
| 2053 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
| 2054 |
|
| 2055 |
pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
| 2056 |
} |
| 2057 |
|
| 2058 |
return CC_SUCCESS;
|
| 2059 |
} |
| 2060 |
|
| 2061 |
static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) |
| 2062 |
{
|
| 2063 |
uint32_t slot_ctx[4];
|
| 2064 |
dma_addr_t octx; |
| 2065 |
int i;
|
| 2066 |
|
| 2067 |
trace_usb_xhci_slot_reset(slotid); |
| 2068 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
| 2069 |
|
| 2070 |
octx = xhci->slots[slotid-1].ctx;
|
| 2071 |
|
| 2072 |
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
| 2073 |
|
| 2074 |
for (i = 2; i <= 31; i++) { |
| 2075 |
if (xhci->slots[slotid-1].eps[i-1]) { |
| 2076 |
xhci_disable_ep(xhci, slotid, i); |
| 2077 |
} |
| 2078 |
} |
| 2079 |
|
| 2080 |
pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 2081 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
| 2082 |
slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
|
| 2083 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
| 2084 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
| 2085 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
| 2086 |
|
| 2087 |
return CC_SUCCESS;
|
| 2088 |
} |
| 2089 |
|
| 2090 |
static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) |
| 2091 |
{
|
| 2092 |
unsigned int slotid; |
| 2093 |
slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; |
| 2094 |
if (slotid < 1 || slotid > MAXSLOTS) { |
| 2095 |
fprintf(stderr, "xhci: bad slot id %d\n", slotid);
|
| 2096 |
event->ccode = CC_TRB_ERROR; |
| 2097 |
return 0; |
| 2098 |
} else if (!xhci->slots[slotid-1].enabled) { |
| 2099 |
fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
|
| 2100 |
event->ccode = CC_SLOT_NOT_ENABLED_ERROR; |
| 2101 |
return 0; |
| 2102 |
} |
| 2103 |
return slotid;
|
| 2104 |
} |
| 2105 |
|
| 2106 |
static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
|
| 2107 |
{
|
| 2108 |
dma_addr_t ctx; |
| 2109 |
uint8_t bw_ctx[xhci->numports+1];
|
| 2110 |
|
| 2111 |
DPRINTF("xhci_get_port_bandwidth()\n");
|
| 2112 |
|
| 2113 |
ctx = xhci_mask64(pctx); |
| 2114 |
|
| 2115 |
DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); |
| 2116 |
|
| 2117 |
/* TODO: actually implement real values here */
|
| 2118 |
bw_ctx[0] = 0; |
| 2119 |
memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ |
| 2120 |
pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
|
| 2121 |
|
| 2122 |
return CC_SUCCESS;
|
| 2123 |
} |
| 2124 |
|
| 2125 |
static uint32_t rotl(uint32_t v, unsigned count) |
| 2126 |
{
|
| 2127 |
count &= 31;
|
| 2128 |
return (v << count) | (v >> (32 - count)); |
| 2129 |
} |
| 2130 |
|
| 2131 |
|
| 2132 |
static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
|
| 2133 |
{
|
| 2134 |
uint32_t val; |
| 2135 |
val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); |
| 2136 |
val += rotl(lo + 0x49434878, hi & 0x1F); |
| 2137 |
val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); |
| 2138 |
return ~val;
|
| 2139 |
} |
| 2140 |
|
| 2141 |
static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) |
| 2142 |
{
|
| 2143 |
uint32_t buf[8];
|
| 2144 |
uint32_t obuf[8];
|
| 2145 |
dma_addr_t paddr = xhci_mask64(addr); |
| 2146 |
|
| 2147 |
pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
|
| 2148 |
|
| 2149 |
memcpy(obuf, buf, sizeof(obuf));
|
| 2150 |
|
| 2151 |
if ((buf[0] & 0xff) == 2) { |
| 2152 |
obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; |
| 2153 |
obuf[0] |= (buf[2] * buf[3]) & 0xff; |
| 2154 |
obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; |
| 2155 |
obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; |
| 2156 |
obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; |
| 2157 |
obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; |
| 2158 |
obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; |
| 2159 |
obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; |
| 2160 |
obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; |
| 2161 |
} |
| 2162 |
|
| 2163 |
pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
|
| 2164 |
} |
| 2165 |
|
| 2166 |
static void xhci_process_commands(XHCIState *xhci) |
| 2167 |
{
|
| 2168 |
XHCITRB trb; |
| 2169 |
TRBType type; |
| 2170 |
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
|
| 2171 |
dma_addr_t addr; |
| 2172 |
unsigned int i, slotid = 0; |
| 2173 |
|
| 2174 |
DPRINTF("xhci_process_commands()\n");
|
| 2175 |
if (!xhci_running(xhci)) {
|
| 2176 |
DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
|
| 2177 |
return;
|
| 2178 |
} |
| 2179 |
|
| 2180 |
xhci->crcr_low |= CRCR_CRR; |
| 2181 |
|
| 2182 |
while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
|
| 2183 |
event.ptr = addr; |
| 2184 |
switch (type) {
|
| 2185 |
case CR_ENABLE_SLOT:
|
| 2186 |
for (i = 0; i < MAXSLOTS; i++) { |
| 2187 |
if (!xhci->slots[i].enabled) {
|
| 2188 |
break;
|
| 2189 |
} |
| 2190 |
} |
| 2191 |
if (i >= MAXSLOTS) {
|
| 2192 |
fprintf(stderr, "xhci: no device slots available\n");
|
| 2193 |
event.ccode = CC_NO_SLOTS_ERROR; |
| 2194 |
} else {
|
| 2195 |
slotid = i+1;
|
| 2196 |
event.ccode = xhci_enable_slot(xhci, slotid); |
| 2197 |
} |
| 2198 |
break;
|
| 2199 |
case CR_DISABLE_SLOT:
|
| 2200 |
slotid = xhci_get_slot(xhci, &event, &trb); |
| 2201 |
if (slotid) {
|
| 2202 |
event.ccode = xhci_disable_slot(xhci, slotid); |
| 2203 |
} |
| 2204 |
break;
|
| 2205 |
case CR_ADDRESS_DEVICE:
|
| 2206 |
slotid = xhci_get_slot(xhci, &event, &trb); |
| 2207 |
if (slotid) {
|
| 2208 |
event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, |
| 2209 |
trb.control & TRB_CR_BSR); |
| 2210 |
} |
| 2211 |
break;
|
| 2212 |
case CR_CONFIGURE_ENDPOINT:
|
| 2213 |
slotid = xhci_get_slot(xhci, &event, &trb); |
| 2214 |
if (slotid) {
|
| 2215 |
event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, |
| 2216 |
trb.control & TRB_CR_DC); |
| 2217 |
} |
| 2218 |
break;
|
| 2219 |
case CR_EVALUATE_CONTEXT:
|
| 2220 |
slotid = xhci_get_slot(xhci, &event, &trb); |
| 2221 |
if (slotid) {
|
| 2222 |
event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); |
| 2223 |
} |
| 2224 |
break;
|
| 2225 |
case CR_STOP_ENDPOINT:
|
| 2226 |
slotid = xhci_get_slot(xhci, &event, &trb); |
| 2227 |
if (slotid) {
|
| 2228 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
| 2229 |
& TRB_CR_EPID_MASK; |
| 2230 |
event.ccode = xhci_stop_ep(xhci, slotid, epid); |
| 2231 |
} |
| 2232 |
break;
|
| 2233 |
case CR_RESET_ENDPOINT:
|
| 2234 |
slotid = xhci_get_slot(xhci, &event, &trb); |
| 2235 |
if (slotid) {
|
| 2236 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
| 2237 |
& TRB_CR_EPID_MASK; |
| 2238 |
event.ccode = xhci_reset_ep(xhci, slotid, epid); |
| 2239 |
} |
| 2240 |
break;
|
| 2241 |
case CR_SET_TR_DEQUEUE:
|
| 2242 |
slotid = xhci_get_slot(xhci, &event, &trb); |
| 2243 |
if (slotid) {
|
| 2244 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
| 2245 |
& TRB_CR_EPID_MASK; |
| 2246 |
event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, |
| 2247 |
trb.parameter); |
| 2248 |
} |
| 2249 |
break;
|
| 2250 |
case CR_RESET_DEVICE:
|
| 2251 |
slotid = xhci_get_slot(xhci, &event, &trb); |
| 2252 |
if (slotid) {
|
| 2253 |
event.ccode = xhci_reset_slot(xhci, slotid); |
| 2254 |
} |
| 2255 |
break;
|
| 2256 |
case CR_GET_PORT_BANDWIDTH:
|
| 2257 |
event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); |
| 2258 |
break;
|
| 2259 |
case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
|
| 2260 |
xhci_via_challenge(xhci, trb.parameter); |
| 2261 |
break;
|
| 2262 |
case CR_VENDOR_NEC_FIRMWARE_REVISION:
|
| 2263 |
event.type = 48; /* NEC reply */ |
| 2264 |
event.length = 0x3025;
|
| 2265 |
break;
|
| 2266 |
case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
|
| 2267 |
{
|
| 2268 |
uint32_t chi = trb.parameter >> 32;
|
| 2269 |
uint32_t clo = trb.parameter; |
| 2270 |
uint32_t val = xhci_nec_challenge(chi, clo); |
| 2271 |
event.length = val & 0xFFFF;
|
| 2272 |
event.epid = val >> 16;
|
| 2273 |
slotid = val >> 24;
|
| 2274 |
event.type = 48; /* NEC reply */ |
| 2275 |
} |
| 2276 |
break;
|
| 2277 |
default:
|
| 2278 |
fprintf(stderr, "xhci: unimplemented command %d\n", type);
|
| 2279 |
event.ccode = CC_TRB_ERROR; |
| 2280 |
break;
|
| 2281 |
} |
| 2282 |
event.slotid = slotid; |
| 2283 |
xhci_event(xhci, &event, 0);
|
| 2284 |
} |
| 2285 |
} |
| 2286 |
|
| 2287 |
static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) |
| 2288 |
{
|
| 2289 |
port->portsc = PORTSC_PP; |
| 2290 |
if (port->uport->dev && port->uport->dev->attached && !is_detach &&
|
| 2291 |
(1 << port->uport->dev->speed) & port->speedmask) {
|
| 2292 |
port->portsc |= PORTSC_CCS; |
| 2293 |
switch (port->uport->dev->speed) {
|
| 2294 |
case USB_SPEED_LOW:
|
| 2295 |
port->portsc |= PORTSC_SPEED_LOW; |
| 2296 |
break;
|
| 2297 |
case USB_SPEED_FULL:
|
| 2298 |
port->portsc |= PORTSC_SPEED_FULL; |
| 2299 |
break;
|
| 2300 |
case USB_SPEED_HIGH:
|
| 2301 |
port->portsc |= PORTSC_SPEED_HIGH; |
| 2302 |
break;
|
| 2303 |
case USB_SPEED_SUPER:
|
| 2304 |
port->portsc |= PORTSC_SPEED_SUPER; |
| 2305 |
break;
|
| 2306 |
} |
| 2307 |
} |
| 2308 |
|
| 2309 |
if (xhci_running(xhci)) {
|
| 2310 |
port->portsc |= PORTSC_CSC; |
| 2311 |
XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
|
| 2312 |
port->portnr << 24};
|
| 2313 |
xhci_event(xhci, &ev, 0);
|
| 2314 |
DPRINTF("xhci: port change event for port %d\n", port->portnr);
|
| 2315 |
} |
| 2316 |
} |
| 2317 |
|
| 2318 |
static void xhci_reset(DeviceState *dev) |
| 2319 |
{
|
| 2320 |
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); |
| 2321 |
int i;
|
| 2322 |
|
| 2323 |
trace_usb_xhci_reset(); |
| 2324 |
if (!(xhci->usbsts & USBSTS_HCH)) {
|
| 2325 |
fprintf(stderr, "xhci: reset while running!\n");
|
| 2326 |
} |
| 2327 |
|
| 2328 |
xhci->usbcmd = 0;
|
| 2329 |
xhci->usbsts = USBSTS_HCH; |
| 2330 |
xhci->dnctrl = 0;
|
| 2331 |
xhci->crcr_low = 0;
|
| 2332 |
xhci->crcr_high = 0;
|
| 2333 |
xhci->dcbaap_low = 0;
|
| 2334 |
xhci->dcbaap_high = 0;
|
| 2335 |
xhci->config = 0;
|
| 2336 |
xhci->devaddr = 2;
|
| 2337 |
|
| 2338 |
for (i = 0; i < MAXSLOTS; i++) { |
| 2339 |
xhci_disable_slot(xhci, i+1);
|
| 2340 |
} |
| 2341 |
|
| 2342 |
for (i = 0; i < xhci->numports; i++) { |
| 2343 |
xhci_update_port(xhci, xhci->ports + i, 0);
|
| 2344 |
} |
| 2345 |
|
| 2346 |
for (i = 0; i < MAXINTRS; i++) { |
| 2347 |
xhci->intr[i].iman = 0;
|
| 2348 |
xhci->intr[i].imod = 0;
|
| 2349 |
xhci->intr[i].erstsz = 0;
|
| 2350 |
xhci->intr[i].erstba_low = 0;
|
| 2351 |
xhci->intr[i].erstba_high = 0;
|
| 2352 |
xhci->intr[i].erdp_low = 0;
|
| 2353 |
xhci->intr[i].erdp_high = 0;
|
| 2354 |
xhci->intr[i].msix_used = 0;
|
| 2355 |
|
| 2356 |
xhci->intr[i].er_ep_idx = 0;
|
| 2357 |
xhci->intr[i].er_pcs = 1;
|
| 2358 |
xhci->intr[i].er_full = 0;
|
| 2359 |
xhci->intr[i].ev_buffer_put = 0;
|
| 2360 |
xhci->intr[i].ev_buffer_get = 0;
|
| 2361 |
} |
| 2362 |
|
| 2363 |
xhci->mfindex_start = qemu_get_clock_ns(vm_clock); |
| 2364 |
xhci_mfwrap_update(xhci); |
| 2365 |
} |
| 2366 |
|
| 2367 |
static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size) |
| 2368 |
{
|
| 2369 |
XHCIState *xhci = ptr; |
| 2370 |
uint32_t ret; |
| 2371 |
|
| 2372 |
switch (reg) {
|
| 2373 |
case 0x00: /* HCIVERSION, CAPLENGTH */ |
| 2374 |
ret = 0x01000000 | LEN_CAP;
|
| 2375 |
break;
|
| 2376 |
case 0x04: /* HCSPARAMS 1 */ |
| 2377 |
ret = ((xhci->numports_2+xhci->numports_3)<<24)
|
| 2378 |
| (MAXINTRS<<8) | MAXSLOTS;
|
| 2379 |
break;
|
| 2380 |
case 0x08: /* HCSPARAMS 2 */ |
| 2381 |
ret = 0x0000000f;
|
| 2382 |
break;
|
| 2383 |
case 0x0c: /* HCSPARAMS 3 */ |
| 2384 |
ret = 0x00000000;
|
| 2385 |
break;
|
| 2386 |
case 0x10: /* HCCPARAMS */ |
| 2387 |
if (sizeof(dma_addr_t) == 4) { |
| 2388 |
ret = 0x00081000;
|
| 2389 |
} else {
|
| 2390 |
ret = 0x00081001;
|
| 2391 |
} |
| 2392 |
break;
|
| 2393 |
case 0x14: /* DBOFF */ |
| 2394 |
ret = OFF_DOORBELL; |
| 2395 |
break;
|
| 2396 |
case 0x18: /* RTSOFF */ |
| 2397 |
ret = OFF_RUNTIME; |
| 2398 |
break;
|
| 2399 |
|
| 2400 |
/* extended capabilities */
|
| 2401 |
case 0x20: /* Supported Protocol:00 */ |
| 2402 |
ret = 0x02000402; /* USB 2.0 */ |
| 2403 |
break;
|
| 2404 |
case 0x24: /* Supported Protocol:04 */ |
| 2405 |
ret = 0x20425455; /* "USB " */ |
| 2406 |
break;
|
| 2407 |
case 0x28: /* Supported Protocol:08 */ |
| 2408 |
ret = 0x00000001 | (xhci->numports_2<<8); |
| 2409 |
break;
|
| 2410 |
case 0x2c: /* Supported Protocol:0c */ |
| 2411 |
ret = 0x00000000; /* reserved */ |
| 2412 |
break;
|
| 2413 |
case 0x30: /* Supported Protocol:00 */ |
| 2414 |
ret = 0x03000002; /* USB 3.0 */ |
| 2415 |
break;
|
| 2416 |
case 0x34: /* Supported Protocol:04 */ |
| 2417 |
ret = 0x20425455; /* "USB " */ |
| 2418 |
break;
|
| 2419 |
case 0x38: /* Supported Protocol:08 */ |
| 2420 |
ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); |
| 2421 |
break;
|
| 2422 |
case 0x3c: /* Supported Protocol:0c */ |
| 2423 |
ret = 0x00000000; /* reserved */ |
| 2424 |
break;
|
| 2425 |
default:
|
| 2426 |
fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg); |
| 2427 |
ret = 0;
|
| 2428 |
} |
| 2429 |
|
| 2430 |
trace_usb_xhci_cap_read(reg, ret); |
| 2431 |
return ret;
|
| 2432 |
} |
| 2433 |
|
| 2434 |
static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size) |
| 2435 |
{
|
| 2436 |
XHCIPort *port = ptr; |
| 2437 |
uint32_t ret; |
| 2438 |
|
| 2439 |
switch (reg) {
|
| 2440 |
case 0x00: /* PORTSC */ |
| 2441 |
ret = port->portsc; |
| 2442 |
break;
|
| 2443 |
case 0x04: /* PORTPMSC */ |
| 2444 |
case 0x08: /* PORTLI */ |
| 2445 |
ret = 0;
|
| 2446 |
break;
|
| 2447 |
case 0x0c: /* reserved */ |
| 2448 |
default:
|
| 2449 |
fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
|
| 2450 |
port->portnr, (uint32_t)reg); |
| 2451 |
ret = 0;
|
| 2452 |
} |
| 2453 |
|
| 2454 |
trace_usb_xhci_port_read(port->portnr, reg, ret); |
| 2455 |
return ret;
|
| 2456 |
} |
| 2457 |
|
| 2458 |
static void xhci_port_write(void *ptr, target_phys_addr_t reg, |
| 2459 |
uint64_t val, unsigned size)
|
| 2460 |
{
|
| 2461 |
XHCIPort *port = ptr; |
| 2462 |
uint32_t portsc; |
| 2463 |
|
| 2464 |
trace_usb_xhci_port_write(port->portnr, reg, val); |
| 2465 |
|
| 2466 |
switch (reg) {
|
| 2467 |
case 0x00: /* PORTSC */ |
| 2468 |
portsc = port->portsc; |
| 2469 |
/* write-1-to-clear bits*/
|
| 2470 |
portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| |
| 2471 |
PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); |
| 2472 |
if (val & PORTSC_LWS) {
|
| 2473 |
/* overwrite PLS only when LWS=1 */
|
| 2474 |
portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); |
| 2475 |
portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); |
| 2476 |
} |
| 2477 |
/* read/write bits */
|
| 2478 |
portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); |
| 2479 |
portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); |
| 2480 |
/* write-1-to-start bits */
|
| 2481 |
if (val & PORTSC_PR) {
|
| 2482 |
DPRINTF("xhci: port %d reset\n", port);
|
| 2483 |
usb_device_reset(port->uport->dev); |
| 2484 |
portsc |= PORTSC_PRC | PORTSC_PED; |
| 2485 |
} |
| 2486 |
port->portsc = portsc; |
| 2487 |
break;
|
| 2488 |
case 0x04: /* PORTPMSC */ |
| 2489 |
case 0x08: /* PORTLI */ |
| 2490 |
default:
|
| 2491 |
fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
|
| 2492 |
port->portnr, (uint32_t)reg); |
| 2493 |
} |
| 2494 |
} |
| 2495 |
|
| 2496 |
static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size) |
| 2497 |
{
|
| 2498 |
XHCIState *xhci = ptr; |
| 2499 |
uint32_t ret; |
| 2500 |
|
| 2501 |
switch (reg) {
|
| 2502 |
case 0x00: /* USBCMD */ |
| 2503 |
ret = xhci->usbcmd; |
| 2504 |
break;
|
| 2505 |
case 0x04: /* USBSTS */ |
| 2506 |
ret = xhci->usbsts; |
| 2507 |
break;
|
| 2508 |
case 0x08: /* PAGESIZE */ |
| 2509 |
ret = 1; /* 4KiB */ |
| 2510 |
break;
|
| 2511 |
case 0x14: /* DNCTRL */ |
| 2512 |
ret = xhci->dnctrl; |
| 2513 |
break;
|
| 2514 |
case 0x18: /* CRCR low */ |
| 2515 |
ret = xhci->crcr_low & ~0xe;
|
| 2516 |
break;
|
| 2517 |
case 0x1c: /* CRCR high */ |
| 2518 |
ret = xhci->crcr_high; |
| 2519 |
break;
|
| 2520 |
case 0x30: /* DCBAAP low */ |
| 2521 |
ret = xhci->dcbaap_low; |
| 2522 |
break;
|
| 2523 |
case 0x34: /* DCBAAP high */ |
| 2524 |
ret = xhci->dcbaap_high; |
| 2525 |
break;
|
| 2526 |
case 0x38: /* CONFIG */ |
| 2527 |
ret = xhci->config; |
| 2528 |
break;
|
| 2529 |
default:
|
| 2530 |
fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg); |
| 2531 |
ret = 0;
|
| 2532 |
} |
| 2533 |
|
| 2534 |
trace_usb_xhci_oper_read(reg, ret); |
| 2535 |
return ret;
|
| 2536 |
} |
| 2537 |
|
| 2538 |
static void xhci_oper_write(void *ptr, target_phys_addr_t reg, |
| 2539 |
uint64_t val, unsigned size)
|
| 2540 |
{
|
| 2541 |
XHCIState *xhci = ptr; |
| 2542 |
|
| 2543 |
trace_usb_xhci_oper_write(reg, val); |
| 2544 |
|
| 2545 |
switch (reg) {
|
| 2546 |
case 0x00: /* USBCMD */ |
| 2547 |
if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
|
| 2548 |
xhci_run(xhci); |
| 2549 |
} else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { |
| 2550 |
xhci_stop(xhci); |
| 2551 |
} |
| 2552 |
xhci->usbcmd = val & 0xc0f;
|
| 2553 |
xhci_mfwrap_update(xhci); |
| 2554 |
if (val & USBCMD_HCRST) {
|
| 2555 |
xhci_reset(&xhci->pci_dev.qdev); |
| 2556 |
} |
| 2557 |
xhci_intx_update(xhci); |
| 2558 |
break;
|
| 2559 |
|
| 2560 |
case 0x04: /* USBSTS */ |
| 2561 |
/* these bits are write-1-to-clear */
|
| 2562 |
xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); |
| 2563 |
xhci_intx_update(xhci); |
| 2564 |
break;
|
| 2565 |
|
| 2566 |
case 0x14: /* DNCTRL */ |
| 2567 |
xhci->dnctrl = val & 0xffff;
|
| 2568 |
break;
|
| 2569 |
case 0x18: /* CRCR low */ |
| 2570 |
xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
|
| 2571 |
break;
|
| 2572 |
case 0x1c: /* CRCR high */ |
| 2573 |
xhci->crcr_high = val; |
| 2574 |
if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
|
| 2575 |
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
|
| 2576 |
xhci->crcr_low &= ~CRCR_CRR; |
| 2577 |
xhci_event(xhci, &event, 0);
|
| 2578 |
DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
|
| 2579 |
} else {
|
| 2580 |
dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
|
| 2581 |
xhci_ring_init(xhci, &xhci->cmd_ring, base); |
| 2582 |
} |
| 2583 |
xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); |
| 2584 |
break;
|
| 2585 |
case 0x30: /* DCBAAP low */ |
| 2586 |
xhci->dcbaap_low = val & 0xffffffc0;
|
| 2587 |
break;
|
| 2588 |
case 0x34: /* DCBAAP high */ |
| 2589 |
xhci->dcbaap_high = val; |
| 2590 |
break;
|
| 2591 |
case 0x38: /* CONFIG */ |
| 2592 |
xhci->config = val & 0xff;
|
| 2593 |
break;
|
| 2594 |
default:
|
| 2595 |
fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); |
| 2596 |
} |
| 2597 |
} |
| 2598 |
|
| 2599 |
static uint64_t xhci_runtime_read(void *ptr, target_phys_addr_t reg, |
| 2600 |
unsigned size)
|
| 2601 |
{
|
| 2602 |
XHCIState *xhci = ptr; |
| 2603 |
uint32_t ret = 0;
|
| 2604 |
|
| 2605 |
if (reg < 0x20) { |
| 2606 |
switch (reg) {
|
| 2607 |
case 0x00: /* MFINDEX */ |
| 2608 |
ret = xhci_mfindex_get(xhci) & 0x3fff;
|
| 2609 |
break;
|
| 2610 |
default:
|
| 2611 |
fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n",
|
| 2612 |
(int)reg);
|
| 2613 |
break;
|
| 2614 |
} |
| 2615 |
} else {
|
| 2616 |
int v = (reg - 0x20) / 0x20; |
| 2617 |
XHCIInterrupter *intr = &xhci->intr[v]; |
| 2618 |
switch (reg & 0x1f) { |
| 2619 |
case 0x00: /* IMAN */ |
| 2620 |
ret = intr->iman; |
| 2621 |
break;
|
| 2622 |
case 0x04: /* IMOD */ |
| 2623 |
ret = intr->imod; |
| 2624 |
break;
|
| 2625 |
case 0x08: /* ERSTSZ */ |
| 2626 |
ret = intr->erstsz; |
| 2627 |
break;
|
| 2628 |
case 0x10: /* ERSTBA low */ |
| 2629 |
ret = intr->erstba_low; |
| 2630 |
break;
|
| 2631 |
case 0x14: /* ERSTBA high */ |
| 2632 |
ret = intr->erstba_high; |
| 2633 |
break;
|
| 2634 |
case 0x18: /* ERDP low */ |
| 2635 |
ret = intr->erdp_low; |
| 2636 |
break;
|
| 2637 |
case 0x1c: /* ERDP high */ |
| 2638 |
ret = intr->erdp_high; |
| 2639 |
break;
|
| 2640 |
} |
| 2641 |
} |
| 2642 |
|
| 2643 |
trace_usb_xhci_runtime_read(reg, ret); |
| 2644 |
return ret;
|
| 2645 |
} |
| 2646 |
|
| 2647 |
static void xhci_runtime_write(void *ptr, target_phys_addr_t reg, |
| 2648 |
uint64_t val, unsigned size)
|
| 2649 |
{
|
| 2650 |
XHCIState *xhci = ptr; |
| 2651 |
int v = (reg - 0x20) / 0x20; |
| 2652 |
XHCIInterrupter *intr = &xhci->intr[v]; |
| 2653 |
trace_usb_xhci_runtime_write(reg, val); |
| 2654 |
|
| 2655 |
if (reg < 0x20) { |
| 2656 |
fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); |
| 2657 |
return;
|
| 2658 |
} |
| 2659 |
|
| 2660 |
switch (reg & 0x1f) { |
| 2661 |
case 0x00: /* IMAN */ |
| 2662 |
if (val & IMAN_IP) {
|
| 2663 |
intr->iman &= ~IMAN_IP; |
| 2664 |
} |
| 2665 |
intr->iman &= ~IMAN_IE; |
| 2666 |
intr->iman |= val & IMAN_IE; |
| 2667 |
if (v == 0) { |
| 2668 |
xhci_intx_update(xhci); |
| 2669 |
} |
| 2670 |
xhci_msix_update(xhci, v); |
| 2671 |
break;
|
| 2672 |
case 0x04: /* IMOD */ |
| 2673 |
intr->imod = val; |
| 2674 |
break;
|
| 2675 |
case 0x08: /* ERSTSZ */ |
| 2676 |
intr->erstsz = val & 0xffff;
|
| 2677 |
break;
|
| 2678 |
case 0x10: /* ERSTBA low */ |
| 2679 |
/* XXX NEC driver bug: it doesn't align this to 64 bytes
|
| 2680 |
intr->erstba_low = val & 0xffffffc0; */
|
| 2681 |
intr->erstba_low = val & 0xfffffff0;
|
| 2682 |
break;
|
| 2683 |
case 0x14: /* ERSTBA high */ |
| 2684 |
intr->erstba_high = val; |
| 2685 |
xhci_er_reset(xhci, v); |
| 2686 |
break;
|
| 2687 |
case 0x18: /* ERDP low */ |
| 2688 |
if (val & ERDP_EHB) {
|
| 2689 |
intr->erdp_low &= ~ERDP_EHB; |
| 2690 |
} |
| 2691 |
intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); |
| 2692 |
break;
|
| 2693 |
case 0x1c: /* ERDP high */ |
| 2694 |
intr->erdp_high = val; |
| 2695 |
xhci_events_update(xhci, v); |
| 2696 |
break;
|
| 2697 |
default:
|
| 2698 |
fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n",
|
| 2699 |
(int)reg);
|
| 2700 |
} |
| 2701 |
} |
| 2702 |
|
| 2703 |
static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg, |
| 2704 |
unsigned size)
|
| 2705 |
{
|
| 2706 |
/* doorbells always read as 0 */
|
| 2707 |
trace_usb_xhci_doorbell_read(reg, 0);
|
| 2708 |
return 0; |
| 2709 |
} |
| 2710 |
|
| 2711 |
static void xhci_doorbell_write(void *ptr, target_phys_addr_t reg, |
| 2712 |
uint64_t val, unsigned size)
|
| 2713 |
{
|
| 2714 |
XHCIState *xhci = ptr; |
| 2715 |
|
| 2716 |
trace_usb_xhci_doorbell_write(reg, val); |
| 2717 |
|
| 2718 |
if (!xhci_running(xhci)) {
|
| 2719 |
fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
|
| 2720 |
return;
|
| 2721 |
} |
| 2722 |
|
| 2723 |
reg >>= 2;
|
| 2724 |
|
| 2725 |
if (reg == 0) { |
| 2726 |
if (val == 0) { |
| 2727 |
xhci_process_commands(xhci); |
| 2728 |
} else {
|
| 2729 |
fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n",
|
| 2730 |
(uint32_t)val); |
| 2731 |
} |
| 2732 |
} else {
|
| 2733 |
if (reg > MAXSLOTS) {
|
| 2734 |
fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); |
| 2735 |
} else if (val > 31) { |
| 2736 |
fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n",
|
| 2737 |
(int)reg, (uint32_t)val);
|
| 2738 |
} else {
|
| 2739 |
xhci_kick_ep(xhci, reg, val); |
| 2740 |
} |
| 2741 |
} |
| 2742 |
} |
| 2743 |
|
| 2744 |
static const MemoryRegionOps xhci_cap_ops = { |
| 2745 |
.read = xhci_cap_read, |
| 2746 |
.valid.min_access_size = 1,
|
| 2747 |
.valid.max_access_size = 4,
|
| 2748 |
.impl.min_access_size = 4,
|
| 2749 |
.impl.max_access_size = 4,
|
| 2750 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2751 |
}; |
| 2752 |
|
| 2753 |
static const MemoryRegionOps xhci_oper_ops = { |
| 2754 |
.read = xhci_oper_read, |
| 2755 |
.write = xhci_oper_write, |
| 2756 |
.valid.min_access_size = 4,
|
| 2757 |
.valid.max_access_size = 4,
|
| 2758 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2759 |
}; |
| 2760 |
|
| 2761 |
static const MemoryRegionOps xhci_port_ops = { |
| 2762 |
.read = xhci_port_read, |
| 2763 |
.write = xhci_port_write, |
| 2764 |
.valid.min_access_size = 4,
|
| 2765 |
.valid.max_access_size = 4,
|
| 2766 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2767 |
}; |
| 2768 |
|
| 2769 |
static const MemoryRegionOps xhci_runtime_ops = { |
| 2770 |
.read = xhci_runtime_read, |
| 2771 |
.write = xhci_runtime_write, |
| 2772 |
.valid.min_access_size = 4,
|
| 2773 |
.valid.max_access_size = 4,
|
| 2774 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2775 |
}; |
| 2776 |
|
| 2777 |
static const MemoryRegionOps xhci_doorbell_ops = { |
| 2778 |
.read = xhci_doorbell_read, |
| 2779 |
.write = xhci_doorbell_write, |
| 2780 |
.valid.min_access_size = 4,
|
| 2781 |
.valid.max_access_size = 4,
|
| 2782 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2783 |
}; |
| 2784 |
|
| 2785 |
static void xhci_attach(USBPort *usbport) |
| 2786 |
{
|
| 2787 |
XHCIState *xhci = usbport->opaque; |
| 2788 |
XHCIPort *port = xhci_lookup_port(xhci, usbport); |
| 2789 |
|
| 2790 |
xhci_update_port(xhci, port, 0);
|
| 2791 |
} |
| 2792 |
|
| 2793 |
static void xhci_detach(USBPort *usbport) |
| 2794 |
{
|
| 2795 |
XHCIState *xhci = usbport->opaque; |
| 2796 |
XHCIPort *port = xhci_lookup_port(xhci, usbport); |
| 2797 |
|
| 2798 |
xhci_update_port(xhci, port, 1);
|
| 2799 |
} |
| 2800 |
|
| 2801 |
static void xhci_wakeup(USBPort *usbport) |
| 2802 |
{
|
| 2803 |
XHCIState *xhci = usbport->opaque; |
| 2804 |
XHCIPort *port = xhci_lookup_port(xhci, usbport); |
| 2805 |
XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
|
| 2806 |
port->portnr << 24};
|
| 2807 |
uint32_t pls; |
| 2808 |
|
| 2809 |
pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; |
| 2810 |
if (pls != 3) { |
| 2811 |
return;
|
| 2812 |
} |
| 2813 |
port->portsc |= 0xf << PORTSC_PLS_SHIFT;
|
| 2814 |
if (port->portsc & PORTSC_PLC) {
|
| 2815 |
return;
|
| 2816 |
} |
| 2817 |
port->portsc |= PORTSC_PLC; |
| 2818 |
xhci_event(xhci, &ev, 0);
|
| 2819 |
} |
| 2820 |
|
| 2821 |
static void xhci_complete(USBPort *port, USBPacket *packet) |
| 2822 |
{
|
| 2823 |
XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); |
| 2824 |
|
| 2825 |
xhci_complete_packet(xfer, packet->result); |
| 2826 |
xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); |
| 2827 |
} |
| 2828 |
|
| 2829 |
static void xhci_child_detach(USBPort *uport, USBDevice *child) |
| 2830 |
{
|
| 2831 |
USBBus *bus = usb_bus_from_device(child); |
| 2832 |
XHCIState *xhci = container_of(bus, XHCIState, bus); |
| 2833 |
int i;
|
| 2834 |
|
| 2835 |
for (i = 0; i < MAXSLOTS; i++) { |
| 2836 |
if (xhci->slots[i].uport == uport) {
|
| 2837 |
xhci->slots[i].uport = NULL;
|
| 2838 |
} |
| 2839 |
} |
| 2840 |
} |
| 2841 |
|
| 2842 |
static USBPortOps xhci_uport_ops = {
|
| 2843 |
.attach = xhci_attach, |
| 2844 |
.detach = xhci_detach, |
| 2845 |
.wakeup = xhci_wakeup, |
| 2846 |
.complete = xhci_complete, |
| 2847 |
.child_detach = xhci_child_detach, |
| 2848 |
}; |
| 2849 |
|
| 2850 |
static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) |
| 2851 |
{
|
| 2852 |
XHCISlot *slot; |
| 2853 |
int slotid;
|
| 2854 |
|
| 2855 |
for (slotid = 1; slotid <= MAXSLOTS; slotid++) { |
| 2856 |
slot = &xhci->slots[slotid-1];
|
| 2857 |
if (slot->devaddr == dev->addr) {
|
| 2858 |
return slotid;
|
| 2859 |
} |
| 2860 |
} |
| 2861 |
return 0; |
| 2862 |
} |
| 2863 |
|
| 2864 |
static int xhci_find_epid(USBEndpoint *ep) |
| 2865 |
{
|
| 2866 |
if (ep->nr == 0) { |
| 2867 |
return 1; |
| 2868 |
} |
| 2869 |
if (ep->pid == USB_TOKEN_IN) {
|
| 2870 |
return ep->nr * 2 + 1; |
| 2871 |
} else {
|
| 2872 |
return ep->nr * 2; |
| 2873 |
} |
| 2874 |
} |
| 2875 |
|
| 2876 |
static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) |
| 2877 |
{
|
| 2878 |
XHCIState *xhci = container_of(bus, XHCIState, bus); |
| 2879 |
int slotid;
|
| 2880 |
|
| 2881 |
DPRINTF("%s\n", __func__);
|
| 2882 |
slotid = xhci_find_slotid(xhci, ep->dev); |
| 2883 |
if (slotid == 0 || !xhci->slots[slotid-1].enabled) { |
| 2884 |
DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
|
| 2885 |
return;
|
| 2886 |
} |
| 2887 |
xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); |
| 2888 |
} |
| 2889 |
|
| 2890 |
static USBBusOps xhci_bus_ops = {
|
| 2891 |
.wakeup_endpoint = xhci_wakeup_endpoint, |
| 2892 |
}; |
| 2893 |
|
| 2894 |
static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) |
| 2895 |
{
|
| 2896 |
XHCIPort *port; |
| 2897 |
int i, usbports, speedmask;
|
| 2898 |
|
| 2899 |
xhci->usbsts = USBSTS_HCH; |
| 2900 |
|
| 2901 |
if (xhci->numports_2 > MAXPORTS_2) {
|
| 2902 |
xhci->numports_2 = MAXPORTS_2; |
| 2903 |
} |
| 2904 |
if (xhci->numports_3 > MAXPORTS_3) {
|
| 2905 |
xhci->numports_3 = MAXPORTS_3; |
| 2906 |
} |
| 2907 |
usbports = MAX(xhci->numports_2, xhci->numports_3); |
| 2908 |
xhci->numports = xhci->numports_2 + xhci->numports_3; |
| 2909 |
|
| 2910 |
usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); |
| 2911 |
|
| 2912 |
for (i = 0; i < usbports; i++) { |
| 2913 |
speedmask = 0;
|
| 2914 |
if (i < xhci->numports_2) {
|
| 2915 |
port = &xhci->ports[i]; |
| 2916 |
port->portnr = i + 1;
|
| 2917 |
port->uport = &xhci->uports[i]; |
| 2918 |
port->speedmask = |
| 2919 |
USB_SPEED_MASK_LOW | |
| 2920 |
USB_SPEED_MASK_FULL | |
| 2921 |
USB_SPEED_MASK_HIGH; |
| 2922 |
snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); |
| 2923 |
speedmask |= port->speedmask; |
| 2924 |
} |
| 2925 |
if (i < xhci->numports_3) {
|
| 2926 |
port = &xhci->ports[i + xhci->numports_2]; |
| 2927 |
port->portnr = i + 1 + xhci->numports_2;
|
| 2928 |
port->uport = &xhci->uports[i]; |
| 2929 |
port->speedmask = USB_SPEED_MASK_SUPER; |
| 2930 |
snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); |
| 2931 |
speedmask |= port->speedmask; |
| 2932 |
} |
| 2933 |
usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, |
| 2934 |
&xhci_uport_ops, speedmask); |
| 2935 |
} |
| 2936 |
} |
| 2937 |
|
| 2938 |
static int usb_xhci_initfn(struct PCIDevice *dev) |
| 2939 |
{
|
| 2940 |
int i, ret;
|
| 2941 |
|
| 2942 |
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); |
| 2943 |
|
| 2944 |
xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ |
| 2945 |
xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ |
| 2946 |
xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
|
| 2947 |
xhci->pci_dev.config[0x60] = 0x30; /* release number */ |
| 2948 |
|
| 2949 |
usb_xhci_init(xhci, &dev->qdev); |
| 2950 |
|
| 2951 |
xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); |
| 2952 |
|
| 2953 |
xhci->irq = xhci->pci_dev.irq[0];
|
| 2954 |
|
| 2955 |
memory_region_init(&xhci->mem, "xhci", LEN_REGS);
|
| 2956 |
memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, |
| 2957 |
"capabilities", LEN_CAP);
|
| 2958 |
memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, |
| 2959 |
"operational", 0x400); |
| 2960 |
memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, |
| 2961 |
"runtime", LEN_RUNTIME);
|
| 2962 |
memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, |
| 2963 |
"doorbell", LEN_DOORBELL);
|
| 2964 |
|
| 2965 |
memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
|
| 2966 |
memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); |
| 2967 |
memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); |
| 2968 |
memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); |
| 2969 |
|
| 2970 |
for (i = 0; i < xhci->numports; i++) { |
| 2971 |
XHCIPort *port = &xhci->ports[i]; |
| 2972 |
uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; |
| 2973 |
port->xhci = xhci; |
| 2974 |
memory_region_init_io(&port->mem, &xhci_port_ops, port, |
| 2975 |
port->name, 0x10);
|
| 2976 |
memory_region_add_subregion(&xhci->mem, offset, &port->mem); |
| 2977 |
} |
| 2978 |
|
| 2979 |
pci_register_bar(&xhci->pci_dev, 0,
|
| 2980 |
PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, |
| 2981 |
&xhci->mem); |
| 2982 |
|
| 2983 |
ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); |
| 2984 |
assert(ret >= 0);
|
| 2985 |
|
| 2986 |
if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { |
| 2987 |
msi_init(&xhci->pci_dev, 0x70, MAXINTRS, true, false); |
| 2988 |
} |
| 2989 |
if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { |
| 2990 |
msix_init(&xhci->pci_dev, MAXINTRS, |
| 2991 |
&xhci->mem, 0, OFF_MSIX_TABLE,
|
| 2992 |
&xhci->mem, 0, OFF_MSIX_PBA,
|
| 2993 |
0x90);
|
| 2994 |
} |
| 2995 |
|
| 2996 |
return 0; |
| 2997 |
} |
| 2998 |
|
| 2999 |
static const VMStateDescription vmstate_xhci = { |
| 3000 |
.name = "xhci",
|
| 3001 |
.unmigratable = 1,
|
| 3002 |
}; |
| 3003 |
|
| 3004 |
static Property xhci_properties[] = {
|
| 3005 |
DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), |
| 3006 |
DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), |
| 3007 |
DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), |
| 3008 |
DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), |
| 3009 |
DEFINE_PROP_END_OF_LIST(), |
| 3010 |
}; |
| 3011 |
|
| 3012 |
static void xhci_class_init(ObjectClass *klass, void *data) |
| 3013 |
{
|
| 3014 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 3015 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 3016 |
|
| 3017 |
dc->vmsd = &vmstate_xhci; |
| 3018 |
dc->props = xhci_properties; |
| 3019 |
dc->reset = xhci_reset; |
| 3020 |
k->init = usb_xhci_initfn; |
| 3021 |
k->vendor_id = PCI_VENDOR_ID_NEC; |
| 3022 |
k->device_id = PCI_DEVICE_ID_NEC_UPD720200; |
| 3023 |
k->class_id = PCI_CLASS_SERIAL_USB; |
| 3024 |
k->revision = 0x03;
|
| 3025 |
k->is_express = 1;
|
| 3026 |
} |
| 3027 |
|
| 3028 |
static TypeInfo xhci_info = {
|
| 3029 |
.name = "nec-usb-xhci",
|
| 3030 |
.parent = TYPE_PCI_DEVICE, |
| 3031 |
.instance_size = sizeof(XHCIState),
|
| 3032 |
.class_init = xhci_class_init, |
| 3033 |
}; |
| 3034 |
|
| 3035 |
static void xhci_register_types(void) |
| 3036 |
{
|
| 3037 |
type_register_static(&xhci_info); |
| 3038 |
} |
| 3039 |
|
| 3040 |
type_init(xhci_register_types) |