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/*
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* QEMU ESP emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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/* debug ESP card */
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//#define DEBUG_ESP
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#ifdef DEBUG_ESP
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#define DPRINTF(fmt, args...) \
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do { printf("ESP: " fmt , ##args); } while (0) |
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#define pic_set_irq(irq, level) \
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do { printf("ESP: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0) |
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define ESPDMA_REGS 4 |
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#define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1) |
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#define ESP_MAXREG 0x3f |
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#define TI_BUFSZ 32 |
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#define DMA_VER 0xa0000000 |
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#define DMA_INTR 1 |
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#define DMA_INTREN 0x10 |
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#define DMA_WRITE_MEM 0x100 |
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#define DMA_LOADED 0x04000000 |
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typedef struct ESPState ESPState; |
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struct ESPState {
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BlockDriverState **bd; |
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uint8_t rregs[ESP_MAXREG]; |
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uint8_t wregs[ESP_MAXREG]; |
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int irq;
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uint32_t espdmaregs[ESPDMA_REGS]; |
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uint32_t ti_size; |
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uint32_t ti_rptr, ti_wptr; |
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uint8_t ti_buf[TI_BUFSZ]; |
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int sense;
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int dma;
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SCSIDevice *scsi_dev[MAX_DISKS]; |
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SCSIDevice *current_dev; |
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uint8_t cmdbuf[TI_BUFSZ]; |
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int cmdlen;
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int do_cmd;
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uint32_t dma_left; |
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uint8_t async_buf[TARGET_PAGE_SIZE]; |
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uint32_t async_ptr; |
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uint32_t async_len; |
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}; |
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#define STAT_DO 0x00 |
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#define STAT_DI 0x01 |
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#define STAT_CD 0x02 |
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#define STAT_ST 0x03 |
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#define STAT_MI 0x06 |
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#define STAT_MO 0x07 |
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#define STAT_TC 0x10 |
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#define STAT_PE 0x20 |
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#define STAT_GE 0x40 |
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#define STAT_IN 0x80 |
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#define INTR_FC 0x08 |
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#define INTR_BS 0x10 |
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#define INTR_DC 0x20 |
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#define INTR_RST 0x80 |
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#define SEQ_0 0x0 |
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#define SEQ_CD 0x4 |
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static int get_cmd(ESPState *s, uint8_t *buf) |
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{ |
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uint32_t dmaptr, dmalen; |
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int target;
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dmalen = s->wregs[0] | (s->wregs[1] << 8); |
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target = s->wregs[4] & 7; |
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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if (s->dma) {
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dmaptr = iommu_translate(s->espdmaregs[1]);
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DPRINTF("DMA Direction: %c, addr 0x%8.8x\n",
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s->espdmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', dmaptr); |
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cpu_physical_memory_read(dmaptr, buf, dmalen); |
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} else {
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buf[0] = 0; |
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memcpy(&buf[1], s->ti_buf, dmalen);
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dmalen++; |
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} |
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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if (target >= 4 || !s->scsi_dev[target]) { |
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// No such drive
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s->rregs[4] = STAT_IN;
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s->rregs[5] = INTR_DC;
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s->rregs[6] = SEQ_0;
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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return 0; |
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} |
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s->current_dev = s->scsi_dev[target]; |
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return dmalen;
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} |
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static void do_cmd(ESPState *s, uint8_t *buf) |
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{ |
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int32_t datalen; |
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int lun;
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DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
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lun = buf[0] & 7; |
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datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun); |
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if (datalen == 0) { |
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s->ti_size = 0;
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} else {
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s->rregs[4] = STAT_IN | STAT_TC;
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if (datalen > 0) { |
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s->rregs[4] |= STAT_DI;
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s->ti_size = datalen; |
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} else {
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s->rregs[4] |= STAT_DO;
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s->ti_size = -datalen; |
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} |
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} |
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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} |
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static void handle_satn(ESPState *s) |
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{ |
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uint8_t buf[32];
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int len;
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len = get_cmd(s, buf); |
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if (len)
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do_cmd(s, buf); |
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} |
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static void handle_satn_stop(ESPState *s) |
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{ |
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s->cmdlen = get_cmd(s, s->cmdbuf); |
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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s->do_cmd = 1;
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s->espdmaregs[1] += s->cmdlen;
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s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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} |
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} |
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static void write_response(ESPState *s) |
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{ |
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uint32_t dmaptr; |
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DPRINTF("Transfer status (sense=%d)\n", s->sense);
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s->ti_buf[0] = s->sense;
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s->ti_buf[1] = 0; |
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if (s->dma) {
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dmaptr = iommu_translate(s->espdmaregs[1]);
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DPRINTF("DMA Direction: %c\n",
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s->espdmaregs[0] & DMA_WRITE_MEM ? 'w': 'r'); |
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cpu_physical_memory_write(dmaptr, s->ti_buf, 2);
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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} else {
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[7] = 2; |
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} |
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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} |
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static void esp_do_dma(ESPState *s) |
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{ |
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uint32_t dmaptr, minlen, len, from, to; |
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int to_device;
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dmaptr = iommu_translate(s->espdmaregs[1]);
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to_device = (s->espdmaregs[0] & DMA_WRITE_MEM) == 0; |
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from = s->espdmaregs[1];
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minlen = s->dma_left; |
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to = from + minlen; |
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dmaptr = iommu_translate(s->espdmaregs[1]);
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if ((from & TARGET_PAGE_MASK) != (to & TARGET_PAGE_MASK)) {
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len = TARGET_PAGE_SIZE - (from & ~TARGET_PAGE_MASK); |
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} else {
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len = to - from; |
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} |
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DPRINTF("DMA address p %08x v %08x len %08x, from %08x, to %08x\n", dmaptr, s->espdmaregs[1], len, from, to); |
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s->espdmaregs[1] += len;
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if (s->do_cmd) {
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s->ti_size -= len; |
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DPRINTF("command len %d + %d\n", s->cmdlen, len);
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cpu_physical_memory_read(dmaptr, &s->cmdbuf[s->cmdlen], len); |
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf); |
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return;
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} else {
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s->async_len = len; |
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s->dma_left -= len; |
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if (to_device) {
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s->async_ptr = -1;
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cpu_physical_memory_read(dmaptr, s->async_buf, len); |
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scsi_write_data(s->current_dev, s->async_buf, len); |
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} else {
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s->async_ptr = dmaptr; |
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scsi_read_data(s->current_dev, s->async_buf, len); |
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} |
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} |
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} |
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static void esp_command_complete(void *opaque, uint32_t reason, int sense) |
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{ |
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ESPState *s = (ESPState *)opaque; |
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s->ti_size -= s->async_len; |
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s->espdmaregs[1] += s->async_len;
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if (s->async_ptr != (uint32_t)-1) { |
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cpu_physical_memory_write(s->async_ptr, s->async_buf, s->async_len); |
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} |
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if (reason == SCSI_REASON_DONE) {
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DPRINTF("SCSI Command complete\n");
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if (s->ti_size != 0) |
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DPRINTF("SCSI command completed unexpectedly\n");
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s->ti_size = 0;
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if (sense)
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DPRINTF("Command failed\n");
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s->sense = sense; |
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} else {
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DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
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} |
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if (s->dma_left) {
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esp_do_dma(s); |
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} else {
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if (s->ti_size) {
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s->rregs[4] |= STAT_IN | STAT_TC;
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} else {
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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} |
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s->rregs[5] = INTR_BS;
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s->rregs[6] = 0; |
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s->rregs[7] = 0; |
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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} |
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} |
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static void handle_ti(ESPState *s) |
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{ |
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uint32_t dmalen, minlen; |
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dmalen = s->wregs[0] | (s->wregs[1] << 8); |
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if (dmalen==0) { |
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dmalen=0x10000;
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} |
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if (s->do_cmd)
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minlen = (dmalen < 32) ? dmalen : 32; |
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else
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minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
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DPRINTF("Transfer Information len %d\n", minlen);
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if (s->dma) {
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s->dma_left = minlen; |
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s->rregs[4] &= ~STAT_TC;
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esp_do_dma(s); |
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} else if (s->do_cmd) { |
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DPRINTF("command len %d\n", s->cmdlen);
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf); |
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return;
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} |
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} |
308 |
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static void esp_reset(void *opaque) |
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{ |
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ESPState *s = opaque; |
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memset(s->rregs, 0, ESP_MAXREG);
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memset(s->wregs, 0, ESP_MAXREG);
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s->rregs[0x0e] = 0x4; // Indicate fas100a |
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memset(s->espdmaregs, 0, ESPDMA_REGS * 4); |
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->dma = 0;
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s->do_cmd = 0;
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} |
322 |
|
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static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
324 |
{ |
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ESPState *s = opaque; |
326 |
uint32_t saddr; |
327 |
|
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saddr = (addr & ESP_MAXREG) >> 2;
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DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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switch (saddr) {
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case 2: |
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// FIFO
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if (s->ti_size > 0) { |
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s->ti_size--; |
335 |
if ((s->rregs[4] & 6) == 0) { |
336 |
/* Data in/out. */
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scsi_read_data(s->current_dev, &s->rregs[2], 0); |
338 |
} else {
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s->rregs[2] = s->ti_buf[s->ti_rptr++];
|
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} |
341 |
pic_set_irq(s->irq, 1);
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} |
343 |
if (s->ti_size == 0) { |
344 |
s->ti_rptr = 0;
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s->ti_wptr = 0;
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} |
347 |
break;
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case 5: |
349 |
// interrupt
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// Clear interrupt/error status bits
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s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
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pic_set_irq(s->irq, 0);
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s->espdmaregs[0] &= ~DMA_INTR;
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break;
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default:
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break;
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} |
358 |
return s->rregs[saddr];
|
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} |
360 |
|
361 |
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
362 |
{ |
363 |
ESPState *s = opaque; |
364 |
uint32_t saddr; |
365 |
|
366 |
saddr = (addr & ESP_MAXREG) >> 2;
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DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
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368 |
switch (saddr) {
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369 |
case 0: |
370 |
case 1: |
371 |
s->rregs[saddr] = val; |
372 |
s->rregs[4] &= ~STAT_TC;
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break;
|
374 |
case 2: |
375 |
// FIFO
|
376 |
if (s->do_cmd) {
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377 |
s->cmdbuf[s->cmdlen++] = val & 0xff;
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378 |
} else if ((s->rregs[4] & 6) == 0) { |
379 |
uint8_t buf; |
380 |
buf = val & 0xff;
|
381 |
s->ti_size--; |
382 |
scsi_write_data(s->current_dev, &buf, 0);
|
383 |
} else {
|
384 |
s->ti_size++; |
385 |
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
386 |
} |
387 |
break;
|
388 |
case 3: |
389 |
s->rregs[saddr] = val; |
390 |
// Command
|
391 |
if (val & 0x80) { |
392 |
s->dma = 1;
|
393 |
} else {
|
394 |
s->dma = 0;
|
395 |
} |
396 |
switch(val & 0x7f) { |
397 |
case 0: |
398 |
DPRINTF("NOP (%2.2x)\n", val);
|
399 |
break;
|
400 |
case 1: |
401 |
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
402 |
//s->ti_size = 0;
|
403 |
s->rregs[5] = INTR_FC;
|
404 |
s->rregs[6] = 0; |
405 |
break;
|
406 |
case 2: |
407 |
DPRINTF("Chip reset (%2.2x)\n", val);
|
408 |
esp_reset(s); |
409 |
break;
|
410 |
case 3: |
411 |
DPRINTF("Bus reset (%2.2x)\n", val);
|
412 |
s->rregs[5] = INTR_RST;
|
413 |
if (!(s->wregs[8] & 0x40)) { |
414 |
s->espdmaregs[0] |= DMA_INTR;
|
415 |
pic_set_irq(s->irq, 1);
|
416 |
} |
417 |
break;
|
418 |
case 0x10: |
419 |
handle_ti(s); |
420 |
break;
|
421 |
case 0x11: |
422 |
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
423 |
write_response(s); |
424 |
break;
|
425 |
case 0x12: |
426 |
DPRINTF("Message Accepted (%2.2x)\n", val);
|
427 |
write_response(s); |
428 |
s->rregs[5] = INTR_DC;
|
429 |
s->rregs[6] = 0; |
430 |
break;
|
431 |
case 0x1a: |
432 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
433 |
break;
|
434 |
case 0x42: |
435 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
436 |
handle_satn(s); |
437 |
break;
|
438 |
case 0x43: |
439 |
DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
440 |
handle_satn_stop(s); |
441 |
break;
|
442 |
default:
|
443 |
DPRINTF("Unhandled ESP command (%2.2x)\n", val);
|
444 |
break;
|
445 |
} |
446 |
break;
|
447 |
case 4 ... 7: |
448 |
break;
|
449 |
case 8: |
450 |
s->rregs[saddr] = val; |
451 |
break;
|
452 |
case 9 ... 10: |
453 |
break;
|
454 |
case 11: |
455 |
s->rregs[saddr] = val & 0x15;
|
456 |
break;
|
457 |
case 12 ... 15: |
458 |
s->rregs[saddr] = val; |
459 |
break;
|
460 |
default:
|
461 |
break;
|
462 |
} |
463 |
s->wregs[saddr] = val; |
464 |
} |
465 |
|
466 |
static CPUReadMemoryFunc *esp_mem_read[3] = { |
467 |
esp_mem_readb, |
468 |
esp_mem_readb, |
469 |
esp_mem_readb, |
470 |
}; |
471 |
|
472 |
static CPUWriteMemoryFunc *esp_mem_write[3] = { |
473 |
esp_mem_writeb, |
474 |
esp_mem_writeb, |
475 |
esp_mem_writeb, |
476 |
}; |
477 |
|
478 |
static uint32_t espdma_mem_readl(void *opaque, target_phys_addr_t addr) |
479 |
{ |
480 |
ESPState *s = opaque; |
481 |
uint32_t saddr; |
482 |
|
483 |
saddr = (addr & ESPDMA_MAXADDR) >> 2;
|
484 |
DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->espdmaregs[saddr]);
|
485 |
|
486 |
return s->espdmaregs[saddr];
|
487 |
} |
488 |
|
489 |
static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
490 |
{ |
491 |
ESPState *s = opaque; |
492 |
uint32_t saddr; |
493 |
|
494 |
saddr = (addr & ESPDMA_MAXADDR) >> 2;
|
495 |
DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->espdmaregs[saddr], val);
|
496 |
switch (saddr) {
|
497 |
case 0: |
498 |
if (!(val & DMA_INTREN))
|
499 |
pic_set_irq(s->irq, 0);
|
500 |
if (val & 0x80) { |
501 |
esp_reset(s); |
502 |
} else if (val & 0x40) { |
503 |
val &= ~0x40;
|
504 |
} else if (val == 0) |
505 |
val = 0x40;
|
506 |
val &= 0x0fffffff;
|
507 |
val |= DMA_VER; |
508 |
break;
|
509 |
case 1: |
510 |
s->espdmaregs[0] |= DMA_LOADED;
|
511 |
break;
|
512 |
default:
|
513 |
break;
|
514 |
} |
515 |
s->espdmaregs[saddr] = val; |
516 |
} |
517 |
|
518 |
static CPUReadMemoryFunc *espdma_mem_read[3] = { |
519 |
espdma_mem_readl, |
520 |
espdma_mem_readl, |
521 |
espdma_mem_readl, |
522 |
}; |
523 |
|
524 |
static CPUWriteMemoryFunc *espdma_mem_write[3] = { |
525 |
espdma_mem_writel, |
526 |
espdma_mem_writel, |
527 |
espdma_mem_writel, |
528 |
}; |
529 |
|
530 |
static void esp_save(QEMUFile *f, void *opaque) |
531 |
{ |
532 |
ESPState *s = opaque; |
533 |
unsigned int i; |
534 |
|
535 |
qemu_put_buffer(f, s->rregs, ESP_MAXREG); |
536 |
qemu_put_buffer(f, s->wregs, ESP_MAXREG); |
537 |
qemu_put_be32s(f, &s->irq); |
538 |
for (i = 0; i < ESPDMA_REGS; i++) |
539 |
qemu_put_be32s(f, &s->espdmaregs[i]); |
540 |
qemu_put_be32s(f, &s->ti_size); |
541 |
qemu_put_be32s(f, &s->ti_rptr); |
542 |
qemu_put_be32s(f, &s->ti_wptr); |
543 |
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
544 |
qemu_put_be32s(f, &s->dma); |
545 |
} |
546 |
|
547 |
static int esp_load(QEMUFile *f, void *opaque, int version_id) |
548 |
{ |
549 |
ESPState *s = opaque; |
550 |
unsigned int i; |
551 |
|
552 |
if (version_id != 1) |
553 |
return -EINVAL;
|
554 |
|
555 |
qemu_get_buffer(f, s->rregs, ESP_MAXREG); |
556 |
qemu_get_buffer(f, s->wregs, ESP_MAXREG); |
557 |
qemu_get_be32s(f, &s->irq); |
558 |
for (i = 0; i < ESPDMA_REGS; i++) |
559 |
qemu_get_be32s(f, &s->espdmaregs[i]); |
560 |
qemu_get_be32s(f, &s->ti_size); |
561 |
qemu_get_be32s(f, &s->ti_rptr); |
562 |
qemu_get_be32s(f, &s->ti_wptr); |
563 |
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
564 |
qemu_get_be32s(f, &s->dma); |
565 |
|
566 |
return 0; |
567 |
} |
568 |
|
569 |
void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr) |
570 |
{ |
571 |
ESPState *s; |
572 |
int esp_io_memory, espdma_io_memory;
|
573 |
int i;
|
574 |
|
575 |
s = qemu_mallocz(sizeof(ESPState));
|
576 |
if (!s)
|
577 |
return;
|
578 |
|
579 |
s->bd = bd; |
580 |
s->irq = irq; |
581 |
|
582 |
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
|
583 |
cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
|
584 |
|
585 |
espdma_io_memory = cpu_register_io_memory(0, espdma_mem_read, espdma_mem_write, s);
|
586 |
cpu_register_physical_memory(espdaddr, 16, espdma_io_memory);
|
587 |
|
588 |
esp_reset(s); |
589 |
|
590 |
register_savevm("esp", espaddr, 1, esp_save, esp_load, s); |
591 |
qemu_register_reset(esp_reset, s); |
592 |
for (i = 0; i < MAX_DISKS; i++) { |
593 |
if (bs_table[i]) {
|
594 |
s->scsi_dev[i] = |
595 |
scsi_disk_init(bs_table[i], esp_command_complete, s); |
596 |
} |
597 |
} |
598 |
} |
599 |
|