Revision 4e12cd94

b/hw/cirrus_vga.c
220 220
        ( /* check dst is within bounds */ \
221 221
            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
222 222
                + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
223
                    (s)->vram_size \
223
                    (s)->vga.vram_size \
224 224
        ) || \
225 225
        ( /* check src is within bounds */ \
226 226
            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
227 227
                + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
228
                    (s)->vram_size \
228
                    (s)->vga.vram_size \
229 229
        ) \
230 230
    )
231 231

  
......
238 238
                              uint8_t *dst, int dst_pitch, int width, int height);
239 239

  
240 240
typedef struct CirrusVGAState {
241
    VGA_STATE_COMMON
241
    VGACommonState vga;
242 242

  
243 243
    int cirrus_linear_io_addr;
244 244
    int cirrus_linear_bitblt_io_addr;
......
599 599
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
600 600
        break;
601 601
    case 2:
602
        color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
602
        color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
603 603
        s->cirrus_blt_fgcol = le16_to_cpu(color);
604 604
        break;
605 605
    case 3:
606 606
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
607
            (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
607
            (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
608 608
        break;
609 609
    default:
610 610
    case 4:
611
        color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
612
            (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
611
        color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
612
            (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
613 613
        s->cirrus_blt_fgcol = le32_to_cpu(color);
614 614
        break;
615 615
    }
......
623 623
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
624 624
        break;
625 625
    case 2:
626
        color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
626
        color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
627 627
        s->cirrus_blt_bgcol = le16_to_cpu(color);
628 628
        break;
629 629
    case 3:
630 630
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
631
            (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
631
            (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
632 632
        break;
633 633
    default:
634 634
    case 4:
635
        color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
636
            (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
635
        color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
636
            (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
637 637
        s->cirrus_blt_bgcol = le32_to_cpu(color);
638 638
        break;
639 639
    }
......
652 652
	off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
653 653
	off_cur &= TARGET_PAGE_MASK;
654 654
	while (off_cur < off_cur_end) {
655
	    cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
655
	    cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
656 656
	    off_cur += TARGET_PAGE_SIZE;
657 657
	}
658 658
	off_begin += off_pitch;
......
664 664
{
665 665
    uint8_t *dst;
666 666

  
667
    dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
667
    dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
668 668

  
669 669
    if (BLTUNSAFE(s))
670 670
        return 0;
......
687 687
    if (BLTUNSAFE(s))
688 688
        return 0;
689 689
    rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
690
    rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
690
    rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
691 691
             s->cirrus_blt_dstpitch,
692 692
             s->cirrus_blt_width, s->cirrus_blt_height);
693 693
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
......
706 706
static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
707 707
{
708 708
    return cirrus_bitblt_common_patterncopy(s,
709
					    s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
709
					    s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
710 710
                                            s->cirrus_addr_mask));
711 711
}
712 712

  
......
718 718
    int depth;
719 719
    int notify = 0;
720 720

  
721
    depth = s->get_bpp((VGAState *)s) / 8;
722
    s->get_resolution((VGAState *)s, &width, &height);
721
    depth = s->vga.get_bpp(&s->vga) / 8;
722
    s->vga.get_resolution(&s->vga, &width, &height);
723 723

  
724 724
    /* extra x, y */
725 725
    sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
......
757 757
    if (notify)
758 758
	vga_hw_update();
759 759

  
760
    (*s->cirrus_rop) (s, s->vram_ptr +
760
    (*s->cirrus_rop) (s, s->vga.vram_ptr +
761 761
		      (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
762
		      s->vram_ptr +
762
		      s->vga.vram_ptr +
763 763
		      (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
764 764
		      s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
765 765
		      s->cirrus_blt_width, s->cirrus_blt_height);
766 766

  
767 767
    if (notify)
768
	qemu_console_copy(s->ds,
768
	qemu_console_copy(s->vga.ds,
769 769
			  sx, sy, dx, dy,
770 770
			  s->cirrus_blt_width / depth,
771 771
			  s->cirrus_blt_height);
......
783 783
    if (BLTUNSAFE(s))
784 784
        return 0;
785 785

  
786
    cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
787
            s->cirrus_blt_srcaddr - s->start_addr,
786
    cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
787
            s->cirrus_blt_srcaddr - s->vga.start_addr,
788 788
            s->cirrus_blt_width, s->cirrus_blt_height);
789 789

  
790 790
    return 1;
......
810 810
        } else {
811 811
            /* at least one scan line */
812 812
            do {
813
                (*s->cirrus_rop)(s, s->vram_ptr +
813
                (*s->cirrus_rop)(s, s->vga.vram_ptr +
814 814
                                 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
815 815
                                  s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
816 816
                cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
......
842 842
{
843 843
    int need_update;
844 844

  
845
    s->gr[0x31] &=
845
    s->vga.gr[0x31] &=
846 846
	~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
847 847
    need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
848 848
        || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
......
916 916
{
917 917
    uint8_t blt_rop;
918 918

  
919
    s->gr[0x31] |= CIRRUS_BLT_BUSY;
919
    s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
920 920

  
921
    s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
922
    s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
923
    s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
924
    s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
921
    s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
922
    s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
923
    s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
924
    s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
925 925
    s->cirrus_blt_dstaddr =
926
	(s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
926
	(s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
927 927
    s->cirrus_blt_srcaddr =
928
	(s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
929
    s->cirrus_blt_mode = s->gr[0x30];
930
    s->cirrus_blt_modeext = s->gr[0x33];
931
    blt_rop = s->gr[0x32];
928
	(s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
929
    s->cirrus_blt_mode = s->vga.gr[0x30];
930
    s->cirrus_blt_modeext = s->vga.gr[0x33];
931
    blt_rop = s->vga.gr[0x32];
932 932

  
933 933
#ifdef DEBUG_BITBLT
934 934
    printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
......
941 941
           s->cirrus_blt_srcpitch,
942 942
           s->cirrus_blt_dstaddr,
943 943
           s->cirrus_blt_srcaddr,
944
           s->gr[0x2f]);
944
           s->vga.gr[0x2f]);
945 945
#endif
946 946

  
947 947
    switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
......
1059 1059
{
1060 1060
    unsigned old_value;
1061 1061

  
1062
    old_value = s->gr[0x31];
1063
    s->gr[0x31] = reg_value;
1062
    old_value = s->vga.gr[0x31];
1063
    s->vga.gr[0x31] = reg_value;
1064 1064

  
1065 1065
    if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1066 1066
	((reg_value & CIRRUS_BLT_RESET) == 0)) {
......
1083 1083
                               uint32_t *pstart_addr,
1084 1084
                               uint32_t *pline_compare)
1085 1085
{
1086
    CirrusVGAState * s = (CirrusVGAState *)s1;
1086
    CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1087 1087
    uint32_t start_addr, line_offset, line_compare;
1088 1088

  
1089
    line_offset = s->cr[0x13]
1090
	| ((s->cr[0x1b] & 0x10) << 4);
1089
    line_offset = s->vga.cr[0x13]
1090
	| ((s->vga.cr[0x1b] & 0x10) << 4);
1091 1091
    line_offset <<= 3;
1092 1092
    *pline_offset = line_offset;
1093 1093

  
1094
    start_addr = (s->cr[0x0c] << 8)
1095
	| s->cr[0x0d]
1096
	| ((s->cr[0x1b] & 0x01) << 16)
1097
	| ((s->cr[0x1b] & 0x0c) << 15)
1098
	| ((s->cr[0x1d] & 0x80) << 12);
1094
    start_addr = (s->vga.cr[0x0c] << 8)
1095
	| s->vga.cr[0x0d]
1096
	| ((s->vga.cr[0x1b] & 0x01) << 16)
1097
	| ((s->vga.cr[0x1b] & 0x0c) << 15)
1098
	| ((s->vga.cr[0x1d] & 0x80) << 12);
1099 1099
    *pstart_addr = start_addr;
1100 1100

  
1101
    line_compare = s->cr[0x18] |
1102
        ((s->cr[0x07] & 0x10) << 4) |
1103
        ((s->cr[0x09] & 0x40) << 3);
1101
    line_compare = s->vga.cr[0x18] |
1102
        ((s->vga.cr[0x07] & 0x10) << 4) |
1103
        ((s->vga.cr[0x09] & 0x40) << 3);
1104 1104
    *pline_compare = line_compare;
1105 1105
}
1106 1106

  
......
1128 1128

  
1129 1129
static int cirrus_get_bpp(VGAState *s1)
1130 1130
{
1131
    CirrusVGAState * s = (CirrusVGAState *)s1;
1131
    CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1132 1132
    uint32_t ret = 8;
1133 1133

  
1134
    if ((s->sr[0x07] & 0x01) != 0) {
1134
    if ((s->vga.sr[0x07] & 0x01) != 0) {
1135 1135
	/* Cirrus SVGA */
1136
	switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1136
	switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1137 1137
	case CIRRUS_SR7_BPP_8:
1138 1138
	    ret = 8;
1139 1139
	    break;
......
1151 1151
	    break;
1152 1152
	default:
1153 1153
#ifdef DEBUG_CIRRUS
1154
	    printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1154
	    printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1155 1155
#endif
1156 1156
	    ret = 8;
1157 1157
	    break;
......
1191 1191
    unsigned offset;
1192 1192
    unsigned limit;
1193 1193

  
1194
    if ((s->gr[0x0b] & 0x01) != 0)	/* dual bank */
1195
	offset = s->gr[0x09 + bank_index];
1194
    if ((s->vga.gr[0x0b] & 0x01) != 0)	/* dual bank */
1195
	offset = s->vga.gr[0x09 + bank_index];
1196 1196
    else			/* single bank */
1197
	offset = s->gr[0x09];
1197
	offset = s->vga.gr[0x09];
1198 1198

  
1199
    if ((s->gr[0x0b] & 0x20) != 0)
1199
    if ((s->vga.gr[0x0b] & 0x20) != 0)
1200 1200
	offset <<= 14;
1201 1201
    else
1202 1202
	offset <<= 12;
......
1206 1206
    else
1207 1207
	limit = s->real_vram_size - offset;
1208 1208

  
1209
    if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1209
    if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1210 1210
	if (limit > 0x8000) {
1211 1211
	    offset += 0x8000;
1212 1212
	    limit -= 0x8000;
......
1218 1218
    if (limit > 0) {
1219 1219
        /* Thinking about changing bank base? First, drop the dirty bitmap information
1220 1220
         * on the current location, otherwise we lose this pointer forever */
1221
        if (s->lfb_vram_mapped) {
1221
        if (s->vga.lfb_vram_mapped) {
1222 1222
            target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1223 1223
            cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1224 1224
        }
......
1247 1247
    case 0x04:			// Standard VGA
1248 1248
	return CIRRUS_HOOK_NOT_HANDLED;
1249 1249
    case 0x06:			// Unlock Cirrus extensions
1250
	*reg_value = s->sr[reg_index];
1250
	*reg_value = s->vga.sr[reg_index];
1251 1251
	break;
1252 1252
    case 0x10:
1253 1253
    case 0x30:
......
1257 1257
    case 0xb0:
1258 1258
    case 0xd0:
1259 1259
    case 0xf0:			// Graphics Cursor X
1260
	*reg_value = s->sr[0x10];
1260
	*reg_value = s->vga.sr[0x10];
1261 1261
	break;
1262 1262
    case 0x11:
1263 1263
    case 0x31:
......
1267 1267
    case 0xb1:
1268 1268
    case 0xd1:
1269 1269
    case 0xf1:			// Graphics Cursor Y
1270
	*reg_value = s->sr[0x11];
1270
	*reg_value = s->vga.sr[0x11];
1271 1271
	break;
1272 1272
    case 0x05:			// ???
1273 1273
    case 0x07:			// Extended Sequencer Mode
......
1296 1296
#ifdef DEBUG_CIRRUS
1297 1297
	printf("cirrus: handled inport sr_index %02x\n", reg_index);
1298 1298
#endif
1299
	*reg_value = s->sr[reg_index];
1299
	*reg_value = s->vga.sr[reg_index];
1300 1300
	break;
1301 1301
    default:
1302 1302
#ifdef DEBUG_CIRRUS
......
1322 1322
    case 0x06:			// Unlock Cirrus extensions
1323 1323
	reg_value &= 0x17;
1324 1324
	if (reg_value == 0x12) {
1325
	    s->sr[reg_index] = 0x12;
1325
	    s->vga.sr[reg_index] = 0x12;
1326 1326
	} else {
1327
	    s->sr[reg_index] = 0x0f;
1327
	    s->vga.sr[reg_index] = 0x0f;
1328 1328
	}
1329 1329
	break;
1330 1330
    case 0x10:
......
1335 1335
    case 0xb0:
1336 1336
    case 0xd0:
1337 1337
    case 0xf0:			// Graphics Cursor X
1338
	s->sr[0x10] = reg_value;
1338
	s->vga.sr[0x10] = reg_value;
1339 1339
	s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1340 1340
	break;
1341 1341
    case 0x11:
......
1346 1346
    case 0xb1:
1347 1347
    case 0xd1:
1348 1348
    case 0xf1:			// Graphics Cursor Y
1349
	s->sr[0x11] = reg_value;
1349
	s->vga.sr[0x11] = reg_value;
1350 1350
	s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1351 1351
	break;
1352 1352
    case 0x07:			// Extended Sequencer Mode
......
1372 1372
    case 0x1d:			// VCLK 2 Denominator & Post
1373 1373
    case 0x1e:			// VCLK 3 Denominator & Post
1374 1374
    case 0x1f:			// BIOS Write Enable and MCLK select
1375
	s->sr[reg_index] = reg_value;
1375
	s->vga.sr[reg_index] = reg_value;
1376 1376
#ifdef DEBUG_CIRRUS
1377 1377
	printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1378 1378
	       reg_index, reg_value);
1379 1379
#endif
1380 1380
	break;
1381 1381
    case 0x17:			// Configuration Readback and Extended Control
1382
	s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1382
	s->vga.sr[reg_index] = (s->vga.sr[reg_index] & 0x38) | (reg_value & 0xc7);
1383 1383
        cirrus_update_memory_access(s);
1384 1384
        break;
1385 1385
    default:
......
1427 1427

  
1428 1428
static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1429 1429
{
1430
    if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1430
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1431 1431
	return CIRRUS_HOOK_NOT_HANDLED;
1432 1432
    *reg_value =
1433
        s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1434
                                 s->dac_sub_index];
1435
    if (++s->dac_sub_index == 3) {
1436
	s->dac_sub_index = 0;
1437
	s->dac_read_index++;
1433
        s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1434
                                 s->vga.dac_sub_index];
1435
    if (++s->vga.dac_sub_index == 3) {
1436
	s->vga.dac_sub_index = 0;
1437
	s->vga.dac_read_index++;
1438 1438
    }
1439 1439
    return CIRRUS_HOOK_HANDLED;
1440 1440
}
1441 1441

  
1442 1442
static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1443 1443
{
1444
    if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1444
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1445 1445
	return CIRRUS_HOOK_NOT_HANDLED;
1446
    s->dac_cache[s->dac_sub_index] = reg_value;
1447
    if (++s->dac_sub_index == 3) {
1448
        memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1449
               s->dac_cache, 3);
1446
    s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1447
    if (++s->vga.dac_sub_index == 3) {
1448
        memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1449
               s->vga.dac_cache, 3);
1450 1450
        /* XXX update cursor */
1451
	s->dac_sub_index = 0;
1452
	s->dac_write_index++;
1451
	s->vga.dac_sub_index = 0;
1452
	s->vga.dac_write_index++;
1453 1453
    }
1454 1454
    return CIRRUS_HOOK_HANDLED;
1455 1455
}
......
1483 1483
    }
1484 1484

  
1485 1485
    if (reg_index < 0x3a) {
1486
	*reg_value = s->gr[reg_index];
1486
	*reg_value = s->vga.gr[reg_index];
1487 1487
    } else {
1488 1488
#ifdef DEBUG_CIRRUS
1489 1489
	printf("cirrus: inport gr_index %02x\n", reg_index);
......
1515 1515
    case 0x08:			// Standard VGA
1516 1516
	return CIRRUS_HOOK_NOT_HANDLED;
1517 1517
    case 0x05:			// Standard VGA, Cirrus extended mode
1518
	s->gr[reg_index] = reg_value & 0x7f;
1518
	s->vga.gr[reg_index] = reg_value & 0x7f;
1519 1519
        cirrus_update_memory_access(s);
1520 1520
	break;
1521 1521
    case 0x09:			// bank offset #0
1522 1522
    case 0x0A:			// bank offset #1
1523
	s->gr[reg_index] = reg_value;
1523
	s->vga.gr[reg_index] = reg_value;
1524 1524
	cirrus_update_bank_ptr(s, 0);
1525 1525
	cirrus_update_bank_ptr(s, 1);
1526 1526
        cirrus_update_memory_access(s);
1527 1527
        break;
1528 1528
    case 0x0B:
1529
	s->gr[reg_index] = reg_value;
1529
	s->vga.gr[reg_index] = reg_value;
1530 1530
	cirrus_update_bank_ptr(s, 0);
1531 1531
	cirrus_update_bank_ptr(s, 1);
1532 1532
        cirrus_update_memory_access(s);
......
1553 1553
    case 0x35:			// BLT TRANSPARENT COLOR 0xff00
1554 1554
    case 0x38:			// BLT TRANSPARENT COLOR MASK 0x00ff
1555 1555
    case 0x39:			// BLT TRANSPARENT COLOR MASK 0xff00
1556
	s->gr[reg_index] = reg_value;
1556
	s->vga.gr[reg_index] = reg_value;
1557 1557
	break;
1558 1558
    case 0x21:			// BLT WIDTH 0x001f00
1559 1559
    case 0x23:			// BLT HEIGHT 0x001f00
1560 1560
    case 0x25:			// BLT DEST PITCH 0x001f00
1561 1561
    case 0x27:			// BLT SRC PITCH 0x001f00
1562
	s->gr[reg_index] = reg_value & 0x1f;
1562
	s->vga.gr[reg_index] = reg_value & 0x1f;
1563 1563
	break;
1564 1564
    case 0x2a:			// BLT DEST ADDR 0x3f0000
1565
	s->gr[reg_index] = reg_value & 0x3f;
1565
	s->vga.gr[reg_index] = reg_value & 0x3f;
1566 1566
        /* if auto start mode, starts bit blt now */
1567
        if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1567
        if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1568 1568
            cirrus_bitblt_start(s);
1569 1569
        }
1570 1570
	break;
1571 1571
    case 0x2e:			// BLT SRC ADDR 0x3f0000
1572
	s->gr[reg_index] = reg_value & 0x3f;
1572
	s->vga.gr[reg_index] = reg_value & 0x3f;
1573 1573
	break;
1574 1574
    case 0x31:			// BLT STATUS/START
1575 1575
	cirrus_write_bitblt(s, reg_value);
......
1622 1622
    case 0x18:			// Standard VGA
1623 1623
	return CIRRUS_HOOK_NOT_HANDLED;
1624 1624
    case 0x24:			// Attribute Controller Toggle Readback (R)
1625
        *reg_value = (s->ar_flip_flop << 7);
1625
        *reg_value = (s->vga.ar_flip_flop << 7);
1626 1626
        break;
1627 1627
    case 0x19:			// Interlace End
1628 1628
    case 0x1a:			// Miscellaneous Control
......
1632 1632
    case 0x22:			// Graphics Data Latches Readback (R)
1633 1633
    case 0x25:			// Part Status
1634 1634
    case 0x27:			// Part ID (R)
1635
	*reg_value = s->cr[reg_index];
1635
	*reg_value = s->vga.cr[reg_index];
1636 1636
	break;
1637 1637
    case 0x26:			// Attribute Controller Index Readback (R)
1638
	*reg_value = s->ar_index & 0x3f;
1638
	*reg_value = s->vga.ar_index & 0x3f;
1639 1639
	break;
1640 1640
    default:
1641 1641
#ifdef DEBUG_CIRRUS
......
1683 1683
    case 0x1b:			// Extended Display Control
1684 1684
    case 0x1c:			// Sync Adjust and Genlock
1685 1685
    case 0x1d:			// Overlay Extended Control
1686
	s->cr[reg_index] = reg_value;
1686
	s->vga.cr[reg_index] = reg_value;
1687 1687
#ifdef DEBUG_CIRRUS
1688 1688
	printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1689 1689
	       reg_index, reg_value);
......
1946 1946
    unsigned val = mem_value;
1947 1947
    uint8_t *dst;
1948 1948

  
1949
    dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1949
    dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1950 1950
    for (x = 0; x < 8; x++) {
1951 1951
	if (val & 0x80) {
1952 1952
	    *dst = s->cirrus_shadow_gr1;
......
1956 1956
	val <<= 1;
1957 1957
	dst++;
1958 1958
    }
1959
    cpu_physical_memory_set_dirty(s->vram_offset + offset);
1960
    cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1959
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1960
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
1961 1961
}
1962 1962

  
1963 1963
static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
......
1969 1969
    unsigned val = mem_value;
1970 1970
    uint8_t *dst;
1971 1971

  
1972
    dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1972
    dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1973 1973
    for (x = 0; x < 8; x++) {
1974 1974
	if (val & 0x80) {
1975 1975
	    *dst = s->cirrus_shadow_gr1;
1976
	    *(dst + 1) = s->gr[0x11];
1976
	    *(dst + 1) = s->vga.gr[0x11];
1977 1977
	} else if (mode == 5) {
1978 1978
	    *dst = s->cirrus_shadow_gr0;
1979
	    *(dst + 1) = s->gr[0x10];
1979
	    *(dst + 1) = s->vga.gr[0x10];
1980 1980
	}
1981 1981
	val <<= 1;
1982 1982
	dst += 2;
1983 1983
    }
1984
    cpu_physical_memory_set_dirty(s->vram_offset + offset);
1985
    cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1984
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1985
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
1986 1986
}
1987 1987

  
1988 1988
/***************************************
......
1998 1998
    unsigned bank_offset;
1999 1999
    uint32_t val;
2000 2000

  
2001
    if ((s->sr[0x07] & 0x01) == 0) {
2001
    if ((s->vga.sr[0x07] & 0x01) == 0) {
2002 2002
	return vga_mem_readb(s, addr);
2003 2003
    }
2004 2004

  
......
2011 2011
	bank_offset = addr & 0x7fff;
2012 2012
	if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2013 2013
	    bank_offset += s->cirrus_bank_base[bank_index];
2014
	    if ((s->gr[0x0B] & 0x14) == 0x14) {
2014
	    if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2015 2015
		bank_offset <<= 4;
2016
	    } else if (s->gr[0x0B] & 0x02) {
2016
	    } else if (s->vga.gr[0x0B] & 0x02) {
2017 2017
		bank_offset <<= 3;
2018 2018
	    }
2019 2019
	    bank_offset &= s->cirrus_addr_mask;
2020
	    val = *(s->vram_ptr + bank_offset);
2020
	    val = *(s->vga.vram_ptr + bank_offset);
2021 2021
	} else
2022 2022
	    val = 0xff;
2023 2023
    } else if (addr >= 0x18000 && addr < 0x18100) {
2024 2024
	/* memory-mapped I/O */
2025 2025
	val = 0xff;
2026
	if ((s->sr[0x17] & 0x44) == 0x04) {
2026
	if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2027 2027
	    val = cirrus_mmio_blt_read(s, addr & 0xff);
2028 2028
	}
2029 2029
    } else {
......
2073 2073
    unsigned bank_offset;
2074 2074
    unsigned mode;
2075 2075

  
2076
    if ((s->sr[0x07] & 0x01) == 0) {
2076
    if ((s->vga.sr[0x07] & 0x01) == 0) {
2077 2077
	vga_mem_writeb(s, addr, mem_value);
2078 2078
        return;
2079 2079
    }
......
2093 2093
	    bank_offset = addr & 0x7fff;
2094 2094
	    if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2095 2095
		bank_offset += s->cirrus_bank_base[bank_index];
2096
		if ((s->gr[0x0B] & 0x14) == 0x14) {
2096
		if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2097 2097
		    bank_offset <<= 4;
2098
		} else if (s->gr[0x0B] & 0x02) {
2098
		} else if (s->vga.gr[0x0B] & 0x02) {
2099 2099
		    bank_offset <<= 3;
2100 2100
		}
2101 2101
		bank_offset &= s->cirrus_addr_mask;
2102
		mode = s->gr[0x05] & 0x7;
2103
		if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2104
		    *(s->vram_ptr + bank_offset) = mem_value;
2105
		    cpu_physical_memory_set_dirty(s->vram_offset +
2102
		mode = s->vga.gr[0x05] & 0x7;
2103
		if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2104
		    *(s->vga.vram_ptr + bank_offset) = mem_value;
2105
		    cpu_physical_memory_set_dirty(s->vga.vram_offset +
2106 2106
						  bank_offset);
2107 2107
		} else {
2108
		    if ((s->gr[0x0B] & 0x14) != 0x14) {
2108
		    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2109 2109
			cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2110 2110
							 bank_offset,
2111 2111
							 mem_value);
......
2119 2119
	}
2120 2120
    } else if (addr >= 0x18000 && addr < 0x18100) {
2121 2121
	/* memory-mapped I/O */
2122
	if ((s->sr[0x17] & 0x44) == 0x04) {
2122
	if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2123 2123
	    cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2124 2124
	}
2125 2125
    } else {
......
2176 2176
static inline void invalidate_cursor1(CirrusVGAState *s)
2177 2177
{
2178 2178
    if (s->last_hw_cursor_size) {
2179
        vga_invalidate_scanlines((VGAState *)s,
2179
        vga_invalidate_scanlines(&s->vga,
2180 2180
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2181 2181
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2182 2182
    }
......
2188 2188
    uint32_t content;
2189 2189
    int y, y_min, y_max;
2190 2190

  
2191
    src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2192
    if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2193
        src += (s->sr[0x13] & 0x3c) * 256;
2191
    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2192
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2193
        src += (s->vga.sr[0x13] & 0x3c) * 256;
2194 2194
        y_min = 64;
2195 2195
        y_max = -1;
2196 2196
        for(y = 0; y < 64; y++) {
......
2207 2207
            src += 16;
2208 2208
        }
2209 2209
    } else {
2210
        src += (s->sr[0x13] & 0x3f) * 256;
2210
        src += (s->vga.sr[0x13] & 0x3f) * 256;
2211 2211
        y_min = 32;
2212 2212
        y_max = -1;
2213 2213
        for(y = 0; y < 32; y++) {
......
2235 2235
   update the cursor only if it moves. */
2236 2236
static void cirrus_cursor_invalidate(VGAState *s1)
2237 2237
{
2238
    CirrusVGAState *s = (CirrusVGAState *)s1;
2238
    CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2239 2239
    int size;
2240 2240

  
2241
    if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2241
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2242 2242
        size = 0;
2243 2243
    } else {
2244
        if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2244
        if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2245 2245
            size = 64;
2246 2246
        else
2247 2247
            size = 32;
......
2264 2264

  
2265 2265
static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2266 2266
{
2267
    CirrusVGAState *s = (CirrusVGAState *)s1;
2267
    CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2268 2268
    int w, h, bpp, x1, x2, poffset;
2269 2269
    unsigned int color0, color1;
2270 2270
    const uint8_t *palette, *src;
2271 2271
    uint32_t content;
2272 2272

  
2273
    if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2273
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2274 2274
        return;
2275 2275
    /* fast test to see if the cursor intersects with the scan line */
2276
    if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2276
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2277 2277
        h = 64;
2278 2278
    } else {
2279 2279
        h = 32;
......
2282 2282
        scr_y >= (s->hw_cursor_y + h))
2283 2283
        return;
2284 2284

  
2285
    src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2286
    if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2287
        src += (s->sr[0x13] & 0x3c) * 256;
2285
    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2286
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2287
        src += (s->vga.sr[0x13] & 0x3c) * 256;
2288 2288
        src += (scr_y - s->hw_cursor_y) * 16;
2289 2289
        poffset = 8;
2290 2290
        content = ((uint32_t *)src)[0] |
......
2292 2292
            ((uint32_t *)src)[2] |
2293 2293
            ((uint32_t *)src)[3];
2294 2294
    } else {
2295
        src += (s->sr[0x13] & 0x3f) * 256;
2295
        src += (s->vga.sr[0x13] & 0x3f) * 256;
2296 2296
        src += (scr_y - s->hw_cursor_y) * 4;
2297 2297
        poffset = 128;
2298 2298
        content = ((uint32_t *)src)[0] |
......
2304 2304
    w = h;
2305 2305

  
2306 2306
    x1 = s->hw_cursor_x;
2307
    if (x1 >= s->last_scr_width)
2307
    if (x1 >= s->vga.last_scr_width)
2308 2308
        return;
2309 2309
    x2 = s->hw_cursor_x + w;
2310
    if (x2 > s->last_scr_width)
2311
        x2 = s->last_scr_width;
2310
    if (x2 > s->vga.last_scr_width)
2311
        x2 = s->vga.last_scr_width;
2312 2312
    w = x2 - x1;
2313 2313
    palette = s->cirrus_hidden_palette;
2314
    color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2315
                             c6_to_8(palette[0x0 * 3 + 1]),
2316
                             c6_to_8(palette[0x0 * 3 + 2]));
2317
    color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2318
                             c6_to_8(palette[0xf * 3 + 1]),
2319
                             c6_to_8(palette[0xf * 3 + 2]));
2320
    bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2314
    color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2315
                                 c6_to_8(palette[0x0 * 3 + 1]),
2316
                                 c6_to_8(palette[0x0 * 3 + 2]));
2317
    color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2318
                                 c6_to_8(palette[0xf * 3 + 1]),
2319
                                 c6_to_8(palette[0xf * 3 + 2]));
2320
    bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
2321 2321
    d1 += x1 * bpp;
2322
    switch(ds_get_bits_per_pixel(s->ds)) {
2322
    switch(ds_get_bits_per_pixel(s->vga.ds)) {
2323 2323
    default:
2324 2324
        break;
2325 2325
    case 8:
......
2350 2350

  
2351 2351
    addr &= s->cirrus_addr_mask;
2352 2352

  
2353
    if (((s->sr[0x17] & 0x44) == 0x44) &&
2353
    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2354 2354
        ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2355 2355
	/* memory-mapped I/O */
2356 2356
	ret = cirrus_mmio_blt_read(s, addr & 0xff);
......
2359 2359
	ret = 0xff;
2360 2360
    } else {
2361 2361
	/* video memory */
2362
	if ((s->gr[0x0B] & 0x14) == 0x14) {
2362
	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2363 2363
	    addr <<= 4;
2364
	} else if (s->gr[0x0B] & 0x02) {
2364
	} else if (s->vga.gr[0x0B] & 0x02) {
2365 2365
	    addr <<= 3;
2366 2366
	}
2367 2367
	addr &= s->cirrus_addr_mask;
2368
	ret = *(s->vram_ptr + addr);
2368
	ret = *(s->vga.vram_ptr + addr);
2369 2369
    }
2370 2370

  
2371 2371
    return ret;
......
2409 2409

  
2410 2410
    addr &= s->cirrus_addr_mask;
2411 2411

  
2412
    if (((s->sr[0x17] & 0x44) == 0x44) &&
2412
    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2413 2413
        ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {
2414 2414
	/* memory-mapped I/O */
2415 2415
	cirrus_mmio_blt_write(s, addr & 0xff, val);
......
2421 2421
	}
2422 2422
    } else {
2423 2423
	/* video memory */
2424
	if ((s->gr[0x0B] & 0x14) == 0x14) {
2424
	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2425 2425
	    addr <<= 4;
2426
	} else if (s->gr[0x0B] & 0x02) {
2426
	} else if (s->vga.gr[0x0B] & 0x02) {
2427 2427
	    addr <<= 3;
2428 2428
	}
2429 2429
	addr &= s->cirrus_addr_mask;
2430 2430

  
2431
	mode = s->gr[0x05] & 0x7;
2432
	if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2433
	    *(s->vram_ptr + addr) = (uint8_t) val;
2434
	    cpu_physical_memory_set_dirty(s->vram_offset + addr);
2431
	mode = s->vga.gr[0x05] & 0x7;
2432
	if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2433
	    *(s->vga.vram_ptr + addr) = (uint8_t) val;
2434
	    cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
2435 2435
	} else {
2436
	    if ((s->gr[0x0B] & 0x14) != 0x14) {
2436
	    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2437 2437
		cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2438 2438
	    } else {
2439 2439
		cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
......
2586 2586

  
2587 2587
static void map_linear_vram(CirrusVGAState *s)
2588 2588
{
2589
    if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2590
        s->map_addr = s->lfb_addr;
2591
        s->map_end = s->lfb_end;
2592
        cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2589
    if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2590
        s->vga.map_addr = s->vga.lfb_addr;
2591
        s->vga.map_end = s->vga.lfb_end;
2592
        cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2593 2593
    }
2594 2594

  
2595
    if (!s->map_addr)
2595
    if (!s->vga.map_addr)
2596 2596
        return;
2597 2597

  
2598
    s->lfb_vram_mapped = 0;
2598
    s->vga.lfb_vram_mapped = 0;
2599 2599

  
2600 2600
    if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2601
        && !((s->sr[0x07] & 0x01) == 0)
2602
        && !((s->gr[0x0B] & 0x14) == 0x14)
2603
        && !(s->gr[0x0B] & 0x02)) {
2601
        && !((s->vga.sr[0x07] & 0x01) == 0)
2602
        && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2603
        && !(s->vga.gr[0x0B] & 0x02)) {
2604 2604

  
2605 2605
        cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2606
                                    (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2606
                                    (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2607 2607
        cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2608
                                    (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2608
                                    (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2609 2609

  
2610
        s->lfb_vram_mapped = 1;
2610
        s->vga.lfb_vram_mapped = 1;
2611 2611
    }
2612 2612
    else {
2613 2613
        cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2614
                                     s->vga_io_memory);
2614
                                     s->vga.vga_io_memory);
2615 2615
    }
2616 2616

  
2617
    vga_dirty_log_start((VGAState *)s);
2617
    vga_dirty_log_start(&s->vga);
2618 2618
}
2619 2619

  
2620 2620
static void unmap_linear_vram(CirrusVGAState *s)
2621 2621
{
2622
    if (s->map_addr && s->lfb_addr && s->lfb_end)
2623
        s->map_addr = s->map_end = 0;
2622
    if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
2623
        s->vga.map_addr = s->vga.map_end = 0;
2624 2624

  
2625 2625
    cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2626
                                 s->vga_io_memory);
2626
                                 s->vga.vga_io_memory);
2627 2627
}
2628 2628

  
2629 2629
/* Compute the memory access functions */
......
2631 2631
{
2632 2632
    unsigned mode;
2633 2633

  
2634
    if ((s->sr[0x17] & 0x44) == 0x44) {
2634
    if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2635 2635
        goto generic_io;
2636 2636
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2637 2637
        goto generic_io;
2638 2638
    } else {
2639
	if ((s->gr[0x0B] & 0x14) == 0x14) {
2639
	if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2640 2640
            goto generic_io;
2641
	} else if (s->gr[0x0B] & 0x02) {
2641
	} else if (s->vga.gr[0x0B] & 0x02) {
2642 2642
            goto generic_io;
2643 2643
        }
2644 2644

  
2645
	mode = s->gr[0x05] & 0x7;
2646
	if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2645
	mode = s->vga.gr[0x05] & 0x7;
2646
	if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2647 2647
            map_linear_vram(s);
2648 2648
        } else {
2649 2649
        generic_io:
......
2661 2661
    int val, index;
2662 2662

  
2663 2663
    /* check port range access depending on color/monochrome mode */
2664
    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2664
    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->vga.msr & MSR_COLOR_EMULATION))
2665 2665
	|| (addr >= 0x3d0 && addr <= 0x3df
2666
	    && !(s->msr & MSR_COLOR_EMULATION))) {
2666
	    && !(s->vga.msr & MSR_COLOR_EMULATION))) {
2667 2667
	val = 0xff;
2668 2668
    } else {
2669 2669
	switch (addr) {
2670 2670
	case 0x3c0:
2671
	    if (s->ar_flip_flop == 0) {
2672
		val = s->ar_index;
2671
	    if (s->vga.ar_flip_flop == 0) {
2672
		val = s->vga.ar_index;
2673 2673
	    } else {
2674 2674
		val = 0;
2675 2675
	    }
2676 2676
	    break;
2677 2677
	case 0x3c1:
2678
	    index = s->ar_index & 0x1f;
2678
	    index = s->vga.ar_index & 0x1f;
2679 2679
	    if (index < 21)
2680
		val = s->ar[index];
2680
		val = s->vga.ar[index];
2681 2681
	    else
2682 2682
		val = 0;
2683 2683
	    break;
2684 2684
	case 0x3c2:
2685
	    val = s->st00;
2685
	    val = s->vga.st00;
2686 2686
	    break;
2687 2687
	case 0x3c4:
2688
	    val = s->sr_index;
2688
	    val = s->vga.sr_index;
2689 2689
	    break;
2690 2690
	case 0x3c5:
2691
	    if (cirrus_hook_read_sr(s, s->sr_index, &val))
2691
	    if (cirrus_hook_read_sr(s, s->vga.sr_index, &val))
2692 2692
		break;
2693
	    val = s->sr[s->sr_index];
2693
	    val = s->vga.sr[s->vga.sr_index];
2694 2694
#ifdef DEBUG_VGA_REG
2695
	    printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2695
	    printf("vga: read SR%x = 0x%02x\n", s->vga.sr_index, val);
2696 2696
#endif
2697 2697
	    break;
2698 2698
	case 0x3c6:
2699 2699
	    cirrus_read_hidden_dac(s, &val);
2700 2700
	    break;
2701 2701
	case 0x3c7:
2702
	    val = s->dac_state;
2702
	    val = s->vga.dac_state;
2703 2703
	    break;
2704 2704
	case 0x3c8:
2705
	    val = s->dac_write_index;
2705
	    val = s->vga.dac_write_index;
2706 2706
	    s->cirrus_hidden_dac_lockindex = 0;
2707 2707
	    break;
2708 2708
        case 0x3c9:
2709 2709
	    if (cirrus_hook_read_palette(s, &val))
2710 2710
		break;
2711
	    val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2712
	    if (++s->dac_sub_index == 3) {
2713
		s->dac_sub_index = 0;
2714
		s->dac_read_index++;
2711
	    val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
2712
	    if (++s->vga.dac_sub_index == 3) {
2713
		s->vga.dac_sub_index = 0;
2714
		s->vga.dac_read_index++;
2715 2715
	    }
2716 2716
	    break;
2717 2717
	case 0x3ca:
2718
	    val = s->fcr;
2718
	    val = s->vga.fcr;
2719 2719
	    break;
2720 2720
	case 0x3cc:
2721
	    val = s->msr;
2721
	    val = s->vga.msr;
2722 2722
	    break;
2723 2723
	case 0x3ce:
2724
	    val = s->gr_index;
2724
	    val = s->vga.gr_index;
2725 2725
	    break;
2726 2726
	case 0x3cf:
2727
	    if (cirrus_hook_read_gr(s, s->gr_index, &val))
2727
	    if (cirrus_hook_read_gr(s, s->vga.gr_index, &val))
2728 2728
		break;
2729
	    val = s->gr[s->gr_index];
2729
	    val = s->vga.gr[s->vga.gr_index];
2730 2730
#ifdef DEBUG_VGA_REG
2731
	    printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2731
	    printf("vga: read GR%x = 0x%02x\n", s->vga.gr_index, val);
2732 2732
#endif
2733 2733
	    break;
2734 2734
	case 0x3b4:
2735 2735
	case 0x3d4:
2736
	    val = s->cr_index;
2736
	    val = s->vga.cr_index;
2737 2737
	    break;
2738 2738
	case 0x3b5:
2739 2739
	case 0x3d5:
2740
	    if (cirrus_hook_read_cr(s, s->cr_index, &val))
2740
	    if (cirrus_hook_read_cr(s, s->vga.cr_index, &val))
2741 2741
		break;
2742
	    val = s->cr[s->cr_index];
2742
	    val = s->vga.cr[s->vga.cr_index];
2743 2743
#ifdef DEBUG_VGA_REG
2744
	    printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2744
	    printf("vga: read CR%x = 0x%02x\n", s->vga.cr_index, val);
2745 2745
#endif
2746 2746
	    break;
2747 2747
	case 0x3ba:
2748 2748
	case 0x3da:
2749 2749
	    /* just toggle to fool polling */
2750
	    val = s->st01 = s->retrace((VGAState *) s);
2751
	    s->ar_flip_flop = 0;
2750
	    val = s->vga.st01 = s->vga.retrace(&s->vga);
2751
	    s->vga.ar_flip_flop = 0;
2752 2752
	    break;
2753 2753
	default:
2754 2754
	    val = 0x00;
......
2767 2767
    int index;
2768 2768

  
2769 2769
    /* check port range access depending on color/monochrome mode */
2770
    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2770
    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->vga.msr & MSR_COLOR_EMULATION))
2771 2771
	|| (addr >= 0x3d0 && addr <= 0x3df
2772
	    && !(s->msr & MSR_COLOR_EMULATION)))
2772
	    && !(s->vga.msr & MSR_COLOR_EMULATION)))
2773 2773
	return;
2774 2774

  
2775 2775
#ifdef DEBUG_VGA
......
2778 2778

  
2779 2779
    switch (addr) {
2780 2780
    case 0x3c0:
2781
	if (s->ar_flip_flop == 0) {
2781
	if (s->vga.ar_flip_flop == 0) {
2782 2782
	    val &= 0x3f;
2783
	    s->ar_index = val;
2783
	    s->vga.ar_index = val;
2784 2784
	} else {
2785
	    index = s->ar_index & 0x1f;
2785
	    index = s->vga.ar_index & 0x1f;
2786 2786
	    switch (index) {
2787 2787
	    case 0x00 ... 0x0f:
2788
		s->ar[index] = val & 0x3f;
2788
		s->vga.ar[index] = val & 0x3f;
2789 2789
		break;
2790 2790
	    case 0x10:
2791
		s->ar[index] = val & ~0x10;
2791
		s->vga.ar[index] = val & ~0x10;
2792 2792
		break;
2793 2793
	    case 0x11:
2794
		s->ar[index] = val;
2794
		s->vga.ar[index] = val;
2795 2795
		break;
2796 2796
	    case 0x12:
2797
		s->ar[index] = val & ~0xc0;
2797
		s->vga.ar[index] = val & ~0xc0;
2798 2798
		break;
2799 2799
	    case 0x13:
2800
		s->ar[index] = val & ~0xf0;
2800
		s->vga.ar[index] = val & ~0xf0;
2801 2801
		break;
2802 2802
	    case 0x14:
2803
		s->ar[index] = val & ~0xf0;
2803
		s->vga.ar[index] = val & ~0xf0;
2804 2804
		break;
2805 2805
	    default:
2806 2806
		break;
2807 2807
	    }
2808 2808
	}
2809
	s->ar_flip_flop ^= 1;
2809
	s->vga.ar_flip_flop ^= 1;
2810 2810
	break;
2811 2811
    case 0x3c2:
2812
	s->msr = val & ~0x10;
2813
	s->update_retrace_info((VGAState *) s);
2812
	s->vga.msr = val & ~0x10;
2813
	s->vga.update_retrace_info(&s->vga);
2814 2814
	break;
2815 2815
    case 0x3c4:
2816
	s->sr_index = val;
2816
	s->vga.sr_index = val;
2817 2817
	break;
2818 2818
    case 0x3c5:
2819
	if (cirrus_hook_write_sr(s, s->sr_index, val))
2819
	if (cirrus_hook_write_sr(s, s->vga.sr_index, val))
2820 2820
	    break;
2821 2821
#ifdef DEBUG_VGA_REG
2822
	printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2822
	printf("vga: write SR%x = 0x%02x\n", s->vga.sr_index, val);
2823 2823
#endif
2824
	s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2825
	if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2824
	s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
2825
	if (s->vga.sr_index == 1) s->vga.update_retrace_info(&s->vga);
2826 2826
	break;
2827 2827
    case 0x3c6:
2828 2828
	cirrus_write_hidden_dac(s, val);
2829 2829
	break;
2830 2830
    case 0x3c7:
2831
	s->dac_read_index = val;
2832
	s->dac_sub_index = 0;
2833
	s->dac_state = 3;
2831
	s->vga.dac_read_index = val;
2832
	s->vga.dac_sub_index = 0;
2833
	s->vga.dac_state = 3;
2834 2834
	break;
2835 2835
    case 0x3c8:
2836
	s->dac_write_index = val;
2837
	s->dac_sub_index = 0;
2838
	s->dac_state = 0;
2836
	s->vga.dac_write_index = val;
2837
	s->vga.dac_sub_index = 0;
2838
	s->vga.dac_state = 0;
2839 2839
	break;
2840 2840
    case 0x3c9:
2841 2841
	if (cirrus_hook_write_palette(s, val))
2842 2842
	    break;
2843
	s->dac_cache[s->dac_sub_index] = val;
2844
	if (++s->dac_sub_index == 3) {
2845
	    memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2846
	    s->dac_sub_index = 0;
2847
	    s->dac_write_index++;
2843
	s->vga.dac_cache[s->vga.dac_sub_index] = val;
2844
	if (++s->vga.dac_sub_index == 3) {
2845
	    memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
2846
	    s->vga.dac_sub_index = 0;
2847
	    s->vga.dac_write_index++;
2848 2848
	}
2849 2849
	break;
2850 2850
    case 0x3ce:
2851
	s->gr_index = val;
2851
	s->vga.gr_index = val;
2852 2852
	break;
2853 2853
    case 0x3cf:
2854
	if (cirrus_hook_write_gr(s, s->gr_index, val))
2854
	if (cirrus_hook_write_gr(s, s->vga.gr_index, val))
2855 2855
	    break;
2856 2856
#ifdef DEBUG_VGA_REG
2857
	printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2857
	printf("vga: write GR%x = 0x%02x\n", s->vga.gr_index, val);
2858 2858
#endif
2859
	s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2859
	s->vga.gr[s->vga.gr_index] = val & gr_mask[s->vga.gr_index];
2860 2860
	break;
2861 2861
    case 0x3b4:
2862 2862
    case 0x3d4:
2863
	s->cr_index = val;
2863
	s->vga.cr_index = val;
2864 2864
	break;
2865 2865
    case 0x3b5:
2866 2866
    case 0x3d5:
2867
	if (cirrus_hook_write_cr(s, s->cr_index, val))
2867
	if (cirrus_hook_write_cr(s, s->vga.cr_index, val))
2868 2868
	    break;
2869 2869
#ifdef DEBUG_VGA_REG
2870
	printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2870
	printf("vga: write CR%x = 0x%02x\n", s->vga.cr_index, val);
2871 2871
#endif
2872 2872
	/* handle CR0-7 protection */
2873
	if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2873
	if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
2874 2874
	    /* can always write bit 4 of CR7 */
2875
	    if (s->cr_index == 7)
2876
		s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2875
	    if (s->vga.cr_index == 7)
2876
		s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (val & 0x10);
2877 2877
	    return;
2878 2878
	}
2879
	switch (s->cr_index) {
2879
	switch (s->vga.cr_index) {
2880 2880
	case 0x01:		/* horizontal display end */
2881 2881
	case 0x07:
2882 2882
	case 0x09:
2883 2883
	case 0x0c:
2884 2884
	case 0x0d:
2885 2885
	case 0x12:		/* vertical display end */
2886
	    s->cr[s->cr_index] = val;
2886
	    s->vga.cr[s->vga.cr_index] = val;
2887 2887
	    break;
2888 2888

  
2889 2889
	default:
2890
	    s->cr[s->cr_index] = val;
2890
	    s->vga.cr[s->vga.cr_index] = val;
2891 2891
	    break;
2892 2892
	}
2893 2893

  
2894
	switch(s->cr_index) {
2894
	switch(s->vga.cr_index) {
2895 2895
	case 0x00:
2896 2896
	case 0x04:
2897 2897
	case 0x05:
......
2899 2899
	case 0x07:
2900 2900
	case 0x11:
2901 2901
	case 0x17:
2902
	    s->update_retrace_info((VGAState *) s);
2902
	    s->vga.update_retrace_info(&s->vga);
2903 2903
	    break;
2904 2904
	}
2905 2905
	break;
2906 2906
    case 0x3ba:
2907 2907
    case 0x3da:
2908
	s->fcr = val & 0x10;
2908
	s->vga.fcr = val & 0x10;
2909 2909
	break;
2910 2910
    }
2911 2911
}
......
3020 3020
{
3021 3021
    CirrusVGAState *s = opaque;
3022 3022

  
3023
    if (s->pci_dev)
3024
        pci_device_save(s->pci_dev, f);
3023
    if (s->vga.pci_dev)
3024
        pci_device_save(s->vga.pci_dev, f);
3025 3025

  
3026
    qemu_put_be32s(f, &s->latch);
3027
    qemu_put_8s(f, &s->sr_index);
3028
    qemu_put_buffer(f, s->sr, 256);
3029
    qemu_put_8s(f, &s->gr_index);
3026
    qemu_put_be32s(f, &s->vga.latch);
3027
    qemu_put_8s(f, &s->vga.sr_index);
3028
    qemu_put_buffer(f, s->vga.sr, 256);
3029
    qemu_put_8s(f, &s->vga.gr_index);
3030 3030
    qemu_put_8s(f, &s->cirrus_shadow_gr0);
3031 3031
    qemu_put_8s(f, &s->cirrus_shadow_gr1);
3032
    qemu_put_buffer(f, s->gr + 2, 254);
3033
    qemu_put_8s(f, &s->ar_index);
3034
    qemu_put_buffer(f, s->ar, 21);
3035
    qemu_put_be32(f, s->ar_flip_flop);
3036
    qemu_put_8s(f, &s->cr_index);
3037
    qemu_put_buffer(f, s->cr, 256);
3038
    qemu_put_8s(f, &s->msr);
3039
    qemu_put_8s(f, &s->fcr);
3040
    qemu_put_8s(f, &s->st00);
3041
    qemu_put_8s(f, &s->st01);
3042

  
3043
    qemu_put_8s(f, &s->dac_state);
3044
    qemu_put_8s(f, &s->dac_sub_index);
3045
    qemu_put_8s(f, &s->dac_read_index);
3046
    qemu_put_8s(f, &s->dac_write_index);
3047
    qemu_put_buffer(f, s->dac_cache, 3);
3048
    qemu_put_buffer(f, s->palette, 768);
3049

  
3050
    qemu_put_be32(f, s->bank_offset);
3032
    qemu_put_buffer(f, s->vga.gr + 2, 254);
3033
    qemu_put_8s(f, &s->vga.ar_index);
3034
    qemu_put_buffer(f, s->vga.ar, 21);
3035
    qemu_put_be32(f, s->vga.ar_flip_flop);
3036
    qemu_put_8s(f, &s->vga.cr_index);
3037
    qemu_put_buffer(f, s->vga.cr, 256);
3038
    qemu_put_8s(f, &s->vga.msr);
3039
    qemu_put_8s(f, &s->vga.fcr);
3040
    qemu_put_8s(f, &s->vga.st00);
3041
    qemu_put_8s(f, &s->vga.st01);
3042

  
3043
    qemu_put_8s(f, &s->vga.dac_state);
3044
    qemu_put_8s(f, &s->vga.dac_sub_index);
3045
    qemu_put_8s(f, &s->vga.dac_read_index);
3046
    qemu_put_8s(f, &s->vga.dac_write_index);
3047
    qemu_put_buffer(f, s->vga.dac_cache, 3);
3048
    qemu_put_buffer(f, s->vga.palette, 768);
3049

  
3050
    qemu_put_be32(f, s->vga.bank_offset);
3051 3051

  
3052 3052
    qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3053 3053
    qemu_put_8s(f, &s->cirrus_hidden_dac_data);
......
3066 3066
    if (version_id > 2)
3067 3067
        return -EINVAL;
3068 3068

  
3069
    if (s->pci_dev && version_id >= 2) {
3070
        ret = pci_device_load(s->pci_dev, f);
3069
    if (s->vga.pci_dev && version_id >= 2) {
3070
        ret = pci_device_load(s->vga.pci_dev, f);
3071 3071
        if (ret < 0)
3072 3072
            return ret;
3073 3073
    }
3074 3074

  
3075
    qemu_get_be32s(f, &s->latch);
3076
    qemu_get_8s(f, &s->sr_index);
3077
    qemu_get_buffer(f, s->sr, 256);
3078
    qemu_get_8s(f, &s->gr_index);
3075
    qemu_get_be32s(f, &s->vga.latch);
3076
    qemu_get_8s(f, &s->vga.sr_index);
3077
    qemu_get_buffer(f, s->vga.sr, 256);
3078
    qemu_get_8s(f, &s->vga.gr_index);
3079 3079
    qemu_get_8s(f, &s->cirrus_shadow_gr0);
3080 3080
    qemu_get_8s(f, &s->cirrus_shadow_gr1);
3081
    s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3082
    s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3083
    qemu_get_buffer(f, s->gr + 2, 254);
3084
    qemu_get_8s(f, &s->ar_index);
3085
    qemu_get_buffer(f, s->ar, 21);
3086
    s->ar_flip_flop=qemu_get_be32(f);
3087
    qemu_get_8s(f, &s->cr_index);
3088
    qemu_get_buffer(f, s->cr, 256);
3089
    qemu_get_8s(f, &s->msr);
3090
    qemu_get_8s(f, &s->fcr);
3091
    qemu_get_8s(f, &s->st00);
3092
    qemu_get_8s(f, &s->st01);
3093

  
3094
    qemu_get_8s(f, &s->dac_state);
3095
    qemu_get_8s(f, &s->dac_sub_index);
3096
    qemu_get_8s(f, &s->dac_read_index);
3097
    qemu_get_8s(f, &s->dac_write_index);
3098
    qemu_get_buffer(f, s->dac_cache, 3);
3099
    qemu_get_buffer(f, s->palette, 768);
3100

  
3101
    s->bank_offset=qemu_get_be32(f);
3081
    s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3082
    s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3083
    qemu_get_buffer(f, s->vga.gr + 2, 254);
3084
    qemu_get_8s(f, &s->vga.ar_index);
3085
    qemu_get_buffer(f, s->vga.ar, 21);
3086
    s->vga.ar_flip_flop=qemu_get_be32(f);
3087
    qemu_get_8s(f, &s->vga.cr_index);
3088
    qemu_get_buffer(f, s->vga.cr, 256);
3089
    qemu_get_8s(f, &s->vga.msr);
3090
    qemu_get_8s(f, &s->vga.fcr);
3091
    qemu_get_8s(f, &s->vga.st00);
3092
    qemu_get_8s(f, &s->vga.st01);
3093

  
3094
    qemu_get_8s(f, &s->vga.dac_state);
3095
    qemu_get_8s(f, &s->vga.dac_sub_index);
3096
    qemu_get_8s(f, &s->vga.dac_read_index);
3097
    qemu_get_8s(f, &s->vga.dac_write_index);
3098
    qemu_get_buffer(f, s->vga.dac_cache, 3);
3099
    qemu_get_buffer(f, s->vga.palette, 768);
3100

  
3101
    s->vga.bank_offset = qemu_get_be32(f);
3102 3102

  
3103 3103
    qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3104 3104
    qemu_get_8s(f, &s->cirrus_hidden_dac_data);
......
3108 3108

  
3109 3109
    cirrus_update_memory_access(s);
3110 3110
    /* force refresh */
3111
    s->graphic_mode = -1;
3111
    s->vga.graphic_mode = -1;
3112 3112
    cirrus_update_bank_ptr(s, 0);
3113 3113
    cirrus_update_bank_ptr(s, 1);
3114 3114
    return 0;
......
3126 3126

  
3127 3127
    vga_reset(s);
3128 3128
    unmap_linear_vram(s);
3129
    s->sr[0x06] = 0x0f;
3129
    s->vga.sr[0x06] = 0x0f;
3130 3130
    if (s->device_id == CIRRUS_ID_CLGD5446) {
3131 3131
        /* 4MB 64 bit memory config, always PCI */
3132
        s->sr[0x1F] = 0x2d;		// MemClock
3133
        s->gr[0x18] = 0x0f;             // fastest memory configuration
3134
        s->sr[0x0f] = 0x98;
3135
        s->sr[0x17] = 0x20;
3136
        s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3132
        s->vga.sr[0x1F] = 0x2d;		// MemClock
3133
        s->vga.gr[0x18] = 0x0f;             // fastest memory configuration
3134
        s->vga.sr[0x0f] = 0x98;
3135
        s->vga.sr[0x17] = 0x20;
3136
        s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3137 3137
    } else {
3138
        s->sr[0x1F] = 0x22;		// MemClock
3139
        s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3140
        s->sr[0x17] = s->bustype;
3141
        s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3138
        s->vga.sr[0x1F] = 0x22;		// MemClock
3139
        s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
3140
        s->vga.sr[0x17] = s->bustype;
3141
        s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3142 3142
    }
3143
    s->cr[0x27] = s->device_id;
3143
    s->vga.cr[0x27] = s->device_id;
3144 3144

  
3145 3145
    /* Win2K seems to assume that the pattern buffer is at 0xff
3146 3146
       initially ! */
3147
    memset(s->vram_ptr, 0xff, s->real_vram_size);
3147
    memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
3148 3148

  
3149 3149
    s->cirrus_hidden_dac_lockindex = 5;
3150 3150
    s->cirrus_hidden_dac_data = 0;
......
3196 3196
    register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3197 3197
    register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3198 3198

  
3199
    s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3200
                                           cirrus_vga_mem_write, s);
3199
    s->vga.vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3200
                                                  cirrus_vga_mem_write, s);
3201 3201
    cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3202
                                 s->vga_io_memory);
3202
                                 s->vga.vga_io_memory);
3203 3203
    qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3204 3204

  
3205 3205
    /* I/O handler for LFB */
......
3218 3218
    s->real_vram_size =
3219 3219
        (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3220 3220

  
3221
    /* XXX: s->vram_size must be a power of two */
3221
    /* XXX: s->vga.vram_size must be a power of two */
3222 3222
    s->cirrus_addr_mask = s->real_vram_size - 1;
3223 3223
    s->linear_mmio_mask = s->real_vram_size - 256;
3224 3224

  
3225
    s->get_bpp = cirrus_get_bpp;
3226
    s->get_offsets = cirrus_get_offsets;
3227
    s->get_resolution = cirrus_get_resolution;
3228
    s->cursor_invalidate = cirrus_cursor_invalidate;
3229
    s->cursor_draw_line = cirrus_cursor_draw_line;
3225
    s->vga.get_bpp = cirrus_get_bpp;
3226
    s->vga.get_offsets = cirrus_get_offsets;
3227
    s->vga.get_resolution = cirrus_get_resolution;
3228
    s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3229
    s->vga.cursor_draw_line = cirrus_cursor_draw_line;
3230 3230

  
3231 3231
    qemu_register_reset(cirrus_reset, s);
3232 3232
    cirrus_reset(s);
......
3245 3245

  
3246 3246
    s = qemu_mallocz(sizeof(CirrusVGAState));
3247 3247

  
3248
    vga_common_init((VGAState *)s, vga_ram_size);
3248
    vga_common_init(&s->vga, vga_ram_size);
3249 3249
    cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3250
    s->ds = graphic_console_init(s->update, s->invalidate,
3251
                                 s->screen_dump, s->text_update, s);
3250
    s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3251
                                     s->vga.screen_dump, s->vga.text_update,
3252
                                     &s->vga);
3252 3253
    /* XXX ISA-LFB support */
3253 3254
}
3254 3255

  
......
3264 3265
    CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3265 3266

  
3266 3267
    /* XXX: add byte swapping apertures */
3267
    cpu_register_physical_memory(addr, s->vram_size,
3268
    cpu_register_physical_memory(addr, s->vga.vram_size,
3268 3269
				 s->cirrus_linear_io_addr);
3269 3270
    cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3270 3271
				 s->cirrus_linear_bitblt_io_addr);
3271 3272

  
3272
    s->map_addr = s->map_end = 0;
3273
    s->lfb_addr = addr & TARGET_PAGE_MASK;
3274
    s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3273
    s->vga.map_addr = s->vga.map_end = 0;
3274
    s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3275
    s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
... This diff was truncated because it exceeds the maximum size that can be displayed.

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