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/*
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 * QEMU Cirrus CLGD 54xx VGA Emulator.
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 *
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 * Copyright (c) 2004 Fabrice Bellard
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 * Copyright (c) 2004 Makoto Suzuki (suzu)
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * Reference: Finn Thogersons' VGADOC4b
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 *   available at http://home.worldonline.dk/~finth/
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 */
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "console.h"
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#include "vga_int.h"
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#include "kvm.h"
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/*
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 * TODO:
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 *    - destination write mask support not complete (bits 5..7)
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 *    - optimize linear mappings
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 *    - optimize bitblt functions
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 */
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//#define DEBUG_CIRRUS
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//#define DEBUG_BITBLT
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/***************************************
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 *
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 *  definitions
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 *
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 ***************************************/
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// ID
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#define CIRRUS_ID_CLGD5422  (0x23<<2)
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#define CIRRUS_ID_CLGD5426  (0x24<<2)
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#define CIRRUS_ID_CLGD5424  (0x25<<2)
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#define CIRRUS_ID_CLGD5428  (0x26<<2)
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#define CIRRUS_ID_CLGD5430  (0x28<<2)
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#define CIRRUS_ID_CLGD5434  (0x2A<<2)
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#define CIRRUS_ID_CLGD5436  (0x2B<<2)
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#define CIRRUS_ID_CLGD5446  (0x2E<<2)
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// sequencer 0x07
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#define CIRRUS_SR7_BPP_VGA            0x00
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#define CIRRUS_SR7_BPP_SVGA           0x01
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#define CIRRUS_SR7_BPP_MASK           0x0e
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#define CIRRUS_SR7_BPP_8              0x00
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#define CIRRUS_SR7_BPP_16_DOUBLEVCLK  0x02
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#define CIRRUS_SR7_BPP_24             0x04
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#define CIRRUS_SR7_BPP_16             0x06
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#define CIRRUS_SR7_BPP_32             0x08
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#define CIRRUS_SR7_ISAADDR_MASK       0xe0
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// sequencer 0x0f
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#define CIRRUS_MEMSIZE_512k        0x08
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#define CIRRUS_MEMSIZE_1M          0x10
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#define CIRRUS_MEMSIZE_2M          0x18
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#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80        // bank switching is enabled.
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// sequencer 0x12
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#define CIRRUS_CURSOR_SHOW         0x01
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#define CIRRUS_CURSOR_HIDDENPEL    0x02
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#define CIRRUS_CURSOR_LARGE        0x04        // 64x64 if set, 32x32 if clear
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// sequencer 0x17
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#define CIRRUS_BUSTYPE_VLBFAST   0x10
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#define CIRRUS_BUSTYPE_PCI       0x20
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#define CIRRUS_BUSTYPE_VLBSLOW   0x30
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#define CIRRUS_BUSTYPE_ISA       0x38
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#define CIRRUS_MMIO_ENABLE       0x04
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#define CIRRUS_MMIO_USE_PCIADDR  0x40        // 0xb8000 if cleared.
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#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
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// control 0x0b
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#define CIRRUS_BANKING_DUAL             0x01
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#define CIRRUS_BANKING_GRANULARITY_16K  0x20        // set:16k, clear:4k
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// control 0x30
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#define CIRRUS_BLTMODE_BACKWARDS        0x01
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#define CIRRUS_BLTMODE_MEMSYSDEST       0x02
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#define CIRRUS_BLTMODE_MEMSYSSRC        0x04
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#define CIRRUS_BLTMODE_TRANSPARENTCOMP  0x08
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#define CIRRUS_BLTMODE_PATTERNCOPY      0x40
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#define CIRRUS_BLTMODE_COLOREXPAND      0x80
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#define CIRRUS_BLTMODE_PIXELWIDTHMASK   0x30
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#define CIRRUS_BLTMODE_PIXELWIDTH8      0x00
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#define CIRRUS_BLTMODE_PIXELWIDTH16     0x10
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#define CIRRUS_BLTMODE_PIXELWIDTH24     0x20
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#define CIRRUS_BLTMODE_PIXELWIDTH32     0x30
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// control 0x31
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#define CIRRUS_BLT_BUSY                 0x01
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#define CIRRUS_BLT_START                0x02
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#define CIRRUS_BLT_RESET                0x04
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#define CIRRUS_BLT_FIFOUSED             0x10
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#define CIRRUS_BLT_AUTOSTART            0x80
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// control 0x32
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#define CIRRUS_ROP_0                    0x00
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#define CIRRUS_ROP_SRC_AND_DST          0x05
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#define CIRRUS_ROP_NOP                  0x06
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#define CIRRUS_ROP_SRC_AND_NOTDST       0x09
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#define CIRRUS_ROP_NOTDST               0x0b
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#define CIRRUS_ROP_SRC                  0x0d
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#define CIRRUS_ROP_1                    0x0e
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#define CIRRUS_ROP_NOTSRC_AND_DST       0x50
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#define CIRRUS_ROP_SRC_XOR_DST          0x59
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#define CIRRUS_ROP_SRC_OR_DST           0x6d
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#define CIRRUS_ROP_NOTSRC_OR_NOTDST     0x90
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#define CIRRUS_ROP_SRC_NOTXOR_DST       0x95
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#define CIRRUS_ROP_SRC_OR_NOTDST        0xad
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#define CIRRUS_ROP_NOTSRC               0xd0
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#define CIRRUS_ROP_NOTSRC_OR_DST        0xd6
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#define CIRRUS_ROP_NOTSRC_AND_NOTDST    0xda
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#define CIRRUS_ROP_NOP_INDEX 2
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#define CIRRUS_ROP_SRC_INDEX 5
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// control 0x33
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#define CIRRUS_BLTMODEEXT_SOLIDFILL        0x04
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#define CIRRUS_BLTMODEEXT_COLOREXPINV      0x02
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#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
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// memory-mapped IO
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#define CIRRUS_MMIO_BLTBGCOLOR        0x00        // dword
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#define CIRRUS_MMIO_BLTFGCOLOR        0x04        // dword
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#define CIRRUS_MMIO_BLTWIDTH          0x08        // word
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#define CIRRUS_MMIO_BLTHEIGHT         0x0a        // word
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#define CIRRUS_MMIO_BLTDESTPITCH      0x0c        // word
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#define CIRRUS_MMIO_BLTSRCPITCH       0x0e        // word
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#define CIRRUS_MMIO_BLTDESTADDR       0x10        // dword
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#define CIRRUS_MMIO_BLTSRCADDR        0x14        // dword
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#define CIRRUS_MMIO_BLTWRITEMASK      0x17        // byte
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#define CIRRUS_MMIO_BLTMODE           0x18        // byte
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#define CIRRUS_MMIO_BLTROP            0x1a        // byte
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#define CIRRUS_MMIO_BLTMODEEXT        0x1b        // byte
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c        // word?
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20        // word?
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#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24        // word
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#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26        // word
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#define CIRRUS_MMIO_LINEARDRAW_END_X  0x28        // word
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#define CIRRUS_MMIO_LINEARDRAW_END_Y  0x2a        // word
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f        // byte
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#define CIRRUS_MMIO_BRESENHAM_K1      0x30        // word
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#define CIRRUS_MMIO_BRESENHAM_K3      0x32        // word
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#define CIRRUS_MMIO_BRESENHAM_ERROR   0x34        // word
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#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36        // word
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#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38        // byte
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#define CIRRUS_MMIO_LINEDRAW_MODE     0x39        // byte
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#define CIRRUS_MMIO_BLTSTATUS         0x40        // byte
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// PCI 0x04: command(word), 0x06(word): status
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#define PCI_COMMAND_IOACCESS                0x0001
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#define PCI_COMMAND_MEMACCESS               0x0002
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#define PCI_COMMAND_BUSMASTER               0x0004
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#define PCI_COMMAND_SPECIALCYCLE            0x0008
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#define PCI_COMMAND_MEMWRITEINVALID         0x0010
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#define PCI_COMMAND_PALETTESNOOPING         0x0020
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#define PCI_COMMAND_PARITYDETECTION         0x0040
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#define PCI_COMMAND_ADDRESSDATASTEPPING     0x0080
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#define PCI_COMMAND_SERR                    0x0100
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#define PCI_COMMAND_BACKTOBACKTRANS         0x0200
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// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
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#define PCI_CLASS_BASE_DISPLAY        0x03
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// PCI 0x08, 0x00ff0000
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#define PCI_CLASS_SUB_VGA             0x00
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// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
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// 0x10-0x3f (headertype 00h)
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// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
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//   0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
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#define PCI_MAP_MEM                 0x0
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#define PCI_MAP_IO                  0x1
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#define PCI_MAP_MEM_ADDR_MASK       (~0xf)
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#define PCI_MAP_IO_ADDR_MASK        (~0x3)
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#define PCI_MAP_MEMFLAGS_32BIT      0x0
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#define PCI_MAP_MEMFLAGS_32BIT_1M   0x1
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#define PCI_MAP_MEMFLAGS_64BIT      0x4
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#define PCI_MAP_MEMFLAGS_CACHEABLE  0x8
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// PCI 0x28: cardbus CIS pointer
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// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
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// PCI 0x30: expansion ROM base address
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#define PCI_ROMBIOS_ENABLED         0x1
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// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
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// PCI 0x38: reserved
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// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
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#define CIRRUS_PNPMMIO_SIZE         0x1000
210

    
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/* I/O and memory hook */
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#define CIRRUS_HOOK_NOT_HANDLED 0
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#define CIRRUS_HOOK_HANDLED 1
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#define ABS(a) ((signed)(a) > 0 ? a : -a)
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#define BLTUNSAFE(s) \
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    ( \
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        ( /* check dst is within bounds */ \
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            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
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                + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
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                    (s)->vga.vram_size \
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        ) || \
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        ( /* check src is within bounds */ \
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            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
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                + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
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                    (s)->vga.vram_size \
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        ) \
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    )
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struct CirrusVGAState;
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typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
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                                     uint8_t * dst, const uint8_t * src,
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                                     int dstpitch, int srcpitch,
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                                     int bltwidth, int bltheight);
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typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
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                              uint8_t *dst, int dst_pitch, int width, int height);
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240
typedef struct CirrusVGAState {
241
    VGACommonState vga;
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    int cirrus_linear_io_addr;
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    int cirrus_linear_bitblt_io_addr;
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    int cirrus_mmio_io_addr;
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    uint32_t cirrus_addr_mask;
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    uint32_t linear_mmio_mask;
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    uint8_t cirrus_shadow_gr0;
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    uint8_t cirrus_shadow_gr1;
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    uint8_t cirrus_hidden_dac_lockindex;
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    uint8_t cirrus_hidden_dac_data;
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    uint32_t cirrus_bank_base[2];
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    uint32_t cirrus_bank_limit[2];
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    uint8_t cirrus_hidden_palette[48];
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    uint32_t hw_cursor_x;
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    uint32_t hw_cursor_y;
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    int cirrus_blt_pixelwidth;
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    int cirrus_blt_width;
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    int cirrus_blt_height;
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    int cirrus_blt_dstpitch;
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    int cirrus_blt_srcpitch;
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    uint32_t cirrus_blt_fgcol;
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    uint32_t cirrus_blt_bgcol;
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    uint32_t cirrus_blt_dstaddr;
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    uint32_t cirrus_blt_srcaddr;
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    uint8_t cirrus_blt_mode;
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    uint8_t cirrus_blt_modeext;
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    cirrus_bitblt_rop_t cirrus_rop;
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#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
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    uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
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    uint8_t *cirrus_srcptr;
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    uint8_t *cirrus_srcptr_end;
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    uint32_t cirrus_srccounter;
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    /* hwcursor display state */
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    int last_hw_cursor_size;
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    int last_hw_cursor_x;
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    int last_hw_cursor_y;
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    int last_hw_cursor_y_start;
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    int last_hw_cursor_y_end;
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    int real_vram_size; /* XXX: suppress that */
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    int device_id;
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    int bustype;
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} CirrusVGAState;
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285
typedef struct PCICirrusVGAState {
286
    PCIDevice dev;
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    CirrusVGAState cirrus_vga;
288
} PCICirrusVGAState;
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static uint8_t rop_to_index[256];
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/***************************************
293
 *
294
 *  prototypes.
295
 *
296
 ***************************************/
297

    
298

    
299
static void cirrus_bitblt_reset(CirrusVGAState *s);
300
static void cirrus_update_memory_access(CirrusVGAState *s);
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302
/***************************************
303
 *
304
 *  raster operations
305
 *
306
 ***************************************/
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308
static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
309
                                  uint8_t *dst,const uint8_t *src,
310
                                  int dstpitch,int srcpitch,
311
                                  int bltwidth,int bltheight)
312
{
313
}
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315
static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
316
                                   uint8_t *dst,
317
                                   int dstpitch, int bltwidth,int bltheight)
318
{
319
}
320

    
321
#define ROP_NAME 0
322
#define ROP_OP(d, s) d = 0
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#include "cirrus_vga_rop.h"
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#define ROP_NAME src_and_dst
326
#define ROP_OP(d, s) d = (s) & (d)
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#include "cirrus_vga_rop.h"
328

    
329
#define ROP_NAME src_and_notdst
330
#define ROP_OP(d, s) d = (s) & (~(d))
331
#include "cirrus_vga_rop.h"
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333
#define ROP_NAME notdst
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#define ROP_OP(d, s) d = ~(d)
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#include "cirrus_vga_rop.h"
336

    
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#define ROP_NAME src
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#define ROP_OP(d, s) d = s
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#include "cirrus_vga_rop.h"
340

    
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#define ROP_NAME 1
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#define ROP_OP(d, s) d = ~0
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#include "cirrus_vga_rop.h"
344

    
345
#define ROP_NAME notsrc_and_dst
346
#define ROP_OP(d, s) d = (~(s)) & (d)
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#include "cirrus_vga_rop.h"
348

    
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#define ROP_NAME src_xor_dst
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#define ROP_OP(d, s) d = (s) ^ (d)
351
#include "cirrus_vga_rop.h"
352

    
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#define ROP_NAME src_or_dst
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#define ROP_OP(d, s) d = (s) | (d)
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#include "cirrus_vga_rop.h"
356

    
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#define ROP_NAME notsrc_or_notdst
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#define ROP_OP(d, s) d = (~(s)) | (~(d))
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#include "cirrus_vga_rop.h"
360

    
361
#define ROP_NAME src_notxor_dst
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#define ROP_OP(d, s) d = ~((s) ^ (d))
363
#include "cirrus_vga_rop.h"
364

    
365
#define ROP_NAME src_or_notdst
366
#define ROP_OP(d, s) d = (s) | (~(d))
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#include "cirrus_vga_rop.h"
368

    
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#define ROP_NAME notsrc
370
#define ROP_OP(d, s) d = (~(s))
371
#include "cirrus_vga_rop.h"
372

    
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#define ROP_NAME notsrc_or_dst
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#define ROP_OP(d, s) d = (~(s)) | (d)
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#include "cirrus_vga_rop.h"
376

    
377
#define ROP_NAME notsrc_and_notdst
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#define ROP_OP(d, s) d = (~(s)) & (~(d))
379
#include "cirrus_vga_rop.h"
380

    
381
static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
382
    cirrus_bitblt_rop_fwd_0,
383
    cirrus_bitblt_rop_fwd_src_and_dst,
384
    cirrus_bitblt_rop_nop,
385
    cirrus_bitblt_rop_fwd_src_and_notdst,
386
    cirrus_bitblt_rop_fwd_notdst,
387
    cirrus_bitblt_rop_fwd_src,
388
    cirrus_bitblt_rop_fwd_1,
389
    cirrus_bitblt_rop_fwd_notsrc_and_dst,
390
    cirrus_bitblt_rop_fwd_src_xor_dst,
391
    cirrus_bitblt_rop_fwd_src_or_dst,
392
    cirrus_bitblt_rop_fwd_notsrc_or_notdst,
393
    cirrus_bitblt_rop_fwd_src_notxor_dst,
394
    cirrus_bitblt_rop_fwd_src_or_notdst,
395
    cirrus_bitblt_rop_fwd_notsrc,
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    cirrus_bitblt_rop_fwd_notsrc_or_dst,
397
    cirrus_bitblt_rop_fwd_notsrc_and_notdst,
398
};
399

    
400
static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
401
    cirrus_bitblt_rop_bkwd_0,
402
    cirrus_bitblt_rop_bkwd_src_and_dst,
403
    cirrus_bitblt_rop_nop,
404
    cirrus_bitblt_rop_bkwd_src_and_notdst,
405
    cirrus_bitblt_rop_bkwd_notdst,
406
    cirrus_bitblt_rop_bkwd_src,
407
    cirrus_bitblt_rop_bkwd_1,
408
    cirrus_bitblt_rop_bkwd_notsrc_and_dst,
409
    cirrus_bitblt_rop_bkwd_src_xor_dst,
410
    cirrus_bitblt_rop_bkwd_src_or_dst,
411
    cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
412
    cirrus_bitblt_rop_bkwd_src_notxor_dst,
413
    cirrus_bitblt_rop_bkwd_src_or_notdst,
414
    cirrus_bitblt_rop_bkwd_notsrc,
415
    cirrus_bitblt_rop_bkwd_notsrc_or_dst,
416
    cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
417
};
418

    
419
#define TRANSP_ROP(name) {\
420
    name ## _8,\
421
    name ## _16,\
422
        }
423
#define TRANSP_NOP(func) {\
424
    func,\
425
    func,\
426
        }
427

    
428
static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
429
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
430
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
431
    TRANSP_NOP(cirrus_bitblt_rop_nop),
432
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
433
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
434
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
435
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
436
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
437
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
438
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
439
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
440
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
441
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
442
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
443
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
444
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
445
};
446

    
447
static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
448
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
449
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
450
    TRANSP_NOP(cirrus_bitblt_rop_nop),
451
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
452
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
453
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
454
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
455
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
456
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
457
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
458
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
459
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
460
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
461
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
462
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
463
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
464
};
465

    
466
#define ROP2(name) {\
467
    name ## _8,\
468
    name ## _16,\
469
    name ## _24,\
470
    name ## _32,\
471
        }
472

    
473
#define ROP_NOP2(func) {\
474
    func,\
475
    func,\
476
    func,\
477
    func,\
478
        }
479

    
480
static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
481
    ROP2(cirrus_patternfill_0),
482
    ROP2(cirrus_patternfill_src_and_dst),
483
    ROP_NOP2(cirrus_bitblt_rop_nop),
484
    ROP2(cirrus_patternfill_src_and_notdst),
485
    ROP2(cirrus_patternfill_notdst),
486
    ROP2(cirrus_patternfill_src),
487
    ROP2(cirrus_patternfill_1),
488
    ROP2(cirrus_patternfill_notsrc_and_dst),
489
    ROP2(cirrus_patternfill_src_xor_dst),
490
    ROP2(cirrus_patternfill_src_or_dst),
491
    ROP2(cirrus_patternfill_notsrc_or_notdst),
492
    ROP2(cirrus_patternfill_src_notxor_dst),
493
    ROP2(cirrus_patternfill_src_or_notdst),
494
    ROP2(cirrus_patternfill_notsrc),
495
    ROP2(cirrus_patternfill_notsrc_or_dst),
496
    ROP2(cirrus_patternfill_notsrc_and_notdst),
497
};
498

    
499
static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
500
    ROP2(cirrus_colorexpand_transp_0),
501
    ROP2(cirrus_colorexpand_transp_src_and_dst),
502
    ROP_NOP2(cirrus_bitblt_rop_nop),
503
    ROP2(cirrus_colorexpand_transp_src_and_notdst),
504
    ROP2(cirrus_colorexpand_transp_notdst),
505
    ROP2(cirrus_colorexpand_transp_src),
506
    ROP2(cirrus_colorexpand_transp_1),
507
    ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
508
    ROP2(cirrus_colorexpand_transp_src_xor_dst),
509
    ROP2(cirrus_colorexpand_transp_src_or_dst),
510
    ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
511
    ROP2(cirrus_colorexpand_transp_src_notxor_dst),
512
    ROP2(cirrus_colorexpand_transp_src_or_notdst),
513
    ROP2(cirrus_colorexpand_transp_notsrc),
514
    ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
515
    ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
516
};
517

    
518
static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
519
    ROP2(cirrus_colorexpand_0),
520
    ROP2(cirrus_colorexpand_src_and_dst),
521
    ROP_NOP2(cirrus_bitblt_rop_nop),
522
    ROP2(cirrus_colorexpand_src_and_notdst),
523
    ROP2(cirrus_colorexpand_notdst),
524
    ROP2(cirrus_colorexpand_src),
525
    ROP2(cirrus_colorexpand_1),
526
    ROP2(cirrus_colorexpand_notsrc_and_dst),
527
    ROP2(cirrus_colorexpand_src_xor_dst),
528
    ROP2(cirrus_colorexpand_src_or_dst),
529
    ROP2(cirrus_colorexpand_notsrc_or_notdst),
530
    ROP2(cirrus_colorexpand_src_notxor_dst),
531
    ROP2(cirrus_colorexpand_src_or_notdst),
532
    ROP2(cirrus_colorexpand_notsrc),
533
    ROP2(cirrus_colorexpand_notsrc_or_dst),
534
    ROP2(cirrus_colorexpand_notsrc_and_notdst),
535
};
536

    
537
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
538
    ROP2(cirrus_colorexpand_pattern_transp_0),
539
    ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
540
    ROP_NOP2(cirrus_bitblt_rop_nop),
541
    ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
542
    ROP2(cirrus_colorexpand_pattern_transp_notdst),
543
    ROP2(cirrus_colorexpand_pattern_transp_src),
544
    ROP2(cirrus_colorexpand_pattern_transp_1),
545
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
546
    ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
547
    ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
548
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
549
    ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
550
    ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
551
    ROP2(cirrus_colorexpand_pattern_transp_notsrc),
552
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
553
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
554
};
555

    
556
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
557
    ROP2(cirrus_colorexpand_pattern_0),
558
    ROP2(cirrus_colorexpand_pattern_src_and_dst),
559
    ROP_NOP2(cirrus_bitblt_rop_nop),
560
    ROP2(cirrus_colorexpand_pattern_src_and_notdst),
561
    ROP2(cirrus_colorexpand_pattern_notdst),
562
    ROP2(cirrus_colorexpand_pattern_src),
563
    ROP2(cirrus_colorexpand_pattern_1),
564
    ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
565
    ROP2(cirrus_colorexpand_pattern_src_xor_dst),
566
    ROP2(cirrus_colorexpand_pattern_src_or_dst),
567
    ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
568
    ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
569
    ROP2(cirrus_colorexpand_pattern_src_or_notdst),
570
    ROP2(cirrus_colorexpand_pattern_notsrc),
571
    ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
572
    ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
573
};
574

    
575
static const cirrus_fill_t cirrus_fill[16][4] = {
576
    ROP2(cirrus_fill_0),
577
    ROP2(cirrus_fill_src_and_dst),
578
    ROP_NOP2(cirrus_bitblt_fill_nop),
579
    ROP2(cirrus_fill_src_and_notdst),
580
    ROP2(cirrus_fill_notdst),
581
    ROP2(cirrus_fill_src),
582
    ROP2(cirrus_fill_1),
583
    ROP2(cirrus_fill_notsrc_and_dst),
584
    ROP2(cirrus_fill_src_xor_dst),
585
    ROP2(cirrus_fill_src_or_dst),
586
    ROP2(cirrus_fill_notsrc_or_notdst),
587
    ROP2(cirrus_fill_src_notxor_dst),
588
    ROP2(cirrus_fill_src_or_notdst),
589
    ROP2(cirrus_fill_notsrc),
590
    ROP2(cirrus_fill_notsrc_or_dst),
591
    ROP2(cirrus_fill_notsrc_and_notdst),
592
};
593

    
594
static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
595
{
596
    unsigned int color;
597
    switch (s->cirrus_blt_pixelwidth) {
598
    case 1:
599
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
600
        break;
601
    case 2:
602
        color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
603
        s->cirrus_blt_fgcol = le16_to_cpu(color);
604
        break;
605
    case 3:
606
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
607
            (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
608
        break;
609
    default:
610
    case 4:
611
        color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
612
            (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
613
        s->cirrus_blt_fgcol = le32_to_cpu(color);
614
        break;
615
    }
616
}
617

    
618
static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
619
{
620
    unsigned int color;
621
    switch (s->cirrus_blt_pixelwidth) {
622
    case 1:
623
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
624
        break;
625
    case 2:
626
        color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
627
        s->cirrus_blt_bgcol = le16_to_cpu(color);
628
        break;
629
    case 3:
630
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
631
            (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
632
        break;
633
    default:
634
    case 4:
635
        color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
636
            (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
637
        s->cirrus_blt_bgcol = le32_to_cpu(color);
638
        break;
639
    }
640
}
641

    
642
static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
643
                                     int off_pitch, int bytesperline,
644
                                     int lines)
645
{
646
    int y;
647
    int off_cur;
648
    int off_cur_end;
649

    
650
    for (y = 0; y < lines; y++) {
651
        off_cur = off_begin;
652
        off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
653
        off_cur &= TARGET_PAGE_MASK;
654
        while (off_cur < off_cur_end) {
655
            cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
656
            off_cur += TARGET_PAGE_SIZE;
657
        }
658
        off_begin += off_pitch;
659
    }
660
}
661

    
662
static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
663
                                            const uint8_t * src)
664
{
665
    uint8_t *dst;
666

    
667
    dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
668

    
669
    if (BLTUNSAFE(s))
670
        return 0;
671

    
672
    (*s->cirrus_rop) (s, dst, src,
673
                      s->cirrus_blt_dstpitch, 0,
674
                      s->cirrus_blt_width, s->cirrus_blt_height);
675
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
676
                             s->cirrus_blt_dstpitch, s->cirrus_blt_width,
677
                             s->cirrus_blt_height);
678
    return 1;
679
}
680

    
681
/* fill */
682

    
683
static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
684
{
685
    cirrus_fill_t rop_func;
686

    
687
    if (BLTUNSAFE(s))
688
        return 0;
689
    rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
690
    rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
691
             s->cirrus_blt_dstpitch,
692
             s->cirrus_blt_width, s->cirrus_blt_height);
693
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
694
                             s->cirrus_blt_dstpitch, s->cirrus_blt_width,
695
                             s->cirrus_blt_height);
696
    cirrus_bitblt_reset(s);
697
    return 1;
698
}
699

    
700
/***************************************
701
 *
702
 *  bitblt (video-to-video)
703
 *
704
 ***************************************/
705

    
706
static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
707
{
708
    return cirrus_bitblt_common_patterncopy(s,
709
                                            s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
710
                                            s->cirrus_addr_mask));
711
}
712

    
713
static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
714
{
715
    int sx, sy;
716
    int dx, dy;
717
    int width, height;
718
    int depth;
719
    int notify = 0;
720

    
721
    depth = s->vga.get_bpp(&s->vga) / 8;
722
    s->vga.get_resolution(&s->vga, &width, &height);
723

    
724
    /* extra x, y */
725
    sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
726
    sy = (src / ABS(s->cirrus_blt_srcpitch));
727
    dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
728
    dy = (dst / ABS(s->cirrus_blt_dstpitch));
729

    
730
    /* normalize width */
731
    w /= depth;
732

    
733
    /* if we're doing a backward copy, we have to adjust
734
       our x/y to be the upper left corner (instead of the lower
735
       right corner) */
736
    if (s->cirrus_blt_dstpitch < 0) {
737
        sx -= (s->cirrus_blt_width / depth) - 1;
738
        dx -= (s->cirrus_blt_width / depth) - 1;
739
        sy -= s->cirrus_blt_height - 1;
740
        dy -= s->cirrus_blt_height - 1;
741
    }
742

    
743
    /* are we in the visible portion of memory? */
744
    if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
745
        (sx + w) <= width && (sy + h) <= height &&
746
        (dx + w) <= width && (dy + h) <= height) {
747
        notify = 1;
748
    }
749

    
750
    /* make to sure only copy if it's a plain copy ROP */
751
    if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
752
        *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
753
        notify = 0;
754

    
755
    /* we have to flush all pending changes so that the copy
756
       is generated at the appropriate moment in time */
757
    if (notify)
758
        vga_hw_update();
759

    
760
    (*s->cirrus_rop) (s, s->vga.vram_ptr +
761
                      (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
762
                      s->vga.vram_ptr +
763
                      (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
764
                      s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
765
                      s->cirrus_blt_width, s->cirrus_blt_height);
766

    
767
    if (notify)
768
        qemu_console_copy(s->vga.ds,
769
                          sx, sy, dx, dy,
770
                          s->cirrus_blt_width / depth,
771
                          s->cirrus_blt_height);
772

    
773
    /* we don't have to notify the display that this portion has
774
       changed since qemu_console_copy implies this */
775

    
776
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
777
                                s->cirrus_blt_dstpitch, s->cirrus_blt_width,
778
                                s->cirrus_blt_height);
779
}
780

    
781
static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
782
{
783
    if (BLTUNSAFE(s))
784
        return 0;
785

    
786
    cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
787
            s->cirrus_blt_srcaddr - s->vga.start_addr,
788
            s->cirrus_blt_width, s->cirrus_blt_height);
789

    
790
    return 1;
791
}
792

    
793
/***************************************
794
 *
795
 *  bitblt (cpu-to-video)
796
 *
797
 ***************************************/
798

    
799
static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
800
{
801
    int copy_count;
802
    uint8_t *end_ptr;
803

    
804
    if (s->cirrus_srccounter > 0) {
805
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
806
            cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
807
        the_end:
808
            s->cirrus_srccounter = 0;
809
            cirrus_bitblt_reset(s);
810
        } else {
811
            /* at least one scan line */
812
            do {
813
                (*s->cirrus_rop)(s, s->vga.vram_ptr +
814
                                 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
815
                                  s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
816
                cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
817
                                         s->cirrus_blt_width, 1);
818
                s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
819
                s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
820
                if (s->cirrus_srccounter <= 0)
821
                    goto the_end;
822
                /* more bytes than needed can be transfered because of
823
                   word alignment, so we keep them for the next line */
824
                /* XXX: keep alignment to speed up transfer */
825
                end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
826
                copy_count = s->cirrus_srcptr_end - end_ptr;
827
                memmove(s->cirrus_bltbuf, end_ptr, copy_count);
828
                s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
829
                s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
830
            } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
831
        }
832
    }
833
}
834

    
835
/***************************************
836
 *
837
 *  bitblt wrapper
838
 *
839
 ***************************************/
840

    
841
static void cirrus_bitblt_reset(CirrusVGAState * s)
842
{
843
    int need_update;
844

    
845
    s->vga.gr[0x31] &=
846
        ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
847
    need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
848
        || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
849
    s->cirrus_srcptr = &s->cirrus_bltbuf[0];
850
    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
851
    s->cirrus_srccounter = 0;
852
    if (!need_update)
853
        return;
854
    cirrus_update_memory_access(s);
855
}
856

    
857
static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
858
{
859
    int w;
860

    
861
    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
862
    s->cirrus_srcptr = &s->cirrus_bltbuf[0];
863
    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
864

    
865
    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
866
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
867
            s->cirrus_blt_srcpitch = 8;
868
        } else {
869
            /* XXX: check for 24 bpp */
870
            s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
871
        }
872
        s->cirrus_srccounter = s->cirrus_blt_srcpitch;
873
    } else {
874
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
875
            w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
876
            if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
877
                s->cirrus_blt_srcpitch = ((w + 31) >> 5);
878
            else
879
                s->cirrus_blt_srcpitch = ((w + 7) >> 3);
880
        } else {
881
            /* always align input size to 32 bits */
882
            s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
883
        }
884
        s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
885
    }
886
    s->cirrus_srcptr = s->cirrus_bltbuf;
887
    s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
888
    cirrus_update_memory_access(s);
889
    return 1;
890
}
891

    
892
static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
893
{
894
    /* XXX */
895
#ifdef DEBUG_BITBLT
896
    printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
897
#endif
898
    return 0;
899
}
900

    
901
static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
902
{
903
    int ret;
904

    
905
    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
906
        ret = cirrus_bitblt_videotovideo_patterncopy(s);
907
    } else {
908
        ret = cirrus_bitblt_videotovideo_copy(s);
909
    }
910
    if (ret)
911
        cirrus_bitblt_reset(s);
912
    return ret;
913
}
914

    
915
static void cirrus_bitblt_start(CirrusVGAState * s)
916
{
917
    uint8_t blt_rop;
918

    
919
    s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
920

    
921
    s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
922
    s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
923
    s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
924
    s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
925
    s->cirrus_blt_dstaddr =
926
        (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
927
    s->cirrus_blt_srcaddr =
928
        (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
929
    s->cirrus_blt_mode = s->vga.gr[0x30];
930
    s->cirrus_blt_modeext = s->vga.gr[0x33];
931
    blt_rop = s->vga.gr[0x32];
932

    
933
#ifdef DEBUG_BITBLT
934
    printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
935
           blt_rop,
936
           s->cirrus_blt_mode,
937
           s->cirrus_blt_modeext,
938
           s->cirrus_blt_width,
939
           s->cirrus_blt_height,
940
           s->cirrus_blt_dstpitch,
941
           s->cirrus_blt_srcpitch,
942
           s->cirrus_blt_dstaddr,
943
           s->cirrus_blt_srcaddr,
944
           s->vga.gr[0x2f]);
945
#endif
946

    
947
    switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
948
    case CIRRUS_BLTMODE_PIXELWIDTH8:
949
        s->cirrus_blt_pixelwidth = 1;
950
        break;
951
    case CIRRUS_BLTMODE_PIXELWIDTH16:
952
        s->cirrus_blt_pixelwidth = 2;
953
        break;
954
    case CIRRUS_BLTMODE_PIXELWIDTH24:
955
        s->cirrus_blt_pixelwidth = 3;
956
        break;
957
    case CIRRUS_BLTMODE_PIXELWIDTH32:
958
        s->cirrus_blt_pixelwidth = 4;
959
        break;
960
    default:
961
#ifdef DEBUG_BITBLT
962
        printf("cirrus: bitblt - pixel width is unknown\n");
963
#endif
964
        goto bitblt_ignore;
965
    }
966
    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
967

    
968
    if ((s->
969
         cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
970
                            CIRRUS_BLTMODE_MEMSYSDEST))
971
        == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
972
#ifdef DEBUG_BITBLT
973
        printf("cirrus: bitblt - memory-to-memory copy is requested\n");
974
#endif
975
        goto bitblt_ignore;
976
    }
977

    
978
    if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
979
        (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
980
                               CIRRUS_BLTMODE_TRANSPARENTCOMP |
981
                               CIRRUS_BLTMODE_PATTERNCOPY |
982
                               CIRRUS_BLTMODE_COLOREXPAND)) ==
983
         (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
984
        cirrus_bitblt_fgcol(s);
985
        cirrus_bitblt_solidfill(s, blt_rop);
986
    } else {
987
        if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
988
                                   CIRRUS_BLTMODE_PATTERNCOPY)) ==
989
            CIRRUS_BLTMODE_COLOREXPAND) {
990

    
991
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
992
                if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
993
                    cirrus_bitblt_bgcol(s);
994
                else
995
                    cirrus_bitblt_fgcol(s);
996
                s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
997
            } else {
998
                cirrus_bitblt_fgcol(s);
999
                cirrus_bitblt_bgcol(s);
1000
                s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1001
            }
1002
        } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1003
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1004
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1005
                    if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1006
                        cirrus_bitblt_bgcol(s);
1007
                    else
1008
                        cirrus_bitblt_fgcol(s);
1009
                    s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1010
                } else {
1011
                    cirrus_bitblt_fgcol(s);
1012
                    cirrus_bitblt_bgcol(s);
1013
                    s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1014
                }
1015
            } else {
1016
                s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1017
            }
1018
        } else {
1019
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1020
                if (s->cirrus_blt_pixelwidth > 2) {
1021
                    printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1022
                    goto bitblt_ignore;
1023
                }
1024
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1025
                    s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1026
                    s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1027
                    s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028
                } else {
1029
                    s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1030
                }
1031
            } else {
1032
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1033
                    s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1034
                    s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1035
                    s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1036
                } else {
1037
                    s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1038
                }
1039
            }
1040
        }
1041
        // setup bitblt engine.
1042
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1043
            if (!cirrus_bitblt_cputovideo(s))
1044
                goto bitblt_ignore;
1045
        } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1046
            if (!cirrus_bitblt_videotocpu(s))
1047
                goto bitblt_ignore;
1048
        } else {
1049
            if (!cirrus_bitblt_videotovideo(s))
1050
                goto bitblt_ignore;
1051
        }
1052
    }
1053
    return;
1054
  bitblt_ignore:;
1055
    cirrus_bitblt_reset(s);
1056
}
1057

    
1058
static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1059
{
1060
    unsigned old_value;
1061

    
1062
    old_value = s->vga.gr[0x31];
1063
    s->vga.gr[0x31] = reg_value;
1064

    
1065
    if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1066
        ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1067
        cirrus_bitblt_reset(s);
1068
    } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1069
               ((reg_value & CIRRUS_BLT_START) != 0)) {
1070
        cirrus_bitblt_start(s);
1071
    }
1072
}
1073

    
1074

    
1075
/***************************************
1076
 *
1077
 *  basic parameters
1078
 *
1079
 ***************************************/
1080

    
1081
static void cirrus_get_offsets(VGAState *s1,
1082
                               uint32_t *pline_offset,
1083
                               uint32_t *pstart_addr,
1084
                               uint32_t *pline_compare)
1085
{
1086
    CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1087
    uint32_t start_addr, line_offset, line_compare;
1088

    
1089
    line_offset = s->vga.cr[0x13]
1090
        | ((s->vga.cr[0x1b] & 0x10) << 4);
1091
    line_offset <<= 3;
1092
    *pline_offset = line_offset;
1093

    
1094
    start_addr = (s->vga.cr[0x0c] << 8)
1095
        | s->vga.cr[0x0d]
1096
        | ((s->vga.cr[0x1b] & 0x01) << 16)
1097
        | ((s->vga.cr[0x1b] & 0x0c) << 15)
1098
        | ((s->vga.cr[0x1d] & 0x80) << 12);
1099
    *pstart_addr = start_addr;
1100

    
1101
    line_compare = s->vga.cr[0x18] |
1102
        ((s->vga.cr[0x07] & 0x10) << 4) |
1103
        ((s->vga.cr[0x09] & 0x40) << 3);
1104
    *pline_compare = line_compare;
1105
}
1106

    
1107
static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1108
{
1109
    uint32_t ret = 16;
1110

    
1111
    switch (s->cirrus_hidden_dac_data & 0xf) {
1112
    case 0:
1113
        ret = 15;
1114
        break;                        /* Sierra HiColor */
1115
    case 1:
1116
        ret = 16;
1117
        break;                        /* XGA HiColor */
1118
    default:
1119
#ifdef DEBUG_CIRRUS
1120
        printf("cirrus: invalid DAC value %x in 16bpp\n",
1121
               (s->cirrus_hidden_dac_data & 0xf));
1122
#endif
1123
        ret = 15;                /* XXX */
1124
        break;
1125
    }
1126
    return ret;
1127
}
1128

    
1129
static int cirrus_get_bpp(VGAState *s1)
1130
{
1131
    CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1132
    uint32_t ret = 8;
1133

    
1134
    if ((s->vga.sr[0x07] & 0x01) != 0) {
1135
        /* Cirrus SVGA */
1136
        switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1137
        case CIRRUS_SR7_BPP_8:
1138
            ret = 8;
1139
            break;
1140
        case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1141
            ret = cirrus_get_bpp16_depth(s);
1142
            break;
1143
        case CIRRUS_SR7_BPP_24:
1144
            ret = 24;
1145
            break;
1146
        case CIRRUS_SR7_BPP_16:
1147
            ret = cirrus_get_bpp16_depth(s);
1148
            break;
1149
        case CIRRUS_SR7_BPP_32:
1150
            ret = 32;
1151
            break;
1152
        default:
1153
#ifdef DEBUG_CIRRUS
1154
            printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1155
#endif
1156
            ret = 8;
1157
            break;
1158
        }
1159
    } else {
1160
        /* VGA */
1161
        ret = 0;
1162
    }
1163

    
1164
    return ret;
1165
}
1166

    
1167
static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1168
{
1169
    int width, height;
1170

    
1171
    width = (s->cr[0x01] + 1) * 8;
1172
    height = s->cr[0x12] |
1173
        ((s->cr[0x07] & 0x02) << 7) |
1174
        ((s->cr[0x07] & 0x40) << 3);
1175
    height = (height + 1);
1176
    /* interlace support */
1177
    if (s->cr[0x1a] & 0x01)
1178
        height = height * 2;
1179
    *pwidth = width;
1180
    *pheight = height;
1181
}
1182

    
1183
/***************************************
1184
 *
1185
 * bank memory
1186
 *
1187
 ***************************************/
1188

    
1189
static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1190
{
1191
    unsigned offset;
1192
    unsigned limit;
1193

    
1194
    if ((s->vga.gr[0x0b] & 0x01) != 0)        /* dual bank */
1195
        offset = s->vga.gr[0x09 + bank_index];
1196
    else                        /* single bank */
1197
        offset = s->vga.gr[0x09];
1198

    
1199
    if ((s->vga.gr[0x0b] & 0x20) != 0)
1200
        offset <<= 14;
1201
    else
1202
        offset <<= 12;
1203

    
1204
    if (s->real_vram_size <= offset)
1205
        limit = 0;
1206
    else
1207
        limit = s->real_vram_size - offset;
1208

    
1209
    if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1210
        if (limit > 0x8000) {
1211
            offset += 0x8000;
1212
            limit -= 0x8000;
1213
        } else {
1214
            limit = 0;
1215
        }
1216
    }
1217

    
1218
    if (limit > 0) {
1219
        /* Thinking about changing bank base? First, drop the dirty bitmap information
1220
         * on the current location, otherwise we lose this pointer forever */
1221
        if (s->vga.lfb_vram_mapped) {
1222
            target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1223
            cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1224
        }
1225
        s->cirrus_bank_base[bank_index] = offset;
1226
        s->cirrus_bank_limit[bank_index] = limit;
1227
    } else {
1228
        s->cirrus_bank_base[bank_index] = 0;
1229
        s->cirrus_bank_limit[bank_index] = 0;
1230
    }
1231
}
1232

    
1233
/***************************************
1234
 *
1235
 *  I/O access between 0x3c4-0x3c5
1236
 *
1237
 ***************************************/
1238

    
1239
static int
1240
cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1241
{
1242
    switch (reg_index) {
1243
    case 0x00:                        // Standard VGA
1244
    case 0x01:                        // Standard VGA
1245
    case 0x02:                        // Standard VGA
1246
    case 0x03:                        // Standard VGA
1247
    case 0x04:                        // Standard VGA
1248
        return CIRRUS_HOOK_NOT_HANDLED;
1249
    case 0x06:                        // Unlock Cirrus extensions
1250
        *reg_value = s->vga.sr[reg_index];
1251
        break;
1252
    case 0x10:
1253
    case 0x30:
1254
    case 0x50:
1255
    case 0x70:                        // Graphics Cursor X
1256
    case 0x90:
1257
    case 0xb0:
1258
    case 0xd0:
1259
    case 0xf0:                        // Graphics Cursor X
1260
        *reg_value = s->vga.sr[0x10];
1261
        break;
1262
    case 0x11:
1263
    case 0x31:
1264
    case 0x51:
1265
    case 0x71:                        // Graphics Cursor Y
1266
    case 0x91:
1267
    case 0xb1:
1268
    case 0xd1:
1269
    case 0xf1:                        // Graphics Cursor Y
1270
        *reg_value = s->vga.sr[0x11];
1271
        break;
1272
    case 0x05:                        // ???
1273
    case 0x07:                        // Extended Sequencer Mode
1274
    case 0x08:                        // EEPROM Control
1275
    case 0x09:                        // Scratch Register 0
1276
    case 0x0a:                        // Scratch Register 1
1277
    case 0x0b:                        // VCLK 0
1278
    case 0x0c:                        // VCLK 1
1279
    case 0x0d:                        // VCLK 2
1280
    case 0x0e:                        // VCLK 3
1281
    case 0x0f:                        // DRAM Control
1282
    case 0x12:                        // Graphics Cursor Attribute
1283
    case 0x13:                        // Graphics Cursor Pattern Address
1284
    case 0x14:                        // Scratch Register 2
1285
    case 0x15:                        // Scratch Register 3
1286
    case 0x16:                        // Performance Tuning Register
1287
    case 0x17:                        // Configuration Readback and Extended Control
1288
    case 0x18:                        // Signature Generator Control
1289
    case 0x19:                        // Signal Generator Result
1290
    case 0x1a:                        // Signal Generator Result
1291
    case 0x1b:                        // VCLK 0 Denominator & Post
1292
    case 0x1c:                        // VCLK 1 Denominator & Post
1293
    case 0x1d:                        // VCLK 2 Denominator & Post
1294
    case 0x1e:                        // VCLK 3 Denominator & Post
1295
    case 0x1f:                        // BIOS Write Enable and MCLK select
1296
#ifdef DEBUG_CIRRUS
1297
        printf("cirrus: handled inport sr_index %02x\n", reg_index);
1298
#endif
1299
        *reg_value = s->vga.sr[reg_index];
1300
        break;
1301
    default:
1302
#ifdef DEBUG_CIRRUS
1303
        printf("cirrus: inport sr_index %02x\n", reg_index);
1304
#endif
1305
        *reg_value = 0xff;
1306
        break;
1307
    }
1308

    
1309
    return CIRRUS_HOOK_HANDLED;
1310
}
1311

    
1312
static int
1313
cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1314
{
1315
    switch (reg_index) {
1316
    case 0x00:                        // Standard VGA
1317
    case 0x01:                        // Standard VGA
1318
    case 0x02:                        // Standard VGA
1319
    case 0x03:                        // Standard VGA
1320
    case 0x04:                        // Standard VGA
1321
        return CIRRUS_HOOK_NOT_HANDLED;
1322
    case 0x06:                        // Unlock Cirrus extensions
1323
        reg_value &= 0x17;
1324
        if (reg_value == 0x12) {
1325
            s->vga.sr[reg_index] = 0x12;
1326
        } else {
1327
            s->vga.sr[reg_index] = 0x0f;
1328
        }
1329
        break;
1330
    case 0x10:
1331
    case 0x30:
1332
    case 0x50:
1333
    case 0x70:                        // Graphics Cursor X
1334
    case 0x90:
1335
    case 0xb0:
1336
    case 0xd0:
1337
    case 0xf0:                        // Graphics Cursor X
1338
        s->vga.sr[0x10] = reg_value;
1339
        s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1340
        break;
1341
    case 0x11:
1342
    case 0x31:
1343
    case 0x51:
1344
    case 0x71:                        // Graphics Cursor Y
1345
    case 0x91:
1346
    case 0xb1:
1347
    case 0xd1:
1348
    case 0xf1:                        // Graphics Cursor Y
1349
        s->vga.sr[0x11] = reg_value;
1350
        s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1351
        break;
1352
    case 0x07:                        // Extended Sequencer Mode
1353
    cirrus_update_memory_access(s);
1354
    case 0x08:                        // EEPROM Control
1355
    case 0x09:                        // Scratch Register 0
1356
    case 0x0a:                        // Scratch Register 1
1357
    case 0x0b:                        // VCLK 0
1358
    case 0x0c:                        // VCLK 1
1359
    case 0x0d:                        // VCLK 2
1360
    case 0x0e:                        // VCLK 3
1361
    case 0x0f:                        // DRAM Control
1362
    case 0x12:                        // Graphics Cursor Attribute
1363
    case 0x13:                        // Graphics Cursor Pattern Address
1364
    case 0x14:                        // Scratch Register 2
1365
    case 0x15:                        // Scratch Register 3
1366
    case 0x16:                        // Performance Tuning Register
1367
    case 0x18:                        // Signature Generator Control
1368
    case 0x19:                        // Signature Generator Result
1369
    case 0x1a:                        // Signature Generator Result
1370
    case 0x1b:                        // VCLK 0 Denominator & Post
1371
    case 0x1c:                        // VCLK 1 Denominator & Post
1372
    case 0x1d:                        // VCLK 2 Denominator & Post
1373
    case 0x1e:                        // VCLK 3 Denominator & Post
1374
    case 0x1f:                        // BIOS Write Enable and MCLK select
1375
        s->vga.sr[reg_index] = reg_value;
1376
#ifdef DEBUG_CIRRUS
1377
        printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1378
               reg_index, reg_value);
1379
#endif
1380
        break;
1381
    case 0x17:                        // Configuration Readback and Extended Control
1382
        s->vga.sr[reg_index] = (s->vga.sr[reg_index] & 0x38) | (reg_value & 0xc7);
1383
        cirrus_update_memory_access(s);
1384
        break;
1385
    default:
1386
#ifdef DEBUG_CIRRUS
1387
        printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1388
               reg_value);
1389
#endif
1390
        break;
1391
    }
1392

    
1393
    return CIRRUS_HOOK_HANDLED;
1394
}
1395

    
1396
/***************************************
1397
 *
1398
 *  I/O access at 0x3c6
1399
 *
1400
 ***************************************/
1401

    
1402
static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1403
{
1404
    *reg_value = 0xff;
1405
    if (++s->cirrus_hidden_dac_lockindex == 5) {
1406
        *reg_value = s->cirrus_hidden_dac_data;
1407
        s->cirrus_hidden_dac_lockindex = 0;
1408
    }
1409
}
1410

    
1411
static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1412
{
1413
    if (s->cirrus_hidden_dac_lockindex == 4) {
1414
        s->cirrus_hidden_dac_data = reg_value;
1415
#if defined(DEBUG_CIRRUS)
1416
        printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1417
#endif
1418
    }
1419
    s->cirrus_hidden_dac_lockindex = 0;
1420
}
1421

    
1422
/***************************************
1423
 *
1424
 *  I/O access at 0x3c9
1425
 *
1426
 ***************************************/
1427

    
1428
static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1429
{
1430
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1431
        return CIRRUS_HOOK_NOT_HANDLED;
1432
    *reg_value =
1433
        s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1434
                                 s->vga.dac_sub_index];
1435
    if (++s->vga.dac_sub_index == 3) {
1436
        s->vga.dac_sub_index = 0;
1437
        s->vga.dac_read_index++;
1438
    }
1439
    return CIRRUS_HOOK_HANDLED;
1440
}
1441

    
1442
static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1443
{
1444
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1445
        return CIRRUS_HOOK_NOT_HANDLED;
1446
    s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1447
    if (++s->vga.dac_sub_index == 3) {
1448
        memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1449
               s->vga.dac_cache, 3);
1450
        /* XXX update cursor */
1451
        s->vga.dac_sub_index = 0;
1452
        s->vga.dac_write_index++;
1453
    }
1454
    return CIRRUS_HOOK_HANDLED;
1455
}
1456

    
1457
/***************************************
1458
 *
1459
 *  I/O access between 0x3ce-0x3cf
1460
 *
1461
 ***************************************/
1462

    
1463
static int
1464
cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1465
{
1466
    switch (reg_index) {
1467
    case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1468
      *reg_value = s->cirrus_shadow_gr0;
1469
      return CIRRUS_HOOK_HANDLED;
1470
    case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1471
      *reg_value = s->cirrus_shadow_gr1;
1472
      return CIRRUS_HOOK_HANDLED;
1473
    case 0x02:                        // Standard VGA
1474
    case 0x03:                        // Standard VGA
1475
    case 0x04:                        // Standard VGA
1476
    case 0x06:                        // Standard VGA
1477
    case 0x07:                        // Standard VGA
1478
    case 0x08:                        // Standard VGA
1479
        return CIRRUS_HOOK_NOT_HANDLED;
1480
    case 0x05:                        // Standard VGA, Cirrus extended mode
1481
    default:
1482
        break;
1483
    }
1484

    
1485
    if (reg_index < 0x3a) {
1486
        *reg_value = s->vga.gr[reg_index];
1487
    } else {
1488
#ifdef DEBUG_CIRRUS
1489
        printf("cirrus: inport gr_index %02x\n", reg_index);
1490
#endif
1491
        *reg_value = 0xff;
1492
    }
1493

    
1494
    return CIRRUS_HOOK_HANDLED;
1495
}
1496

    
1497
static int
1498
cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1499
{
1500
#if defined(DEBUG_BITBLT) && 0
1501
    printf("gr%02x: %02x\n", reg_index, reg_value);
1502
#endif
1503
    switch (reg_index) {
1504
    case 0x00:                        // Standard VGA, BGCOLOR 0x000000ff
1505
        s->cirrus_shadow_gr0 = reg_value;
1506
        return CIRRUS_HOOK_NOT_HANDLED;
1507
    case 0x01:                        // Standard VGA, FGCOLOR 0x000000ff
1508
        s->cirrus_shadow_gr1 = reg_value;
1509
        return CIRRUS_HOOK_NOT_HANDLED;
1510
    case 0x02:                        // Standard VGA
1511
    case 0x03:                        // Standard VGA
1512
    case 0x04:                        // Standard VGA
1513
    case 0x06:                        // Standard VGA
1514
    case 0x07:                        // Standard VGA
1515
    case 0x08:                        // Standard VGA
1516
        return CIRRUS_HOOK_NOT_HANDLED;
1517
    case 0x05:                        // Standard VGA, Cirrus extended mode
1518
        s->vga.gr[reg_index] = reg_value & 0x7f;
1519
        cirrus_update_memory_access(s);
1520
        break;
1521
    case 0x09:                        // bank offset #0
1522
    case 0x0A:                        // bank offset #1
1523
        s->vga.gr[reg_index] = reg_value;
1524
        cirrus_update_bank_ptr(s, 0);
1525
        cirrus_update_bank_ptr(s, 1);
1526
        cirrus_update_memory_access(s);
1527
        break;
1528
    case 0x0B:
1529
        s->vga.gr[reg_index] = reg_value;
1530
        cirrus_update_bank_ptr(s, 0);
1531
        cirrus_update_bank_ptr(s, 1);
1532
        cirrus_update_memory_access(s);
1533
        break;
1534
    case 0x10:                        // BGCOLOR 0x0000ff00
1535
    case 0x11:                        // FGCOLOR 0x0000ff00
1536
    case 0x12:                        // BGCOLOR 0x00ff0000
1537
    case 0x13:                        // FGCOLOR 0x00ff0000
1538
    case 0x14:                        // BGCOLOR 0xff000000
1539
    case 0x15:                        // FGCOLOR 0xff000000
1540
    case 0x20:                        // BLT WIDTH 0x0000ff
1541
    case 0x22:                        // BLT HEIGHT 0x0000ff
1542
    case 0x24:                        // BLT DEST PITCH 0x0000ff
1543
    case 0x26:                        // BLT SRC PITCH 0x0000ff
1544
    case 0x28:                        // BLT DEST ADDR 0x0000ff
1545
    case 0x29:                        // BLT DEST ADDR 0x00ff00
1546
    case 0x2c:                        // BLT SRC ADDR 0x0000ff
1547
    case 0x2d:                        // BLT SRC ADDR 0x00ff00
1548
    case 0x2f:                  // BLT WRITEMASK
1549
    case 0x30:                        // BLT MODE
1550
    case 0x32:                        // RASTER OP
1551
    case 0x33:                        // BLT MODEEXT
1552
    case 0x34:                        // BLT TRANSPARENT COLOR 0x00ff
1553
    case 0x35:                        // BLT TRANSPARENT COLOR 0xff00
1554
    case 0x38:                        // BLT TRANSPARENT COLOR MASK 0x00ff
1555
    case 0x39:                        // BLT TRANSPARENT COLOR MASK 0xff00
1556
        s->vga.gr[reg_index] = reg_value;
1557
        break;
1558
    case 0x21:                        // BLT WIDTH 0x001f00
1559
    case 0x23:                        // BLT HEIGHT 0x001f00
1560
    case 0x25:                        // BLT DEST PITCH 0x001f00
1561
    case 0x27:                        // BLT SRC PITCH 0x001f00
1562
        s->vga.gr[reg_index] = reg_value & 0x1f;
1563
        break;
1564
    case 0x2a:                        // BLT DEST ADDR 0x3f0000
1565
        s->vga.gr[reg_index] = reg_value & 0x3f;
1566
        /* if auto start mode, starts bit blt now */
1567
        if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1568
            cirrus_bitblt_start(s);
1569
        }
1570
        break;
1571
    case 0x2e:                        // BLT SRC ADDR 0x3f0000
1572
        s->vga.gr[reg_index] = reg_value & 0x3f;
1573
        break;
1574
    case 0x31:                        // BLT STATUS/START
1575
        cirrus_write_bitblt(s, reg_value);
1576
        break;
1577
    default:
1578
#ifdef DEBUG_CIRRUS
1579
        printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1580
               reg_value);
1581
#endif
1582
        break;
1583
    }
1584

    
1585
    return CIRRUS_HOOK_HANDLED;
1586
}
1587

    
1588
/***************************************
1589
 *
1590
 *  I/O access between 0x3d4-0x3d5
1591
 *
1592
 ***************************************/
1593

    
1594
static int
1595
cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1596
{
1597
    switch (reg_index) {
1598
    case 0x00:                        // Standard VGA
1599
    case 0x01:                        // Standard VGA
1600
    case 0x02:                        // Standard VGA
1601
    case 0x03:                        // Standard VGA
1602
    case 0x04:                        // Standard VGA
1603
    case 0x05:                        // Standard VGA
1604
    case 0x06:                        // Standard VGA
1605
    case 0x07:                        // Standard VGA
1606
    case 0x08:                        // Standard VGA
1607
    case 0x09:                        // Standard VGA
1608
    case 0x0a:                        // Standard VGA
1609
    case 0x0b:                        // Standard VGA
1610
    case 0x0c:                        // Standard VGA
1611
    case 0x0d:                        // Standard VGA
1612
    case 0x0e:                        // Standard VGA
1613
    case 0x0f:                        // Standard VGA
1614
    case 0x10:                        // Standard VGA
1615
    case 0x11:                        // Standard VGA
1616
    case 0x12:                        // Standard VGA
1617
    case 0x13:                        // Standard VGA
1618
    case 0x14:                        // Standard VGA
1619
    case 0x15:                        // Standard VGA
1620
    case 0x16:                        // Standard VGA
1621
    case 0x17:                        // Standard VGA
1622
    case 0x18:                        // Standard VGA
1623
        return CIRRUS_HOOK_NOT_HANDLED;
1624
    case 0x24:                        // Attribute Controller Toggle Readback (R)
1625
        *reg_value = (s->vga.ar_flip_flop << 7);
1626
        break;
1627
    case 0x19:                        // Interlace End
1628
    case 0x1a:                        // Miscellaneous Control
1629
    case 0x1b:                        // Extended Display Control
1630
    case 0x1c:                        // Sync Adjust and Genlock
1631
    case 0x1d:                        // Overlay Extended Control
1632
    case 0x22:                        // Graphics Data Latches Readback (R)
1633
    case 0x25:                        // Part Status
1634
    case 0x27:                        // Part ID (R)
1635
        *reg_value = s->vga.cr[reg_index];
1636
        break;
1637
    case 0x26:                        // Attribute Controller Index Readback (R)
1638
        *reg_value = s->vga.ar_index & 0x3f;
1639
        break;
1640
    default:
1641
#ifdef DEBUG_CIRRUS
1642
        printf("cirrus: inport cr_index %02x\n", reg_index);
1643
        *reg_value = 0xff;
1644
#endif
1645
        break;
1646
    }
1647

    
1648
    return CIRRUS_HOOK_HANDLED;
1649
}
1650

    
1651
static int
1652
cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1653
{
1654
    switch (reg_index) {
1655
    case 0x00:                        // Standard VGA
1656
    case 0x01:                        // Standard VGA
1657
    case 0x02:                        // Standard VGA
1658
    case 0x03:                        // Standard VGA
1659
    case 0x04:                        // Standard VGA
1660
    case 0x05:                        // Standard VGA
1661
    case 0x06:                        // Standard VGA
1662
    case 0x07:                        // Standard VGA
1663
    case 0x08:                        // Standard VGA
1664
    case 0x09:                        // Standard VGA
1665
    case 0x0a:                        // Standard VGA
1666
    case 0x0b:                        // Standard VGA
1667
    case 0x0c:                        // Standard VGA
1668
    case 0x0d:                        // Standard VGA
1669
    case 0x0e:                        // Standard VGA
1670
    case 0x0f:                        // Standard VGA
1671
    case 0x10:                        // Standard VGA
1672
    case 0x11:                        // Standard VGA
1673
    case 0x12:                        // Standard VGA
1674
    case 0x13:                        // Standard VGA
1675
    case 0x14:                        // Standard VGA
1676
    case 0x15:                        // Standard VGA
1677
    case 0x16:                        // Standard VGA
1678
    case 0x17:                        // Standard VGA
1679
    case 0x18:                        // Standard VGA
1680
        return CIRRUS_HOOK_NOT_HANDLED;
1681
    case 0x19:                        // Interlace End
1682
    case 0x1a:                        // Miscellaneous Control
1683
    case 0x1b:                        // Extended Display Control
1684
    case 0x1c:                        // Sync Adjust and Genlock
1685
    case 0x1d:                        // Overlay Extended Control
1686
        s->vga.cr[reg_index] = reg_value;
1687
#ifdef DEBUG_CIRRUS
1688
        printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1689
               reg_index, reg_value);
1690
#endif
1691
        break;
1692
    case 0x22:                        // Graphics Data Latches Readback (R)
1693
    case 0x24:                        // Attribute Controller Toggle Readback (R)
1694
    case 0x26:                        // Attribute Controller Index Readback (R)
1695
    case 0x27:                        // Part ID (R)
1696
        break;
1697
    case 0x25:                        // Part Status
1698
    default:
1699
#ifdef DEBUG_CIRRUS
1700
        printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1701
               reg_value);
1702
#endif
1703
        break;
1704
    }
1705

    
1706
    return CIRRUS_HOOK_HANDLED;
1707
}
1708

    
1709
/***************************************
1710
 *
1711
 *  memory-mapped I/O (bitblt)
1712
 *
1713
 ***************************************/
1714

    
1715
static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1716
{
1717
    int value = 0xff;
1718

    
1719
    switch (address) {
1720
    case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1721
        cirrus_hook_read_gr(s, 0x00, &value);
1722
        break;
1723
    case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1724
        cirrus_hook_read_gr(s, 0x10, &value);
1725
        break;
1726
    case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1727
        cirrus_hook_read_gr(s, 0x12, &value);
1728
        break;
1729
    case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1730
        cirrus_hook_read_gr(s, 0x14, &value);
1731
        break;
1732
    case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1733
        cirrus_hook_read_gr(s, 0x01, &value);
1734
        break;
1735
    case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1736
        cirrus_hook_read_gr(s, 0x11, &value);
1737
        break;
1738
    case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1739
        cirrus_hook_read_gr(s, 0x13, &value);
1740
        break;
1741
    case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1742
        cirrus_hook_read_gr(s, 0x15, &value);
1743
        break;
1744
    case (CIRRUS_MMIO_BLTWIDTH + 0):
1745
        cirrus_hook_read_gr(s, 0x20, &value);
1746
        break;
1747
    case (CIRRUS_MMIO_BLTWIDTH + 1):
1748
        cirrus_hook_read_gr(s, 0x21, &value);
1749
        break;
1750
    case (CIRRUS_MMIO_BLTHEIGHT + 0):
1751
        cirrus_hook_read_gr(s, 0x22, &value);
1752
        break;
1753
    case (CIRRUS_MMIO_BLTHEIGHT + 1):
1754
        cirrus_hook_read_gr(s, 0x23, &value);
1755
        break;
1756
    case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1757
        cirrus_hook_read_gr(s, 0x24, &value);
1758
        break;
1759
    case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1760
        cirrus_hook_read_gr(s, 0x25, &value);
1761
        break;
1762
    case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1763
        cirrus_hook_read_gr(s, 0x26, &value);
1764
        break;
1765
    case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1766
        cirrus_hook_read_gr(s, 0x27, &value);
1767
        break;
1768
    case (CIRRUS_MMIO_BLTDESTADDR + 0):
1769
        cirrus_hook_read_gr(s, 0x28, &value);
1770
        break;
1771
    case (CIRRUS_MMIO_BLTDESTADDR + 1):
1772
        cirrus_hook_read_gr(s, 0x29, &value);
1773
        break;
1774
    case (CIRRUS_MMIO_BLTDESTADDR + 2):
1775
        cirrus_hook_read_gr(s, 0x2a, &value);
1776
        break;
1777
    case (CIRRUS_MMIO_BLTSRCADDR + 0):
1778
        cirrus_hook_read_gr(s, 0x2c, &value);
1779
        break;
1780
    case (CIRRUS_MMIO_BLTSRCADDR + 1):
1781
        cirrus_hook_read_gr(s, 0x2d, &value);
1782
        break;
1783
    case (CIRRUS_MMIO_BLTSRCADDR + 2):
1784
        cirrus_hook_read_gr(s, 0x2e, &value);
1785
        break;
1786
    case CIRRUS_MMIO_BLTWRITEMASK:
1787
        cirrus_hook_read_gr(s, 0x2f, &value);
1788
        break;
1789
    case CIRRUS_MMIO_BLTMODE:
1790
        cirrus_hook_read_gr(s, 0x30, &value);
1791
        break;
1792
    case CIRRUS_MMIO_BLTROP:
1793
        cirrus_hook_read_gr(s, 0x32, &value);
1794
        break;
1795
    case CIRRUS_MMIO_BLTMODEEXT:
1796
        cirrus_hook_read_gr(s, 0x33, &value);
1797
        break;
1798
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1799
        cirrus_hook_read_gr(s, 0x34, &value);
1800
        break;
1801
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1802
        cirrus_hook_read_gr(s, 0x35, &value);
1803
        break;
1804
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1805
        cirrus_hook_read_gr(s, 0x38, &value);
1806
        break;
1807
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1808
        cirrus_hook_read_gr(s, 0x39, &value);
1809
        break;
1810
    case CIRRUS_MMIO_BLTSTATUS:
1811
        cirrus_hook_read_gr(s, 0x31, &value);
1812
        break;
1813
    default:
1814
#ifdef DEBUG_CIRRUS
1815
        printf("cirrus: mmio read - address 0x%04x\n", address);
1816
#endif
1817
        break;
1818
    }
1819

    
1820
    return (uint8_t) value;
1821
}
1822

    
1823
static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1824
                                  uint8_t value)
1825
{
1826
    switch (address) {
1827
    case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1828
        cirrus_hook_write_gr(s, 0x00, value);
1829
        break;
1830
    case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1831
        cirrus_hook_write_gr(s, 0x10, value);
1832
        break;
1833
    case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1834
        cirrus_hook_write_gr(s, 0x12, value);
1835
        break;
1836
    case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1837
        cirrus_hook_write_gr(s, 0x14, value);
1838
        break;
1839
    case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1840
        cirrus_hook_write_gr(s, 0x01, value);
1841
        break;
1842
    case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1843
        cirrus_hook_write_gr(s, 0x11, value);
1844
        break;
1845
    case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1846
        cirrus_hook_write_gr(s, 0x13, value);
1847
        break;
1848
    case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1849
        cirrus_hook_write_gr(s, 0x15, value);
1850
        break;
1851
    case (CIRRUS_MMIO_BLTWIDTH + 0):
1852
        cirrus_hook_write_gr(s, 0x20, value);
1853
        break;
1854
    case (CIRRUS_MMIO_BLTWIDTH + 1):
1855
        cirrus_hook_write_gr(s, 0x21, value);
1856
        break;
1857
    case (CIRRUS_MMIO_BLTHEIGHT + 0):
1858
        cirrus_hook_write_gr(s, 0x22, value);
1859
        break;
1860
    case (CIRRUS_MMIO_BLTHEIGHT + 1):
1861
        cirrus_hook_write_gr(s, 0x23, value);
1862
        break;
1863
    case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1864
        cirrus_hook_write_gr(s, 0x24, value);
1865
        break;
1866
    case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1867
        cirrus_hook_write_gr(s, 0x25, value);
1868
        break;
1869
    case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1870
        cirrus_hook_write_gr(s, 0x26, value);
1871
        break;
1872
    case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1873
        cirrus_hook_write_gr(s, 0x27, value);
1874
        break;
1875
    case (CIRRUS_MMIO_BLTDESTADDR + 0):
1876
        cirrus_hook_write_gr(s, 0x28, value);
1877
        break;
1878
    case (CIRRUS_MMIO_BLTDESTADDR + 1):
1879
        cirrus_hook_write_gr(s, 0x29, value);
1880
        break;
1881
    case (CIRRUS_MMIO_BLTDESTADDR + 2):
1882
        cirrus_hook_write_gr(s, 0x2a, value);
1883
        break;
1884
    case (CIRRUS_MMIO_BLTDESTADDR + 3):
1885
        /* ignored */
1886
        break;
1887
    case (CIRRUS_MMIO_BLTSRCADDR + 0):
1888
        cirrus_hook_write_gr(s, 0x2c, value);
1889
        break;
1890
    case (CIRRUS_MMIO_BLTSRCADDR + 1):
1891
        cirrus_hook_write_gr(s, 0x2d, value);
1892
        break;
1893
    case (CIRRUS_MMIO_BLTSRCADDR + 2):
1894
        cirrus_hook_write_gr(s, 0x2e, value);
1895
        break;
1896
    case CIRRUS_MMIO_BLTWRITEMASK:
1897
        cirrus_hook_write_gr(s, 0x2f, value);
1898
        break;
1899
    case CIRRUS_MMIO_BLTMODE:
1900
        cirrus_hook_write_gr(s, 0x30, value);
1901
        break;
1902
    case CIRRUS_MMIO_BLTROP:
1903
        cirrus_hook_write_gr(s, 0x32, value);
1904
        break;
1905
    case CIRRUS_MMIO_BLTMODEEXT:
1906
        cirrus_hook_write_gr(s, 0x33, value);
1907
        break;
1908
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1909
        cirrus_hook_write_gr(s, 0x34, value);
1910
        break;
1911
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1912
        cirrus_hook_write_gr(s, 0x35, value);
1913
        break;
1914
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1915
        cirrus_hook_write_gr(s, 0x38, value);
1916
        break;
1917
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1918
        cirrus_hook_write_gr(s, 0x39, value);
1919
        break;
1920
    case CIRRUS_MMIO_BLTSTATUS:
1921
        cirrus_hook_write_gr(s, 0x31, value);
1922
        break;
1923
    default:
1924
#ifdef DEBUG_CIRRUS
1925
        printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1926
               address, value);
1927
#endif
1928
        break;
1929
    }
1930
}
1931

    
1932
/***************************************
1933
 *
1934
 *  write mode 4/5
1935
 *
1936
 * assume TARGET_PAGE_SIZE >= 16
1937
 *
1938
 ***************************************/
1939

    
1940
static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1941
                                             unsigned mode,
1942
                                             unsigned offset,
1943
                                             uint32_t mem_value)
1944
{
1945
    int x;
1946
    unsigned val = mem_value;
1947
    uint8_t *dst;
1948

    
1949
    dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1950
    for (x = 0; x < 8; x++) {
1951
        if (val & 0x80) {
1952
            *dst = s->cirrus_shadow_gr1;
1953
        } else if (mode == 5) {
1954
            *dst = s->cirrus_shadow_gr0;
1955
        }
1956
        val <<= 1;
1957
        dst++;
1958
    }
1959
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1960
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
1961
}
1962

    
1963
static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1964
                                              unsigned mode,
1965
                                              unsigned offset,
1966
                                              uint32_t mem_value)
1967
{
1968
    int x;
1969
    unsigned val = mem_value;
1970
    uint8_t *dst;
1971

    
1972
    dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1973
    for (x = 0; x < 8; x++) {
1974
        if (val & 0x80) {
1975
            *dst = s->cirrus_shadow_gr1;
1976
            *(dst + 1) = s->vga.gr[0x11];
1977
        } else if (mode == 5) {
1978
            *dst = s->cirrus_shadow_gr0;
1979
            *(dst + 1) = s->vga.gr[0x10];
1980
        }
1981
        val <<= 1;
1982
        dst += 2;
1983
    }
1984
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1985
    cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
1986
}
1987

    
1988
/***************************************
1989
 *
1990
 *  memory access between 0xa0000-0xbffff
1991
 *
1992
 ***************************************/
1993

    
1994
static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1995
{
1996
    CirrusVGAState *s = opaque;
1997
    unsigned bank_index;
1998
    unsigned bank_offset;
1999
    uint32_t val;
2000

    
2001
    if ((s->vga.sr[0x07] & 0x01) == 0) {
2002
        return vga_mem_readb(s, addr);
2003
    }
2004

    
2005
    addr &= 0x1ffff;
2006

    
2007
    if (addr < 0x10000) {
2008
        /* XXX handle bitblt */
2009
        /* video memory */
2010
        bank_index = addr >> 15;
2011
        bank_offset = addr & 0x7fff;
2012
        if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2013
            bank_offset += s->cirrus_bank_base[bank_index];
2014
            if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2015
                bank_offset <<= 4;
2016
            } else if (s->vga.gr[0x0B] & 0x02) {
2017
                bank_offset <<= 3;
2018
            }
2019
            bank_offset &= s->cirrus_addr_mask;
2020
            val = *(s->vga.vram_ptr + bank_offset);
2021
        } else
2022
            val = 0xff;
2023
    } else if (addr >= 0x18000 && addr < 0x18100) {
2024
        /* memory-mapped I/O */
2025
        val = 0xff;
2026
        if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2027
            val = cirrus_mmio_blt_read(s, addr & 0xff);
2028
        }
2029
    } else {
2030
        val = 0xff;
2031
#ifdef DEBUG_CIRRUS
2032
        printf("cirrus: mem_readb %06x\n", addr);
2033
#endif
2034
    }
2035
    return val;
2036
}
2037

    
2038
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2039
{
2040
    uint32_t v;
2041
#ifdef TARGET_WORDS_BIGENDIAN
2042
    v = cirrus_vga_mem_readb(opaque, addr) << 8;
2043
    v |= cirrus_vga_mem_readb(opaque, addr + 1);
2044
#else
2045
    v = cirrus_vga_mem_readb(opaque, addr);
2046
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2047
#endif
2048
    return v;
2049
}
2050

    
2051
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2052
{
2053
    uint32_t v;
2054
#ifdef TARGET_WORDS_BIGENDIAN
2055
    v = cirrus_vga_mem_readb(opaque, addr) << 24;
2056
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2057
    v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2058
    v |= cirrus_vga_mem_readb(opaque, addr + 3);
2059
#else
2060
    v = cirrus_vga_mem_readb(opaque, addr);
2061
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2062
    v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2063
    v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2064
#endif
2065
    return v;
2066
}
2067

    
2068
static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2069
                                  uint32_t mem_value)
2070
{
2071
    CirrusVGAState *s = opaque;
2072
    unsigned bank_index;
2073
    unsigned bank_offset;
2074
    unsigned mode;
2075

    
2076
    if ((s->vga.sr[0x07] & 0x01) == 0) {
2077
        vga_mem_writeb(s, addr, mem_value);
2078
        return;
2079
    }
2080

    
2081
    addr &= 0x1ffff;
2082

    
2083
    if (addr < 0x10000) {
2084
        if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2085
            /* bitblt */
2086
            *s->cirrus_srcptr++ = (uint8_t) mem_value;
2087
            if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2088
                cirrus_bitblt_cputovideo_next(s);
2089
            }
2090
        } else {
2091
            /* video memory */
2092
            bank_index = addr >> 15;
2093
            bank_offset = addr & 0x7fff;
2094
            if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2095
                bank_offset += s->cirrus_bank_base[bank_index];
2096
                if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2097
                    bank_offset <<= 4;
2098
                } else if (s->vga.gr[0x0B] & 0x02) {
2099
                    bank_offset <<= 3;
2100
                }
2101
                bank_offset &= s->cirrus_addr_mask;
2102
                mode = s->vga.gr[0x05] & 0x7;
2103
                if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2104
                    *(s->vga.vram_ptr + bank_offset) = mem_value;
2105
                    cpu_physical_memory_set_dirty(s->vga.vram_offset +
2106
                                                  bank_offset);
2107
                } else {
2108
                    if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2109
                        cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2110
                                                         bank_offset,
2111
                                                         mem_value);
2112
                    } else {
2113
                        cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2114
                                                          bank_offset,
2115
                                                          mem_value);
2116
                    }
2117
                }
2118
            }
2119
        }
2120
    } else if (addr >= 0x18000 && addr < 0x18100) {
2121
        /* memory-mapped I/O */
2122
        if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2123
            cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2124
        }
2125
    } else {
2126
#ifdef DEBUG_CIRRUS
2127
        printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2128
#endif
2129
    }
2130
}
2131

    
2132
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2133
{
2134
#ifdef TARGET_WORDS_BIGENDIAN
2135
    cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2136
    cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2137
#else
2138
    cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2139
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2140
#endif
2141
}
2142

    
2143
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2144
{
2145
#ifdef TARGET_WORDS_BIGENDIAN
2146
    cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2147
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2148
    cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2149
    cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2150
#else
2151
    cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2152
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2153
    cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2154
    cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2155
#endif
2156
}
2157

    
2158
static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2159
    cirrus_vga_mem_readb,
2160
    cirrus_vga_mem_readw,
2161
    cirrus_vga_mem_readl,
2162
};
2163

    
2164
static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2165
    cirrus_vga_mem_writeb,
2166
    cirrus_vga_mem_writew,
2167
    cirrus_vga_mem_writel,
2168
};
2169

    
2170
/***************************************
2171
 *
2172
 *  hardware cursor
2173
 *
2174
 ***************************************/
2175

    
2176
static inline void invalidate_cursor1(CirrusVGAState *s)
2177
{
2178
    if (s->last_hw_cursor_size) {
2179
        vga_invalidate_scanlines(&s->vga,
2180
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2181
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2182
    }
2183
}
2184

    
2185
static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2186
{
2187
    const uint8_t *src;
2188
    uint32_t content;
2189
    int y, y_min, y_max;
2190

    
2191
    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2192
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2193
        src += (s->vga.sr[0x13] & 0x3c) * 256;
2194
        y_min = 64;
2195
        y_max = -1;
2196
        for(y = 0; y < 64; y++) {
2197
            content = ((uint32_t *)src)[0] |
2198
                ((uint32_t *)src)[1] |
2199
                ((uint32_t *)src)[2] |
2200
                ((uint32_t *)src)[3];
2201
            if (content) {
2202
                if (y < y_min)
2203
                    y_min = y;
2204
                if (y > y_max)
2205
                    y_max = y;
2206
            }
2207
            src += 16;
2208
        }
2209
    } else {
2210
        src += (s->vga.sr[0x13] & 0x3f) * 256;
2211
        y_min = 32;
2212
        y_max = -1;
2213
        for(y = 0; y < 32; y++) {
2214
            content = ((uint32_t *)src)[0] |
2215
                ((uint32_t *)(src + 128))[0];
2216
            if (content) {
2217
                if (y < y_min)
2218
                    y_min = y;
2219
                if (y > y_max)
2220
                    y_max = y;
2221
            }
2222
            src += 4;
2223
        }
2224
    }
2225
    if (y_min > y_max) {
2226
        s->last_hw_cursor_y_start = 0;
2227
        s->last_hw_cursor_y_end = 0;
2228
    } else {
2229
        s->last_hw_cursor_y_start = y_min;
2230
        s->last_hw_cursor_y_end = y_max + 1;
2231
    }
2232
}
2233

    
2234
/* NOTE: we do not currently handle the cursor bitmap change, so we
2235
   update the cursor only if it moves. */
2236
static void cirrus_cursor_invalidate(VGAState *s1)
2237
{
2238
    CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2239
    int size;
2240

    
2241
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2242
        size = 0;
2243
    } else {
2244
        if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2245
            size = 64;
2246
        else
2247
            size = 32;
2248
    }
2249
    /* invalidate last cursor and new cursor if any change */
2250
    if (s->last_hw_cursor_size != size ||
2251
        s->last_hw_cursor_x != s->hw_cursor_x ||
2252
        s->last_hw_cursor_y != s->hw_cursor_y) {
2253

    
2254
        invalidate_cursor1(s);
2255

    
2256
        s->last_hw_cursor_size = size;
2257
        s->last_hw_cursor_x = s->hw_cursor_x;
2258
        s->last_hw_cursor_y = s->hw_cursor_y;
2259
        /* compute the real cursor min and max y */
2260
        cirrus_cursor_compute_yrange(s);
2261
        invalidate_cursor1(s);
2262
    }
2263
}
2264

    
2265
static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2266
{
2267
    CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2268
    int w, h, bpp, x1, x2, poffset;
2269
    unsigned int color0, color1;
2270
    const uint8_t *palette, *src;
2271
    uint32_t content;
2272

    
2273
    if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2274
        return;
2275
    /* fast test to see if the cursor intersects with the scan line */
2276
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2277
        h = 64;
2278
    } else {
2279
        h = 32;
2280
    }
2281
    if (scr_y < s->hw_cursor_y ||
2282
        scr_y >= (s->hw_cursor_y + h))
2283
        return;
2284

    
2285
    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2286
    if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2287
        src += (s->vga.sr[0x13] & 0x3c) * 256;
2288
        src += (scr_y - s->hw_cursor_y) * 16;
2289
        poffset = 8;
2290
        content = ((uint32_t *)src)[0] |
2291
            ((uint32_t *)src)[1] |
2292
            ((uint32_t *)src)[2] |
2293
            ((uint32_t *)src)[3];
2294
    } else {
2295
        src += (s->vga.sr[0x13] & 0x3f) * 256;
2296
        src += (scr_y - s->hw_cursor_y) * 4;
2297
        poffset = 128;
2298
        content = ((uint32_t *)src)[0] |
2299
            ((uint32_t *)(src + 128))[0];
2300
    }
2301
    /* if nothing to draw, no need to continue */
2302
    if (!content)
2303
        return;
2304
    w = h;
2305

    
2306
    x1 = s->hw_cursor_x;
2307
    if (x1 >= s->vga.last_scr_width)
2308
        return;
2309
    x2 = s->hw_cursor_x + w;
2310
    if (x2 > s->vga.last_scr_width)
2311
        x2 = s->vga.last_scr_width;
2312
    w = x2 - x1;
2313
    palette = s->cirrus_hidden_palette;
2314
    color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2315
                                 c6_to_8(palette[0x0 * 3 + 1]),
2316
                                 c6_to_8(palette[0x0 * 3 + 2]));
2317
    color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2318
                                 c6_to_8(palette[0xf * 3 + 1]),
2319
                                 c6_to_8(palette[0xf * 3 + 2]));
2320
    bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
2321
    d1 += x1 * bpp;
2322
    switch(ds_get_bits_per_pixel(s->vga.ds)) {
2323
    default:
2324
        break;
2325
    case 8:
2326
        vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2327
        break;
2328
    case 15:
2329
        vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2330
        break;
2331
    case 16:
2332
        vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2333
        break;
2334
    case 32:
2335
        vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2336
        break;
2337
    }
2338
}
2339

    
2340
/***************************************
2341
 *
2342
 *  LFB memory access
2343
 *
2344
 ***************************************/
2345

    
2346
static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2347
{
2348
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2349
    uint32_t ret;
2350

    
2351
    addr &= s->cirrus_addr_mask;
2352

    
2353
    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2354
        ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2355
        /* memory-mapped I/O */
2356
        ret = cirrus_mmio_blt_read(s, addr & 0xff);
2357
    } else if (0) {
2358
        /* XXX handle bitblt */
2359
        ret = 0xff;
2360
    } else {
2361
        /* video memory */
2362
        if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2363
            addr <<= 4;
2364
        } else if (s->vga.gr[0x0B] & 0x02) {
2365
            addr <<= 3;
2366
        }
2367
        addr &= s->cirrus_addr_mask;
2368
        ret = *(s->vga.vram_ptr + addr);
2369
    }
2370

    
2371
    return ret;
2372
}
2373

    
2374
static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2375
{
2376
    uint32_t v;
2377
#ifdef TARGET_WORDS_BIGENDIAN
2378
    v = cirrus_linear_readb(opaque, addr) << 8;
2379
    v |= cirrus_linear_readb(opaque, addr + 1);
2380
#else
2381
    v = cirrus_linear_readb(opaque, addr);
2382
    v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2383
#endif
2384
    return v;
2385
}
2386

    
2387
static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2388
{
2389
    uint32_t v;
2390
#ifdef TARGET_WORDS_BIGENDIAN
2391
    v = cirrus_linear_readb(opaque, addr) << 24;
2392
    v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2393
    v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2394
    v |= cirrus_linear_readb(opaque, addr + 3);
2395
#else
2396
    v = cirrus_linear_readb(opaque, addr);
2397
    v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2398
    v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2399
    v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2400
#endif
2401
    return v;
2402
}
2403

    
2404
static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2405
                                 uint32_t val)
2406
{
2407
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2408
    unsigned mode;
2409

    
2410
    addr &= s->cirrus_addr_mask;
2411

    
2412
    if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2413
        ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {
2414
        /* memory-mapped I/O */
2415
        cirrus_mmio_blt_write(s, addr & 0xff, val);
2416
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2417
        /* bitblt */
2418
        *s->cirrus_srcptr++ = (uint8_t) val;
2419
        if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2420
            cirrus_bitblt_cputovideo_next(s);
2421
        }
2422
    } else {
2423
        /* video memory */
2424
        if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2425
            addr <<= 4;
2426
        } else if (s->vga.gr[0x0B] & 0x02) {
2427
            addr <<= 3;
2428
        }
2429
        addr &= s->cirrus_addr_mask;
2430

    
2431
        mode = s->vga.gr[0x05] & 0x7;
2432
        if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2433
            *(s->vga.vram_ptr + addr) = (uint8_t) val;
2434
            cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
2435
        } else {
2436
            if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2437
                cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2438
            } else {
2439
                cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2440
            }
2441
        }
2442
    }
2443
}
2444

    
2445
static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2446
                                 uint32_t val)
2447
{
2448
#ifdef TARGET_WORDS_BIGENDIAN
2449
    cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2450
    cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2451
#else
2452
    cirrus_linear_writeb(opaque, addr, val & 0xff);
2453
    cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2454
#endif
2455
}
2456

    
2457
static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2458
                                 uint32_t val)
2459
{
2460
#ifdef TARGET_WORDS_BIGENDIAN
2461
    cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2462
    cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2463
    cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2464
    cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2465
#else
2466
    cirrus_linear_writeb(opaque, addr, val & 0xff);
2467
    cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2468
    cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2469
    cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2470
#endif
2471
}
2472

    
2473

    
2474
static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2475
    cirrus_linear_readb,
2476
    cirrus_linear_readw,
2477
    cirrus_linear_readl,
2478
};
2479

    
2480
static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2481
    cirrus_linear_writeb,
2482
    cirrus_linear_writew,
2483
    cirrus_linear_writel,
2484
};
2485

    
2486
/***************************************
2487
 *
2488
 *  system to screen memory access
2489
 *
2490
 ***************************************/
2491

    
2492

    
2493
static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2494
{
2495
    uint32_t ret;
2496

    
2497
    /* XXX handle bitblt */
2498
    ret = 0xff;
2499
    return ret;
2500
}
2501

    
2502
static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2503
{
2504
    uint32_t v;
2505
#ifdef TARGET_WORDS_BIGENDIAN
2506
    v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2507
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2508
#else
2509
    v = cirrus_linear_bitblt_readb(opaque, addr);
2510
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2511
#endif
2512
    return v;
2513
}
2514

    
2515
static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2516
{
2517
    uint32_t v;
2518
#ifdef TARGET_WORDS_BIGENDIAN
2519
    v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2520
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2521
    v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2522
    v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2523
#else
2524
    v = cirrus_linear_bitblt_readb(opaque, addr);
2525
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2526
    v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2527
    v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2528
#endif
2529
    return v;
2530
}
2531

    
2532
static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2533
                                 uint32_t val)
2534
{
2535
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2536

    
2537
    if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2538
        /* bitblt */
2539
        *s->cirrus_srcptr++ = (uint8_t) val;
2540
        if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2541
            cirrus_bitblt_cputovideo_next(s);
2542
        }
2543
    }
2544
}
2545

    
2546
static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2547
                                 uint32_t val)
2548
{
2549
#ifdef TARGET_WORDS_BIGENDIAN
2550
    cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2551
    cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2552
#else
2553
    cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2554
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2555
#endif
2556
}
2557

    
2558
static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2559
                                 uint32_t val)
2560
{
2561
#ifdef TARGET_WORDS_BIGENDIAN
2562
    cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2563
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2564
    cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2565
    cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2566
#else
2567
    cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2568
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2569
    cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2570
    cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2571
#endif
2572
}
2573

    
2574

    
2575
static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2576
    cirrus_linear_bitblt_readb,
2577
    cirrus_linear_bitblt_readw,
2578
    cirrus_linear_bitblt_readl,
2579
};
2580

    
2581
static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2582
    cirrus_linear_bitblt_writeb,
2583
    cirrus_linear_bitblt_writew,
2584
    cirrus_linear_bitblt_writel,
2585
};
2586

    
2587
static void map_linear_vram(CirrusVGAState *s)
2588
{
2589
    if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2590
        s->vga.map_addr = s->vga.lfb_addr;
2591
        s->vga.map_end = s->vga.lfb_end;
2592
        cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2593
    }
2594

    
2595
    if (!s->vga.map_addr)
2596
        return;
2597

    
2598
    s->vga.lfb_vram_mapped = 0;
2599

    
2600
    if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2601
        && !((s->vga.sr[0x07] & 0x01) == 0)
2602
        && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2603
        && !(s->vga.gr[0x0B] & 0x02)) {
2604

    
2605
        cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2606
                                    (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2607
        cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2608
                                    (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2609

    
2610
        s->vga.lfb_vram_mapped = 1;
2611
    }
2612
    else {
2613
        cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2614
                                     s->vga.vga_io_memory);
2615
    }
2616

    
2617
    vga_dirty_log_start(&s->vga);
2618
}
2619

    
2620
static void unmap_linear_vram(CirrusVGAState *s)
2621
{
2622
    if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
2623
        s->vga.map_addr = s->vga.map_end = 0;
2624

    
2625
    cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2626
                                 s->vga.vga_io_memory);
2627
}
2628

    
2629
/* Compute the memory access functions */
2630
static void cirrus_update_memory_access(CirrusVGAState *s)
2631
{
2632
    unsigned mode;
2633

    
2634
    if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2635
        goto generic_io;
2636
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2637
        goto generic_io;
2638
    } else {
2639
        if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2640
            goto generic_io;
2641
        } else if (s->vga.gr[0x0B] & 0x02) {
2642
            goto generic_io;
2643
        }
2644

    
2645
        mode = s->vga.gr[0x05] & 0x7;
2646
        if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2647
            map_linear_vram(s);
2648
        } else {
2649
        generic_io:
2650
            unmap_linear_vram(s);
2651
        }
2652
    }
2653
}
2654

    
2655

    
2656
/* I/O ports */
2657

    
2658
static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2659
{
2660
    CirrusVGAState *s = opaque;
2661
    int val, index;
2662

    
2663
    /* check port range access depending on color/monochrome mode */
2664
    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->vga.msr & MSR_COLOR_EMULATION))
2665
        || (addr >= 0x3d0 && addr <= 0x3df
2666
            && !(s->vga.msr & MSR_COLOR_EMULATION))) {
2667
        val = 0xff;
2668
    } else {
2669
        switch (addr) {
2670
        case 0x3c0:
2671
            if (s->vga.ar_flip_flop == 0) {
2672
                val = s->vga.ar_index;
2673
            } else {
2674
                val = 0;
2675
            }
2676
            break;
2677
        case 0x3c1:
2678
            index = s->vga.ar_index & 0x1f;
2679
            if (index < 21)
2680
                val = s->vga.ar[index];
2681
            else
2682
                val = 0;
2683
            break;
2684
        case 0x3c2:
2685
            val = s->vga.st00;
2686
            break;
2687
        case 0x3c4:
2688
            val = s->vga.sr_index;
2689
            break;
2690
        case 0x3c5:
2691
            if (cirrus_hook_read_sr(s, s->vga.sr_index, &val))
2692
                break;
2693
            val = s->vga.sr[s->vga.sr_index];
2694
#ifdef DEBUG_VGA_REG
2695
            printf("vga: read SR%x = 0x%02x\n", s->vga.sr_index, val);
2696
#endif
2697
            break;
2698
        case 0x3c6:
2699
            cirrus_read_hidden_dac(s, &val);
2700
            break;
2701
        case 0x3c7:
2702
            val = s->vga.dac_state;
2703
            break;
2704
        case 0x3c8:
2705
            val = s->vga.dac_write_index;
2706
            s->cirrus_hidden_dac_lockindex = 0;
2707
            break;
2708
        case 0x3c9:
2709
            if (cirrus_hook_read_palette(s, &val))
2710
                break;
2711
            val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
2712
            if (++s->vga.dac_sub_index == 3) {
2713
                s->vga.dac_sub_index = 0;
2714
                s->vga.dac_read_index++;
2715
            }
2716
            break;
2717
        case 0x3ca:
2718
            val = s->vga.fcr;
2719
            break;
2720
        case 0x3cc:
2721
            val = s->vga.msr;
2722
            break;
2723
        case 0x3ce:
2724
            val = s->vga.gr_index;
2725
            break;
2726
        case 0x3cf:
2727
            if (cirrus_hook_read_gr(s, s->vga.gr_index, &val))
2728
                break;
2729
            val = s->vga.gr[s->vga.gr_index];
2730
#ifdef DEBUG_VGA_REG
2731
            printf("vga: read GR%x = 0x%02x\n", s->vga.gr_index, val);
2732
#endif
2733
            break;
2734
        case 0x3b4:
2735
        case 0x3d4:
2736
            val = s->vga.cr_index;
2737
            break;
2738
        case 0x3b5:
2739
        case 0x3d5:
2740
            if (cirrus_hook_read_cr(s, s->vga.cr_index, &val))
2741
                break;
2742
            val = s->vga.cr[s->vga.cr_index];
2743
#ifdef DEBUG_VGA_REG
2744
            printf("vga: read CR%x = 0x%02x\n", s->vga.cr_index, val);
2745
#endif
2746
            break;
2747
        case 0x3ba:
2748
        case 0x3da:
2749
            /* just toggle to fool polling */
2750
            val = s->vga.st01 = s->vga.retrace(&s->vga);
2751
            s->vga.ar_flip_flop = 0;
2752
            break;
2753
        default:
2754
            val = 0x00;
2755
            break;
2756
        }
2757
    }
2758
#if defined(DEBUG_VGA)
2759
    printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2760
#endif
2761
    return val;
2762
}
2763

    
2764
static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2765
{
2766
    CirrusVGAState *s = opaque;
2767
    int index;
2768

    
2769
    /* check port range access depending on color/monochrome mode */
2770
    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->vga.msr & MSR_COLOR_EMULATION))
2771
        || (addr >= 0x3d0 && addr <= 0x3df
2772
            && !(s->vga.msr & MSR_COLOR_EMULATION)))
2773
        return;
2774

    
2775
#ifdef DEBUG_VGA
2776
    printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2777
#endif
2778

    
2779
    switch (addr) {
2780
    case 0x3c0:
2781
        if (s->vga.ar_flip_flop == 0) {
2782
            val &= 0x3f;
2783
            s->vga.ar_index = val;
2784
        } else {
2785
            index = s->vga.ar_index & 0x1f;
2786
            switch (index) {
2787
            case 0x00 ... 0x0f:
2788
                s->vga.ar[index] = val & 0x3f;
2789
                break;
2790
            case 0x10:
2791
                s->vga.ar[index] = val & ~0x10;
2792
                break;
2793
            case 0x11:
2794
                s->vga.ar[index] = val;
2795
                break;
2796
            case 0x12:
2797
                s->vga.ar[index] = val & ~0xc0;
2798
                break;
2799
            case 0x13:
2800
                s->vga.ar[index] = val & ~0xf0;
2801
                break;
2802
            case 0x14:
2803
                s->vga.ar[index] = val & ~0xf0;
2804
                break;
2805
            default:
2806
                break;
2807
            }
2808
        }
2809
        s->vga.ar_flip_flop ^= 1;
2810
        break;
2811
    case 0x3c2:
2812
        s->vga.msr = val & ~0x10;
2813
        s->vga.update_retrace_info(&s->vga);
2814
        break;
2815
    case 0x3c4:
2816
        s->vga.sr_index = val;
2817
        break;
2818
    case 0x3c5:
2819
        if (cirrus_hook_write_sr(s, s->vga.sr_index, val))
2820
            break;
2821
#ifdef DEBUG_VGA_REG
2822
        printf("vga: write SR%x = 0x%02x\n", s->vga.sr_index, val);
2823
#endif
2824
        s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
2825
        if (s->vga.sr_index == 1) s->vga.update_retrace_info(&s->vga);
2826
        break;
2827
    case 0x3c6:
2828
        cirrus_write_hidden_dac(s, val);
2829
        break;
2830
    case 0x3c7:
2831
        s->vga.dac_read_index = val;
2832
        s->vga.dac_sub_index = 0;
2833
        s->vga.dac_state = 3;
2834
        break;
2835
    case 0x3c8:
2836
        s->vga.dac_write_index = val;
2837
        s->vga.dac_sub_index = 0;
2838
        s->vga.dac_state = 0;
2839
        break;
2840
    case 0x3c9:
2841
        if (cirrus_hook_write_palette(s, val))
2842
            break;
2843
        s->vga.dac_cache[s->vga.dac_sub_index] = val;
2844
        if (++s->vga.dac_sub_index == 3) {
2845
            memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
2846
            s->vga.dac_sub_index = 0;
2847
            s->vga.dac_write_index++;
2848
        }
2849
        break;
2850
    case 0x3ce:
2851
        s->vga.gr_index = val;
2852
        break;
2853
    case 0x3cf:
2854
        if (cirrus_hook_write_gr(s, s->vga.gr_index, val))
2855
            break;
2856
#ifdef DEBUG_VGA_REG
2857
        printf("vga: write GR%x = 0x%02x\n", s->vga.gr_index, val);
2858
#endif
2859
        s->vga.gr[s->vga.gr_index] = val & gr_mask[s->vga.gr_index];
2860
        break;
2861
    case 0x3b4:
2862
    case 0x3d4:
2863
        s->vga.cr_index = val;
2864
        break;
2865
    case 0x3b5:
2866
    case 0x3d5:
2867
        if (cirrus_hook_write_cr(s, s->vga.cr_index, val))
2868
            break;
2869
#ifdef DEBUG_VGA_REG
2870
        printf("vga: write CR%x = 0x%02x\n", s->vga.cr_index, val);
2871
#endif
2872
        /* handle CR0-7 protection */
2873
        if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
2874
            /* can always write bit 4 of CR7 */
2875
            if (s->vga.cr_index == 7)
2876
                s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (val & 0x10);
2877
            return;
2878
        }
2879
        switch (s->vga.cr_index) {
2880
        case 0x01:                /* horizontal display end */
2881
        case 0x07:
2882
        case 0x09:
2883
        case 0x0c:
2884
        case 0x0d:
2885
        case 0x12:                /* vertical display end */
2886
            s->vga.cr[s->vga.cr_index] = val;
2887
            break;
2888

    
2889
        default:
2890
            s->vga.cr[s->vga.cr_index] = val;
2891
            break;
2892
        }
2893

    
2894
        switch(s->vga.cr_index) {
2895
        case 0x00:
2896
        case 0x04:
2897
        case 0x05:
2898
        case 0x06:
2899
        case 0x07:
2900
        case 0x11:
2901
        case 0x17:
2902
            s->vga.update_retrace_info(&s->vga);
2903
            break;
2904
        }
2905
        break;
2906
    case 0x3ba:
2907
    case 0x3da:
2908
        s->vga.fcr = val & 0x10;
2909
        break;
2910
    }
2911
}
2912

    
2913
/***************************************
2914
 *
2915
 *  memory-mapped I/O access
2916
 *
2917
 ***************************************/
2918

    
2919
static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2920
{
2921
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2922

    
2923
    addr &= CIRRUS_PNPMMIO_SIZE - 1;
2924

    
2925
    if (addr >= 0x100) {
2926
        return cirrus_mmio_blt_read(s, addr - 0x100);
2927
    } else {
2928
        return vga_ioport_read(s, addr + 0x3c0);
2929
    }
2930
}
2931

    
2932
static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2933
{
2934
    uint32_t v;
2935
#ifdef TARGET_WORDS_BIGENDIAN
2936
    v = cirrus_mmio_readb(opaque, addr) << 8;
2937
    v |= cirrus_mmio_readb(opaque, addr + 1);
2938
#else
2939
    v = cirrus_mmio_readb(opaque, addr);
2940
    v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2941
#endif
2942
    return v;
2943
}
2944

    
2945
static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2946
{
2947
    uint32_t v;
2948
#ifdef TARGET_WORDS_BIGENDIAN
2949
    v = cirrus_mmio_readb(opaque, addr) << 24;
2950
    v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2951
    v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2952
    v |= cirrus_mmio_readb(opaque, addr + 3);
2953
#else
2954
    v = cirrus_mmio_readb(opaque, addr);
2955
    v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2956
    v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2957
    v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2958
#endif
2959
    return v;
2960
}
2961

    
2962
static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2963
                               uint32_t val)
2964
{
2965
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2966

    
2967
    addr &= CIRRUS_PNPMMIO_SIZE - 1;
2968

    
2969
    if (addr >= 0x100) {
2970
        cirrus_mmio_blt_write(s, addr - 0x100, val);
2971
    } else {
2972
        vga_ioport_write(s, addr + 0x3c0, val);
2973
    }
2974
}
2975

    
2976
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2977
                               uint32_t val)
2978
{
2979
#ifdef TARGET_WORDS_BIGENDIAN
2980
    cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2981
    cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2982
#else
2983
    cirrus_mmio_writeb(opaque, addr, val & 0xff);
2984
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2985
#endif
2986
}
2987

    
2988
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2989
                               uint32_t val)
2990
{
2991
#ifdef TARGET_WORDS_BIGENDIAN
2992
    cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2993
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2994
    cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2995
    cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2996
#else
2997
    cirrus_mmio_writeb(opaque, addr, val & 0xff);
2998
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2999
    cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3000
    cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3001
#endif
3002
}
3003

    
3004

    
3005
static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3006
    cirrus_mmio_readb,
3007
    cirrus_mmio_readw,
3008
    cirrus_mmio_readl,
3009
};
3010

    
3011
static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3012
    cirrus_mmio_writeb,
3013
    cirrus_mmio_writew,
3014
    cirrus_mmio_writel,
3015
};
3016

    
3017
/* load/save state */
3018

    
3019
static void cirrus_vga_save(QEMUFile *f, void *opaque)
3020
{
3021
    CirrusVGAState *s = opaque;
3022

    
3023
    if (s->vga.pci_dev)
3024
        pci_device_save(s->vga.pci_dev, f);
3025

    
3026
    qemu_put_be32s(f, &s->vga.latch);
3027
    qemu_put_8s(f, &s->vga.sr_index);
3028
    qemu_put_buffer(f, s->vga.sr, 256);
3029
    qemu_put_8s(f, &s->vga.gr_index);
3030
    qemu_put_8s(f, &s->cirrus_shadow_gr0);
3031
    qemu_put_8s(f, &s->cirrus_shadow_gr1);
3032
    qemu_put_buffer(f, s->vga.gr + 2, 254);
3033
    qemu_put_8s(f, &s->vga.ar_index);
3034
    qemu_put_buffer(f, s->vga.ar, 21);
3035
    qemu_put_be32(f, s->vga.ar_flip_flop);
3036
    qemu_put_8s(f, &s->vga.cr_index);
3037
    qemu_put_buffer(f, s->vga.cr, 256);
3038
    qemu_put_8s(f, &s->vga.msr);
3039
    qemu_put_8s(f, &s->vga.fcr);
3040
    qemu_put_8s(f, &s->vga.st00);
3041
    qemu_put_8s(f, &s->vga.st01);
3042

    
3043
    qemu_put_8s(f, &s->vga.dac_state);
3044
    qemu_put_8s(f, &s->vga.dac_sub_index);
3045
    qemu_put_8s(f, &s->vga.dac_read_index);
3046
    qemu_put_8s(f, &s->vga.dac_write_index);
3047
    qemu_put_buffer(f, s->vga.dac_cache, 3);
3048
    qemu_put_buffer(f, s->vga.palette, 768);
3049

    
3050
    qemu_put_be32(f, s->vga.bank_offset);
3051

    
3052
    qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3053
    qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3054

    
3055
    qemu_put_be32s(f, &s->hw_cursor_x);
3056
    qemu_put_be32s(f, &s->hw_cursor_y);
3057
    /* XXX: we do not save the bitblt state - we assume we do not save
3058
       the state when the blitter is active */
3059
}
3060

    
3061
static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3062
{
3063
    CirrusVGAState *s = opaque;
3064
    int ret;
3065

    
3066
    if (version_id > 2)
3067
        return -EINVAL;
3068

    
3069
    if (s->vga.pci_dev && version_id >= 2) {
3070
        ret = pci_device_load(s->vga.pci_dev, f);
3071
        if (ret < 0)
3072
            return ret;
3073
    }
3074

    
3075
    qemu_get_be32s(f, &s->vga.latch);
3076
    qemu_get_8s(f, &s->vga.sr_index);
3077
    qemu_get_buffer(f, s->vga.sr, 256);
3078
    qemu_get_8s(f, &s->vga.gr_index);
3079
    qemu_get_8s(f, &s->cirrus_shadow_gr0);
3080
    qemu_get_8s(f, &s->cirrus_shadow_gr1);
3081
    s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3082
    s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3083
    qemu_get_buffer(f, s->vga.gr + 2, 254);
3084
    qemu_get_8s(f, &s->vga.ar_index);
3085
    qemu_get_buffer(f, s->vga.ar, 21);
3086
    s->vga.ar_flip_flop=qemu_get_be32(f);
3087
    qemu_get_8s(f, &s->vga.cr_index);
3088
    qemu_get_buffer(f, s->vga.cr, 256);
3089
    qemu_get_8s(f, &s->vga.msr);
3090
    qemu_get_8s(f, &s->vga.fcr);
3091
    qemu_get_8s(f, &s->vga.st00);
3092
    qemu_get_8s(f, &s->vga.st01);
3093

    
3094
    qemu_get_8s(f, &s->vga.dac_state);
3095
    qemu_get_8s(f, &s->vga.dac_sub_index);
3096
    qemu_get_8s(f, &s->vga.dac_read_index);
3097
    qemu_get_8s(f, &s->vga.dac_write_index);
3098
    qemu_get_buffer(f, s->vga.dac_cache, 3);
3099
    qemu_get_buffer(f, s->vga.palette, 768);
3100

    
3101
    s->vga.bank_offset = qemu_get_be32(f);
3102

    
3103
    qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3104
    qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3105

    
3106
    qemu_get_be32s(f, &s->hw_cursor_x);
3107
    qemu_get_be32s(f, &s->hw_cursor_y);
3108

    
3109
    cirrus_update_memory_access(s);
3110
    /* force refresh */
3111
    s->vga.graphic_mode = -1;
3112
    cirrus_update_bank_ptr(s, 0);
3113
    cirrus_update_bank_ptr(s, 1);
3114
    return 0;
3115
}
3116

    
3117
/***************************************
3118
 *
3119
 *  initialize
3120
 *
3121
 ***************************************/
3122

    
3123
static void cirrus_reset(void *opaque)
3124
{
3125
    CirrusVGAState *s = opaque;
3126

    
3127
    vga_reset(s);
3128
    unmap_linear_vram(s);
3129
    s->vga.sr[0x06] = 0x0f;
3130
    if (s->device_id == CIRRUS_ID_CLGD5446) {
3131
        /* 4MB 64 bit memory config, always PCI */
3132
        s->vga.sr[0x1F] = 0x2d;                // MemClock
3133
        s->vga.gr[0x18] = 0x0f;             // fastest memory configuration
3134
        s->vga.sr[0x0f] = 0x98;
3135
        s->vga.sr[0x17] = 0x20;
3136
        s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3137
    } else {
3138
        s->vga.sr[0x1F] = 0x22;                // MemClock
3139
        s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
3140
        s->vga.sr[0x17] = s->bustype;
3141
        s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3142
    }
3143
    s->vga.cr[0x27] = s->device_id;
3144

    
3145
    /* Win2K seems to assume that the pattern buffer is at 0xff
3146
       initially ! */
3147
    memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
3148

    
3149
    s->cirrus_hidden_dac_lockindex = 5;
3150
    s->cirrus_hidden_dac_data = 0;
3151
}
3152

    
3153
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3154
{
3155
    int i;
3156
    static int inited;
3157

    
3158
    if (!inited) {
3159
        inited = 1;
3160
        for(i = 0;i < 256; i++)
3161
            rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3162
        rop_to_index[CIRRUS_ROP_0] = 0;
3163
        rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3164
        rop_to_index[CIRRUS_ROP_NOP] = 2;
3165
        rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3166
        rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3167
        rop_to_index[CIRRUS_ROP_SRC] = 5;
3168
        rop_to_index[CIRRUS_ROP_1] = 6;
3169
        rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3170
        rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3171
        rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3172
        rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3173
        rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3174
        rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3175
        rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3176
        rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3177
        rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3178
        s->device_id = device_id;
3179
        if (is_pci)
3180
            s->bustype = CIRRUS_BUSTYPE_PCI;
3181
        else
3182
            s->bustype = CIRRUS_BUSTYPE_ISA;
3183
    }
3184

    
3185
    register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3186

    
3187
    register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3188
    register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3189
    register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3190
    register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3191

    
3192
    register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3193

    
3194
    register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3195
    register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3196
    register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3197
    register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3198

    
3199
    s->vga.vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3200
                                                  cirrus_vga_mem_write, s);
3201
    cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3202
                                 s->vga.vga_io_memory);
3203
    qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3204

    
3205
    /* I/O handler for LFB */
3206
    s->cirrus_linear_io_addr =
3207
        cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s);
3208

    
3209
    /* I/O handler for LFB */
3210
    s->cirrus_linear_bitblt_io_addr =
3211
        cpu_register_io_memory(0, cirrus_linear_bitblt_read,
3212
                               cirrus_linear_bitblt_write, s);
3213

    
3214
    /* I/O handler for memory-mapped I/O */
3215
    s->cirrus_mmio_io_addr =
3216
        cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3217

    
3218
    s->real_vram_size =
3219
        (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3220

    
3221
    /* XXX: s->vga.vram_size must be a power of two */
3222
    s->cirrus_addr_mask = s->real_vram_size - 1;
3223
    s->linear_mmio_mask = s->real_vram_size - 256;
3224

    
3225
    s->vga.get_bpp = cirrus_get_bpp;
3226
    s->vga.get_offsets = cirrus_get_offsets;
3227
    s->vga.get_resolution = cirrus_get_resolution;
3228
    s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3229
    s->vga.cursor_draw_line = cirrus_cursor_draw_line;
3230

    
3231
    qemu_register_reset(cirrus_reset, s);
3232
    cirrus_reset(s);
3233
    register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3234
}
3235

    
3236
/***************************************
3237
 *
3238
 *  ISA bus support
3239
 *
3240
 ***************************************/
3241

    
3242
void isa_cirrus_vga_init(int vga_ram_size)
3243
{
3244
    CirrusVGAState *s;
3245

    
3246
    s = qemu_mallocz(sizeof(CirrusVGAState));
3247

    
3248
    vga_common_init(&s->vga, vga_ram_size);
3249
    cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3250
    s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3251
                                     s->vga.screen_dump, s->vga.text_update,
3252
                                     &s->vga);
3253
    /* XXX ISA-LFB support */
3254
}
3255

    
3256
/***************************************
3257
 *
3258
 *  PCI bus support
3259
 *
3260
 ***************************************/
3261

    
3262
static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3263
                               uint32_t addr, uint32_t size, int type)
3264
{
3265
    CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3266

    
3267
    /* XXX: add byte swapping apertures */
3268
    cpu_register_physical_memory(addr, s->vga.vram_size,
3269
                                 s->cirrus_linear_io_addr);
3270
    cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3271
                                 s->cirrus_linear_bitblt_io_addr);
3272

    
3273
    s->vga.map_addr = s->vga.map_end = 0;
3274
    s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3275
    s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3276
    /* account for overflow */
3277
    if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
3278
        s->vga.lfb_end = addr + VGA_RAM_SIZE;
3279

    
3280
    vga_dirty_log_start(&s->vga);
3281
}
3282

    
3283
static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3284
                                uint32_t addr, uint32_t size, int type)
3285
{
3286
    CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3287

    
3288
    cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3289
                                 s->cirrus_mmio_io_addr);
3290
}
3291

    
3292
static void pci_cirrus_write_config(PCIDevice *d,
3293
                                    uint32_t address, uint32_t val, int len)
3294
{
3295
    PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3296
    CirrusVGAState *s = &pvs->cirrus_vga;
3297

    
3298
    pci_default_write_config(d, address, val, len);
3299
    if (s->vga.map_addr && pvs->dev.io_regions[0].addr == -1)
3300
        s->vga.map_addr = 0;
3301
    cirrus_update_memory_access(s);
3302
}
3303

    
3304
void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size)
3305
{
3306
    PCICirrusVGAState *d;
3307
    uint8_t *pci_conf;
3308
    CirrusVGAState *s;
3309
    int device_id;
3310

    
3311
    device_id = CIRRUS_ID_CLGD5446;
3312

    
3313
    /* setup PCI configuration registers */
3314
    d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3315
                                                 sizeof(PCICirrusVGAState),
3316
                                                 -1, NULL, pci_cirrus_write_config);
3317
    pci_conf = d->dev.config;
3318
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3319
    pci_config_set_device_id(pci_conf, device_id);
3320
    pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3321
    pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3322
    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
3323

    
3324
    /* setup VGA */
3325
    s = &d->cirrus_vga;
3326
    vga_common_init(&s->vga, vga_ram_size);
3327
    cirrus_init_common(s, device_id, 1);
3328

    
3329
    s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3330
                                     s->vga.screen_dump, s->vga.text_update,
3331
                                     &s->vga);
3332

    
3333
    s->vga.pci_dev = (PCIDevice *)d;
3334

    
3335
    /* setup memory space */
3336
    /* memory #0 LFB */
3337
    /* memory #1 memory-mapped I/O */
3338
    /* XXX: s->vga.vram_size must be a power of two */
3339
    pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3340
                           PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3341
    if (device_id == CIRRUS_ID_CLGD5446) {
3342
        pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3343
                               PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3344
    }
3345
    /* XXX: ROM BIOS */
3346
}