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/*
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* QEMU CUDA support
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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|
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/* Bits in B data register: all active low */
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#define TREQ 0x08 /* Transfer request (input) */ |
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#define TACK 0x10 /* Transfer acknowledge (output) */ |
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#define TIP 0x20 /* Transfer in progress (output) */ |
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|
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/* Bits in ACR */
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#define SR_CTRL 0x1c /* Shift register control bits */ |
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#define SR_EXT 0x0c /* Shift on external clock */ |
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#define SR_OUT 0x10 /* Shift out if 1 */ |
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|
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/* Bits in IFR and IER */
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#define IER_SET 0x80 /* set bits in IER */ |
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#define IER_CLR 0 /* clear bits in IER */ |
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#define SR_INT 0x04 /* Shift register full/empty */ |
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#define T1_INT 0x40 /* Timer 1 interrupt */ |
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|
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/* Bits in ACR */
|
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#define T1MODE 0xc0 /* Timer 1 mode */ |
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#define T1MODE_CONT 0x40 /* continuous interrupts */ |
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|
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/* commands (1st byte) */
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#define ADB_PACKET 0 |
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#define CUDA_PACKET 1 |
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#define ERROR_PACKET 2 |
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#define TIMER_PACKET 3 |
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#define POWER_PACKET 4 |
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#define MACIIC_PACKET 5 |
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#define PMU_PACKET 6 |
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|
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|
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/* CUDA commands (2nd byte) */
|
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#define CUDA_WARM_START 0x0 |
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#define CUDA_AUTOPOLL 0x1 |
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#define CUDA_GET_6805_ADDR 0x2 |
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#define CUDA_GET_TIME 0x3 |
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#define CUDA_GET_PRAM 0x7 |
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#define CUDA_SET_6805_ADDR 0x8 |
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#define CUDA_SET_TIME 0x9 |
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#define CUDA_POWERDOWN 0xa |
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#define CUDA_POWERUP_TIME 0xb |
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#define CUDA_SET_PRAM 0xc |
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#define CUDA_MS_RESET 0xd |
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#define CUDA_SEND_DFAC 0xe |
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#define CUDA_BATTERY_SWAP_SENSE 0x10 |
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#define CUDA_RESET_SYSTEM 0x11 |
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#define CUDA_SET_IPL 0x12 |
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#define CUDA_FILE_SERVER_FLAG 0x13 |
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#define CUDA_SET_AUTO_RATE 0x14 |
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#define CUDA_GET_AUTO_RATE 0x16 |
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#define CUDA_SET_DEVICE_LIST 0x19 |
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#define CUDA_GET_DEVICE_LIST 0x1a |
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#define CUDA_SET_ONE_SECOND_MODE 0x1b |
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#define CUDA_SET_POWER_MESSAGES 0x21 |
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#define CUDA_GET_SET_IIC 0x22 |
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#define CUDA_WAKEUP 0x23 |
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#define CUDA_TIMER_TICKLE 0x24 |
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#define CUDA_COMBINED_FORMAT_IIC 0x25 |
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|
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#define CUDA_TIMER_FREQ (4700000 / 6) |
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|
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typedef struct CUDATimer { |
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unsigned int latch; |
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uint16_t counter_value; /* counter value at load time */
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int64_t load_time; |
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int64_t next_irq_time; |
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QEMUTimer *timer; |
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} CUDATimer; |
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|
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typedef struct CUDAState { |
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/* cuda registers */
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uint8_t b; /* B-side data */
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uint8_t a; /* A-side data */
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uint8_t dirb; /* B-side direction (1=output) */
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uint8_t dira; /* A-side direction (1=output) */
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uint8_t sr; /* Shift register */
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uint8_t acr; /* Auxiliary control register */
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uint8_t pcr; /* Peripheral control register */
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uint8_t ifr; /* Interrupt flag register */
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uint8_t ier; /* Interrupt enable register */
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uint8_t anh; /* A-side data, no handshake */
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CUDATimer timers[2];
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uint8_t last_b; /* last value of B register */
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uint8_t last_acr; /* last value of B register */
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|
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int data_in_size;
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int data_in_index;
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int data_out_index;
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|
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int irq;
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uint8_t autopoll; |
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uint8_t data_in[128];
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uint8_t data_out[16];
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} CUDAState; |
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|
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static CUDAState cuda_state;
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ADBBusState adb_bus; |
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|
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static void cuda_update(CUDAState *s); |
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static void cuda_receive_packet_from_host(CUDAState *s, |
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const uint8_t *data, int len); |
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|
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static void cuda_update_irq(CUDAState *s) |
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{
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if (s->ifr & s->ier & SR_INT) {
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pic_set_irq(s->irq, 1);
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} else {
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pic_set_irq(s->irq, 0);
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} |
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} |
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static unsigned int get_counter(CUDATimer *s) |
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{
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int64_t d; |
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unsigned int counter; |
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d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
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CUDA_TIMER_FREQ, ticks_per_sec); |
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if (d <= s->counter_value) {
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counter = d; |
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} else {
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counter = s->latch - 1 - ((d - s->counter_value) % s->latch);
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} |
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return counter;
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} |
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static void set_counter(CUDATimer *s, unsigned int val) |
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{
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s->load_time = qemu_get_clock(vm_clock); |
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s->counter_value = val; |
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} |
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static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
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{
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int64_t d, next_time, base; |
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/* current counter value */
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d = muldiv64(current_time - s->load_time, |
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CUDA_TIMER_FREQ, ticks_per_sec); |
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if (d <= s->counter_value) {
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next_time = s->counter_value + 1;
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} else {
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base = ((d - s->counter_value) % s->latch); |
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base = (base * s->latch) + s->counter_value; |
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next_time = base + s->latch; |
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} |
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next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
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s->load_time; |
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if (next_time <= current_time)
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next_time = current_time + 1;
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return next_time;
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} |
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|
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static void cuda_timer1(void *opaque) |
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{
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CUDAState *s = opaque; |
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CUDATimer *ti = &s->timers[0];
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|
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ti->next_irq_time = get_next_irq_time(ti, ti->next_irq_time); |
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qemu_mod_timer(ti->timer, ti->next_irq_time); |
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s->ifr |= T1_INT; |
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cuda_update_irq(s); |
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} |
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|
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static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
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{
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CUDAState *s = opaque; |
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uint32_t val; |
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|
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addr = (addr >> 9) & 0xf; |
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switch(addr) {
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case 0: |
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val = s->b; |
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break;
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case 1: |
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val = s->a; |
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break;
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case 2: |
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val = s->dirb; |
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break;
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case 3: |
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val = s->dira; |
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break;
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case 4: |
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val = get_counter(&s->timers[0]) & 0xff; |
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s->ifr &= ~T1_INT; |
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cuda_update_irq(s); |
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break;
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case 5: |
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val = get_counter(&s->timers[0]) >> 8; |
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s->ifr &= ~T1_INT; |
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cuda_update_irq(s); |
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break;
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case 6: |
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val = s->timers[0].latch & 0xff; |
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break;
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case 7: |
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val = (s->timers[0].latch >> 8) & 0xff; |
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break;
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case 8: |
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val = get_counter(&s->timers[1]) & 0xff; |
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break;
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case 9: |
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val = get_counter(&s->timers[1]) >> 8; |
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break;
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case 10: |
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if (s->data_in_index < s->data_in_size) {
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val = s->data_in[s->data_in_index]; |
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} else {
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val = 0;
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} |
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break;
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case 11: |
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val = s->acr; |
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break;
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case 12: |
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val = s->pcr; |
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break;
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case 13: |
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val = s->ifr; |
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break;
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case 14: |
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val = s->ier; |
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break;
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default:
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case 15: |
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val = s->anh; |
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break;
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} |
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#ifdef DEBUG_CUDA
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printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
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#endif
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return val;
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} |
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|
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static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{
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CUDAState *s = opaque; |
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|
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addr = (addr >> 9) & 0xf; |
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#ifdef DEBUG_CUDA
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printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
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#endif
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|
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switch(addr) {
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case 0: |
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s->b = val; |
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cuda_update(s); |
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break;
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case 1: |
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s->a = val; |
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break;
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case 2: |
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s->dirb = val; |
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break;
|
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case 3: |
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s->dira = val; |
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break;
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case 4: |
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val = val | (get_counter(&s->timers[0]) & 0xff00); |
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set_counter(&s->timers[0], val);
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break;
|
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case 5: |
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val = (val << 8) | (get_counter(&s->timers[0]) & 0xff); |
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set_counter(&s->timers[0], val);
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break;
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case 6: |
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
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break;
|
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case 7: |
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
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break;
|
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case 8: |
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val = val | (get_counter(&s->timers[1]) & 0xff00); |
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set_counter(&s->timers[1], val);
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break;
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case 9: |
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val = (val << 8) | (get_counter(&s->timers[1]) & 0xff); |
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set_counter(&s->timers[1], val);
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break;
|
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case 10: |
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s->sr = val; |
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break;
|
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case 11: |
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s->acr = val; |
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if ((s->acr & T1MODE) == T1MODE_CONT) {
|
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if ((s->last_acr & T1MODE) != T1MODE_CONT) {
|
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CUDATimer *ti = &s->timers[0];
|
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/* activate timer interrupt */
|
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ti->next_irq_time = get_next_irq_time(ti, qemu_get_clock(vm_clock)); |
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qemu_mod_timer(ti->timer, ti->next_irq_time); |
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} |
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} else {
|
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if ((s->last_acr & T1MODE) == T1MODE_CONT) {
|
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CUDATimer *ti = &s->timers[0];
|
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qemu_del_timer(ti->timer); |
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} |
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} |
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cuda_update(s); |
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break;
|
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case 12: |
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s->pcr = val; |
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break;
|
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case 13: |
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/* reset bits */
|
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s->ifr &= ~val; |
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cuda_update_irq(s); |
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break;
|
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case 14: |
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if (val & IER_SET) {
|
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/* set bits */
|
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s->ier |= val & 0x7f;
|
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} else {
|
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/* reset bits */
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s->ier &= ~val; |
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} |
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cuda_update_irq(s); |
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break;
|
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default:
|
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case 15: |
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s->anh = val; |
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break;
|
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} |
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} |
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|
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/* NOTE: TIP and TREQ are negated */
|
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static void cuda_update(CUDAState *s) |
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{
|
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if (s->data_in_index < s->data_in_size) {
|
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/* data input */
|
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if (!(s->b & TIP) &&
|
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(s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
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s->sr = s->data_in[s->data_in_index++]; |
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s->ifr |= SR_INT; |
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cuda_update_irq(s); |
| 361 |
} |
| 362 |
} |
| 363 |
if (s->data_in_index < s->data_in_size) {
|
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/* there is some data to read */
|
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s->b = (s->b & ~TREQ); |
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} else {
|
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s->b = (s->b | TREQ); |
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} |
| 369 |
|
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if (s->acr & SR_OUT) {
|
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/* data output */
|
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if (!(s->b & TIP) &&
|
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(s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
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if (s->data_out_index < sizeof(s->data_out)) { |
| 375 |
s->data_out[s->data_out_index++] = s->sr; |
| 376 |
} |
| 377 |
s->ifr |= SR_INT; |
| 378 |
cuda_update_irq(s); |
| 379 |
} |
| 380 |
} |
| 381 |
|
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/* check end of data output */
|
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if (!(s->acr & SR_OUT) && (s->last_acr & SR_OUT)) {
|
| 384 |
if (s->data_out_index > 0) |
| 385 |
cuda_receive_packet_from_host(s, s->data_out, s->data_out_index); |
| 386 |
s->data_out_index = 0;
|
| 387 |
} |
| 388 |
s->last_acr = s->acr; |
| 389 |
s->last_b = s->b; |
| 390 |
} |
| 391 |
|
| 392 |
static void cuda_send_packet_to_host(CUDAState *s, |
| 393 |
const uint8_t *data, int len) |
| 394 |
{
|
| 395 |
memcpy(s->data_in, data, len); |
| 396 |
s->data_in_size = len; |
| 397 |
s->data_in_index = 0;
|
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cuda_update(s); |
| 399 |
s->ifr |= SR_INT; |
| 400 |
cuda_update_irq(s); |
| 401 |
} |
| 402 |
|
| 403 |
void adb_send_packet(ADBBusState *bus, const uint8_t *buf, int len) |
| 404 |
{
|
| 405 |
CUDAState *s = &cuda_state; |
| 406 |
uint8_t data[16];
|
| 407 |
|
| 408 |
memcpy(data + 1, buf, len);
|
| 409 |
data[0] = ADB_PACKET;
|
| 410 |
cuda_send_packet_to_host(s, data, len + 1);
|
| 411 |
} |
| 412 |
|
| 413 |
static void cuda_receive_packet(CUDAState *s, |
| 414 |
const uint8_t *data, int len) |
| 415 |
{
|
| 416 |
uint8_t obuf[16];
|
| 417 |
int ti;
|
| 418 |
|
| 419 |
switch(data[0]) { |
| 420 |
case CUDA_AUTOPOLL:
|
| 421 |
s->autopoll = data[1];
|
| 422 |
obuf[0] = CUDA_PACKET;
|
| 423 |
obuf[1] = data[1]; |
| 424 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 425 |
break;
|
| 426 |
case CUDA_GET_TIME:
|
| 427 |
/* XXX: add time support ? */
|
| 428 |
ti = 0;
|
| 429 |
obuf[0] = CUDA_PACKET;
|
| 430 |
obuf[1] = 0; |
| 431 |
obuf[2] = 0; |
| 432 |
obuf[3] = ti >> 24; |
| 433 |
obuf[4] = ti >> 16; |
| 434 |
obuf[5] = ti >> 8; |
| 435 |
obuf[6] = ti;
|
| 436 |
cuda_send_packet_to_host(s, obuf, 7);
|
| 437 |
break;
|
| 438 |
case CUDA_SET_TIME:
|
| 439 |
case CUDA_FILE_SERVER_FLAG:
|
| 440 |
case CUDA_SET_DEVICE_LIST:
|
| 441 |
case CUDA_SET_AUTO_RATE:
|
| 442 |
case CUDA_SET_POWER_MESSAGES:
|
| 443 |
obuf[0] = CUDA_PACKET;
|
| 444 |
obuf[1] = 0; |
| 445 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 446 |
break;
|
| 447 |
default:
|
| 448 |
break;
|
| 449 |
} |
| 450 |
} |
| 451 |
|
| 452 |
static void cuda_receive_packet_from_host(CUDAState *s, |
| 453 |
const uint8_t *data, int len) |
| 454 |
{
|
| 455 |
switch(data[0]) { |
| 456 |
case ADB_PACKET:
|
| 457 |
adb_receive_packet(&adb_bus, data + 1, len - 1); |
| 458 |
break;
|
| 459 |
case CUDA_PACKET:
|
| 460 |
cuda_receive_packet(s, data + 1, len - 1); |
| 461 |
break;
|
| 462 |
} |
| 463 |
} |
| 464 |
|
| 465 |
static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 466 |
{
|
| 467 |
} |
| 468 |
|
| 469 |
static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 470 |
{
|
| 471 |
} |
| 472 |
|
| 473 |
static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
| 474 |
{
|
| 475 |
return 0; |
| 476 |
} |
| 477 |
|
| 478 |
static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
| 479 |
{
|
| 480 |
return 0; |
| 481 |
} |
| 482 |
|
| 483 |
static CPUWriteMemoryFunc *cuda_write[] = {
|
| 484 |
&cuda_writeb, |
| 485 |
&cuda_writew, |
| 486 |
&cuda_writel, |
| 487 |
}; |
| 488 |
|
| 489 |
static CPUReadMemoryFunc *cuda_read[] = {
|
| 490 |
&cuda_readb, |
| 491 |
&cuda_readw, |
| 492 |
&cuda_readl, |
| 493 |
}; |
| 494 |
|
| 495 |
int cuda_init(void) |
| 496 |
{
|
| 497 |
CUDAState *s = &cuda_state; |
| 498 |
int cuda_mem_index;
|
| 499 |
|
| 500 |
s->timers[0].latch = 0x10000; |
| 501 |
set_counter(&s->timers[0], 0xffff); |
| 502 |
s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
|
| 503 |
s->timers[1].latch = 0x10000; |
| 504 |
set_counter(&s->timers[1], 0xffff); |
| 505 |
cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
|
| 506 |
return cuda_mem_index;
|
| 507 |
} |