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# Date Author Comment
0ec6dc73 01/04/2012 03:41 pm Peter Maydell

hw/omap_gpmc: Fix region map/unmap when configuring prefetch engine

When configuring the prefetch engine (and also when resetting from
a state where the prefetch engine was enabled) be careful to adhere
to the "unmap/change config fields/map" ordering, to avoid trying...

c0465d1a 11/09/2011 08:06 pm Peter Maydell

hw/omap_gpmc.c: Add missing 'break's to fix 8 bit NAND writes

Add missing 'break' statements which would have meant that writing
to an 8 bit NAND device was broken. Spotted by Coverity (see bug
887883).

Signed-off-by: Peter Maydell <>...

7e36b264 09/23/2011 09:36 am Peter Maydell

hw/omap_gpmc: Modify correct field when writing IRQSTATUS register

Writing to IRQSTATUS should affect irqst, not irqen -- error
spotted by Andrzej Zaborowski.

Signed-off-by: Peter Maydell <>
Signed-off-by: Andrzej Zaborowski <>

71963455 09/23/2011 09:36 am Peter Maydell

hw/omap_gpmc: Add comment about FIFOTHRESHOLDSTATUS bit

Promote the remark about why we handle FIFOTHRESHOLDSTATUS the
way we do from the commit message of de8af7fe0 to a comment in
the code.

Signed-off-by: Peter Maydell <>
Signed-off-by: Andrzej Zaborowski <>

856f2df7 08/28/2011 07:37 pm Juha Riihimäki

omap_gpmc: Accept a zero mask field on omap3630

OMAP3630 adds an extra bit of address masking, so a mask of
0xb1111 is valid. Unfortunately the GPMC_REVISION is the same as
on the OMAP3430 which only has three bits of address masking, so
we have to derive this feature directly from the OMAP revision...

ef20677c 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: Pull prefetch engine data into sub-struct

Refactor the gpmc state structure so items relating to
the prefetch engine are in their own sub-struct and have
more useful names.

Signed-off-by: Peter Maydell <>

eee0a1c6 08/28/2011 07:37 pm Peter Maydell

omap: Wire up the DMA request line to the GPMC

Signed-off-by: Peter Maydell <>

d5c8cf99 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: Implement prefetch engine

This commit implements the prefetch engine feature of the GPMC
which can be used for NAND devices. This includes both interrupt
driven and DMA-filling modes.

Signed-off-by: Peter Maydell <>

07bc2f80 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: Clean up omap_gpmc_attach MemoryRegion conversion

Now that all callers of omap_gpmc_attach pass in a MemoryRegion*,
we can remove the base_update and unmap function pointer arguments,
and the opaque pointer that was passed into these callbacks....

3387bf55 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: Refactor omap_gpmc_cs_map and omap_gpmc_cs_unmap

Refactor the omap_gpmc_cs_map/unmap functions: * take the omap_gpmc_s* and a chipselect id rather than the
omap_gpmc_cs_file_s*, so they have access to the general gpmc
member fields * extract the base and mask from the config registers in the functions...

9c8255e1 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: GPMC_IRQSTATUS is write-one-to-clear

Fix a bug in the handling of writes to GPMC_IRQSTATUS:
it behaves as "write one to clear, writing zero is ignored".

Signed-off-by: Peter Maydell <>

77c6c736 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: Wire up the GPMC IRQ correctly

The omap_gpmc wasn't actually wiring up its IRQ, so
anything that provoked an interrupt would be using
uninitialised data for its IRQ number.

Signed-off-by: Peter Maydell <>

de8af7fe 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: Fix handling of FIFOTHRESHOLDSTATUS bit

The OMAP3 TRM is inconsistent about whether the GPMC FIFOTHRESHOLDSTATUS
bit should be set when FIFOPOINTER > FIFOTHRESHOLD or when it is >=
FIFOTHRESHOLD. Apparently the underlying functional spec from which...

b5325c27 08/28/2011 07:37 pm Juha Riihimäki

omap_gpmc: Take omap_mpu_state* in omap_gpmc_init

Take a pointer to the omap mpu state struct in omap_gpmc_init.
Some details of GPMC behaviour depend on the OMAP version we
are a part of.

Signed-off-by: Juha Riihimäki <>
[Riku Voipio: Fixes and restructuring patchset]...

7c470ff1 08/28/2011 07:37 pm Juha Riihimäki

omap_gpmc: Calculate revision from OMAP model

Signed-off-by: Juha Riihimäki <>
[Riku Voipio: Fixes and restructuring patchset]
Signed-off-by: Riku Voipio <>
[Peter Maydell: More fixes and cleanups for upstream submission]...

9ed3e1b1 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: Reindent misindented switch statements

Whitespace-only change fixing indentation.

Signed-off-by: Peter Maydell <>

2a952feb 08/28/2011 07:37 pm Peter Maydell

omap_gpmc: Support NAND devices

Support accesses to NAND devices, both by mapping them into
the GPMC address space, and via the NAND_COMMAND, NAND_ADDRESS
and NAND_DATA GPMC registers.

Signed-off-by: Peter Maydell <>

710ffe60 08/23/2011 10:51 pm Peter Maydell

hw/omap_gpmc: Don't try to map CS0 twice on reset

Remove a spurious second map of the OMAP GPMC CS0 region on reset.
This fixes an assertion failure when we try to add the region to
its container when it was already added. (The old code did not
complain about mismatched map/unmap calls, but the new MemoryRegion...

64066a8f 08/22/2011 06:21 pm Avi Kivity

omap_gpmc/nseries/tusb6010: convert to memory API

Somewhat clumsy since it needs a variable sized region.

Signed-off-by: Avi Kivity <>
Signed-off-by: Anthony Liguori <>

7267c094 08/21/2011 07:01 am Anthony Liguori

Use glib memory allocation and free functions

qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <>

2507c12a 12/11/2010 05:24 pm Alexander Graf

Add endianness as io mem parameter

As stated before, devices can be little, big or native endian. The
target endianness is not of their concern, so we need to push things
down a level.

This patch adds a parameter to cpu_register_io_memory that allows a
device to choose its endianness. For now, all devices simply choose...

f3354b0e 06/30/2010 09:41 pm cmchao

hw/omap2.c : separate gpmc(general purpose memory controller)

Signed-off-by: cmchao <>
Signed-off-by: Aurelien Jarno <>