Revision 4e7a4a4e
| b/target-mips/op.c | ||
|---|---|---|
| 1444 | 1444 |
|
| 1445 | 1445 |
void op_mtc0_watchlo0 (void) |
| 1446 | 1446 |
{
|
| 1447 |
env->CP0_WatchLo = (int32_t)T0; |
|
| 1447 |
/* Watch exceptions for instructions, data loads, data stores |
|
| 1448 |
not implemented. */ |
|
| 1449 |
env->CP0_WatchLo = (int32_t)(T0 & ~0x7); |
|
| 1448 | 1450 |
RETURN(); |
| 1449 | 1451 |
} |
| 1450 | 1452 |
|
| 1451 | 1453 |
void op_mtc0_watchhi0 (void) |
| 1452 | 1454 |
{
|
| 1453 |
env->CP0_WatchHi = T0 & 0x40FF0FF8; |
|
| 1455 |
env->CP0_WatchHi = (T0 & 0x40FF0FF8); |
|
| 1456 |
env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7); |
|
| 1454 | 1457 |
RETURN(); |
| 1455 | 1458 |
} |
| 1456 | 1459 |
|
| ... | ... | |
| 1620 | 1623 |
|
| 1621 | 1624 |
void op_dmtc0_watchlo0 (void) |
| 1622 | 1625 |
{
|
| 1623 |
env->CP0_WatchLo = T0; |
|
| 1626 |
/* Watch exceptions for instructions, data loads, data stores |
|
| 1627 |
not implemented. */ |
|
| 1628 |
env->CP0_WatchLo = T0 & ~0x7; |
|
| 1624 | 1629 |
RETURN(); |
| 1625 | 1630 |
} |
| 1626 | 1631 |
|
| b/target-mips/translate.c | ||
|---|---|---|
| 5406 | 5406 |
env->CP0_EBase = 0x80000000; |
| 5407 | 5407 |
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); |
| 5408 | 5408 |
env->CP0_WatchLo = 0; |
| 5409 |
env->CP0_WatchHi = 0; |
|
| 5409 | 5410 |
/* Count register increments in debug mode, EJTAG version 1 */ |
| 5410 | 5411 |
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); |
| 5411 | 5412 |
#endif |
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