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/*
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 * S/390 virtual CPU header
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 *
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 *  Copyright (c) 2009 Ulrich Hecht
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef CPU_S390X_H
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#define CPU_S390X_H
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#define TARGET_LONG_BITS 64
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#define ELF_MACHINE        EM_S390
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#define CPUState struct CPUS390XState
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#include "cpu-defs.h"
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#define TARGET_PAGE_BITS 12
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#define TARGET_PHYS_ADDR_SPACE_BITS 64
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#define TARGET_VIRT_ADDR_SPACE_BITS 64
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#include "cpu-all.h"
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#include "softfloat.h"
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#define NB_MMU_MODES 3
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#define MMU_MODE0_SUFFIX _primary
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#define MMU_MODE1_SUFFIX _secondary
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#define MMU_MODE2_SUFFIX _home
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#define MMU_USER_IDX 1
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#define MAX_EXT_QUEUE 16
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typedef struct PSW {
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    uint64_t mask;
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    uint64_t addr;
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} PSW;
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typedef struct ExtQueue {
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    uint32_t code;
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    uint32_t param;
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    uint32_t param64;
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} ExtQueue;
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typedef struct CPUS390XState {
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    uint64_t regs[16];        /* GP registers */
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    uint32_t aregs[16];        /* access registers */
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    uint32_t fpc;        /* floating-point control register */
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    CPU_DoubleU fregs[16]; /* FP registers */
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    float_status fpu_status; /* passed to softfloat lib */
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    PSW psw;
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    uint32_t cc;
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    uint32_t cc_op;
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    uint64_t cc_src;
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    uint64_t cc_dst;
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    uint64_t cc_vr;
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    uint64_t __excp_addr;
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    uint64_t psa;
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    uint32_t int_pgm_code;
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    uint32_t int_pgm_ilc;
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    uint32_t int_svc_code;
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    uint32_t int_svc_ilc;
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    uint64_t cregs[16]; /* control registers */
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    int pending_int;
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    ExtQueue ext_queue[MAX_EXT_QUEUE];
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    int ext_index;
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    CPU_COMMON
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    /* reset does memset(0) up to here */
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    int cpu_num;
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    uint8_t *storage_keys;
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    uint64_t tod_offset;
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    uint64_t tod_basetime;
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    QEMUTimer *tod_timer;
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    QEMUTimer *cpu_timer;
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} CPUS390XState;
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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{
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    if (newsp) {
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        env->regs[15] = newsp;
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    }
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    env->regs[0] = 0;
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}
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#endif
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/* Interrupt Codes */
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/* Program Interrupts */
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#define PGM_OPERATION                   0x0001
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#define PGM_PRIVILEGED                  0x0002
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#define PGM_EXECUTE                     0x0003
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#define PGM_PROTECTION                  0x0004
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#define PGM_ADDRESSING                  0x0005
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#define PGM_SPECIFICATION               0x0006
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#define PGM_DATA                        0x0007
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#define PGM_FIXPT_OVERFLOW              0x0008
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#define PGM_FIXPT_DIVIDE                0x0009
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#define PGM_DEC_OVERFLOW                0x000a
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#define PGM_DEC_DIVIDE                  0x000b
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#define PGM_HFP_EXP_OVERFLOW            0x000c
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#define PGM_HFP_EXP_UNDERFLOW           0x000d
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#define PGM_HFP_SIGNIFICANCE            0x000e
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#define PGM_HFP_DIVIDE                  0x000f
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#define PGM_SEGMENT_TRANS               0x0010
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#define PGM_PAGE_TRANS                  0x0011
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#define PGM_TRANS_SPEC                  0x0012
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#define PGM_SPECIAL_OP                  0x0013
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#define PGM_OPERAND                     0x0015
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#define PGM_TRACE_TABLE                 0x0016
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#define PGM_SPACE_SWITCH                0x001c
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#define PGM_HFP_SQRT                    0x001d
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#define PGM_PC_TRANS_SPEC               0x001f
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#define PGM_AFX_TRANS                   0x0020
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#define PGM_ASX_TRANS                   0x0021
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#define PGM_LX_TRANS                    0x0022
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#define PGM_EX_TRANS                    0x0023
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#define PGM_PRIM_AUTH                   0x0024
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#define PGM_SEC_AUTH                    0x0025
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#define PGM_ALET_SPEC                   0x0028
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#define PGM_ALEN_SPEC                   0x0029
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#define PGM_ALE_SEQ                     0x002a
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#define PGM_ASTE_VALID                  0x002b
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#define PGM_ASTE_SEQ                    0x002c
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#define PGM_EXT_AUTH                    0x002d
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#define PGM_STACK_FULL                  0x0030
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#define PGM_STACK_EMPTY                 0x0031
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#define PGM_STACK_SPEC                  0x0032
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#define PGM_STACK_TYPE                  0x0033
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#define PGM_STACK_OP                    0x0034
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#define PGM_ASCE_TYPE                   0x0038
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#define PGM_REG_FIRST_TRANS             0x0039
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#define PGM_REG_SEC_TRANS               0x003a
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#define PGM_REG_THIRD_TRANS             0x003b
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#define PGM_MONITOR                     0x0040
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#define PGM_PER                         0x0080
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#define PGM_CRYPTO                      0x0119
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/* External Interrupts */
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#define EXT_INTERRUPT_KEY               0x0040
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#define EXT_CLOCK_COMP                  0x1004
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#define EXT_CPU_TIMER                   0x1005
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#define EXT_MALFUNCTION                 0x1200
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#define EXT_EMERGENCY                   0x1201
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#define EXT_EXTERNAL_CALL               0x1202
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#define EXT_ETR                         0x1406
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#define EXT_SERVICE                     0x2401
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#define EXT_VIRTIO                      0x2603
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/* PSW defines */
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#undef PSW_MASK_PER
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#undef PSW_MASK_DAT
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#undef PSW_MASK_IO
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#undef PSW_MASK_EXT
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#undef PSW_MASK_KEY
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#undef PSW_SHIFT_KEY
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#undef PSW_MASK_MCHECK
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#undef PSW_MASK_WAIT
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#undef PSW_MASK_PSTATE
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#undef PSW_MASK_ASC
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#undef PSW_MASK_CC
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#undef PSW_MASK_PM
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#undef PSW_MASK_64
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#define PSW_MASK_PER            0x4000000000000000ULL
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#define PSW_MASK_DAT            0x0400000000000000ULL
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#define PSW_MASK_IO             0x0200000000000000ULL
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#define PSW_MASK_EXT            0x0100000000000000ULL
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#define PSW_MASK_KEY            0x00F0000000000000ULL
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#define PSW_SHIFT_KEY           56
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#define PSW_MASK_MCHECK         0x0004000000000000ULL
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#define PSW_MASK_WAIT           0x0002000000000000ULL
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#define PSW_MASK_PSTATE         0x0001000000000000ULL
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#define PSW_MASK_ASC            0x0000C00000000000ULL
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#define PSW_MASK_CC             0x0000300000000000ULL
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#define PSW_MASK_PM             0x00000F0000000000ULL
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#define PSW_MASK_64             0x0000000100000000ULL
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#define PSW_MASK_32             0x0000000080000000ULL
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#undef PSW_ASC_PRIMARY
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#undef PSW_ASC_ACCREG
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#undef PSW_ASC_SECONDARY
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#undef PSW_ASC_HOME
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#define PSW_ASC_PRIMARY         0x0000000000000000ULL
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#define PSW_ASC_ACCREG          0x0000400000000000ULL
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#define PSW_ASC_SECONDARY       0x0000800000000000ULL
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#define PSW_ASC_HOME            0x0000C00000000000ULL
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/* tb flags */
219

    
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#define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
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#define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
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#define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
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#define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
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#define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
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#define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
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#define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
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#define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
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#define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
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#define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
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#define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
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#define FLAG_MASK_64            (PSW_MASK_64     >> 32)
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#define FLAG_MASK_32            0x00001000
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static inline int cpu_mmu_index (CPUState *env)
235
{
236
    if (env->psw.mask & PSW_MASK_PSTATE) {
237
        return 1;
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    }
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240
    return 0;
241
}
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static inline void cpu_get_tb_cpu_state(CPUState* env, target_ulong *pc,
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                                        target_ulong *cs_base, int *flags)
245
{
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    *pc = env->psw.addr;
247
    *cs_base = 0;
248
    *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
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             ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
250
}
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252
static inline int get_ilc(uint8_t opc)
253
{
254
    switch (opc >> 6) {
255
    case 0:
256
        return 1;
257
    case 1:
258
    case 2:
259
        return 2;
260
    case 3:
261
        return 3;
262
    }
263

    
264
    return 0;
265
}
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267
#define ILC_LATER       0x20
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#define ILC_LATER_INC   0x21
269
#define ILC_LATER_INC_2 0x22
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CPUS390XState *cpu_s390x_init(const char *cpu_model);
273
void s390x_translate_init(void);
274
int cpu_s390x_exec(CPUS390XState *s);
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void cpu_s390x_close(CPUS390XState *s);
276
void do_interrupt (CPUState *env);
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278
/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
280
   is returned if the signal was handled by the virtual CPU.  */
281
int cpu_s390x_signal_handler(int host_signum, void *pinfo,
282
                           void *puc);
283
int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
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                              int mmu_idx, int is_softmuu);
285
#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
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#ifndef CONFIG_USER_ONLY
289
int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall);
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#ifdef CONFIG_KVM
292
void kvm_s390_interrupt(CPUState *env, int type, uint32_t code);
293
void kvm_s390_virtio_irq(CPUState *env, int config_change, uint64_t token);
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void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm,
295
                                 uint64_t parm64, int vm);
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#else
297
static inline void kvm_s390_interrupt(CPUState *env, int type, uint32_t code)
298
{
299
}
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301
static inline void kvm_s390_virtio_irq(CPUState *env, int config_change,
302
                                       uint64_t token)
303
{
304
}
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306
static inline void kvm_s390_interrupt_internal(CPUState *env, int type,
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                                               uint32_t parm, uint64_t parm64,
308
                                               int vm)
309
{
310
}
311
#endif
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CPUState *s390_cpu_addr2state(uint16_t cpu_addr);
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/* from s390-virtio-bus */
315
extern const target_phys_addr_t virtio_size;
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#ifndef KVM_S390_SIGP_STOP
318
#define KVM_S390_SIGP_STOP              0
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#define KVM_S390_PROGRAM_INT            0
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#define KVM_S390_SIGP_SET_PREFIX        0
321
#define KVM_S390_RESTART                0
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#define KVM_S390_INT_VIRTIO             0
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#define KVM_S390_INT_SERVICE            0
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#define KVM_S390_INT_EMERGENCY          0
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#endif
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327
#endif
328
void cpu_lock(void);
329
void cpu_unlock(void);
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331
static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
332
{
333
    env->aregs[0] = newtls >> 32;
334
    env->aregs[1] = newtls & 0xffffffffULL;
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}
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#define cpu_init cpu_s390x_init
338
#define cpu_exec cpu_s390x_exec
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#define cpu_gen_code cpu_s390x_gen_code
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#define cpu_signal_handler cpu_s390x_signal_handler
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342
#include "exec-all.h"
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344
#ifdef CONFIG_USER_ONLY
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346
#define EXCP_OPEX 1 /* operation exception (sigill) */
347
#define EXCP_SVC 2 /* supervisor call (syscall) */
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#define EXCP_ADDR 5 /* addressing exception */
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#define EXCP_SPEC 6 /* specification exception */
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351
#else
352

    
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#define EXCP_EXT 1 /* external interrupt */
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#define EXCP_SVC 2 /* supervisor call (syscall) */
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#define EXCP_PGM 3 /* program interruption */
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357
#endif /* CONFIG_USER_ONLY */
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#define INTERRUPT_EXT        (1 << 0)
360
#define INTERRUPT_TOD        (1 << 1)
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#define INTERRUPT_CPUTIMER   (1 << 2)
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/* Program Status Word.  */
364
#define S390_PSWM_REGNUM 0
365
#define S390_PSWA_REGNUM 1
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/* General Purpose Registers.  */
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#define S390_R0_REGNUM 2
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#define S390_R1_REGNUM 3
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#define S390_R2_REGNUM 4
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#define S390_R3_REGNUM 5
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#define S390_R4_REGNUM 6
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#define S390_R5_REGNUM 7
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#define S390_R6_REGNUM 8
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#define S390_R7_REGNUM 9
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#define S390_R8_REGNUM 10
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#define S390_R9_REGNUM 11
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#define S390_R10_REGNUM 12
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#define S390_R11_REGNUM 13
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#define S390_R12_REGNUM 14
380
#define S390_R13_REGNUM 15
381
#define S390_R14_REGNUM 16
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#define S390_R15_REGNUM 17
383
/* Access Registers.  */
384
#define S390_A0_REGNUM 18
385
#define S390_A1_REGNUM 19
386
#define S390_A2_REGNUM 20
387
#define S390_A3_REGNUM 21
388
#define S390_A4_REGNUM 22
389
#define S390_A5_REGNUM 23
390
#define S390_A6_REGNUM 24
391
#define S390_A7_REGNUM 25
392
#define S390_A8_REGNUM 26
393
#define S390_A9_REGNUM 27
394
#define S390_A10_REGNUM 28
395
#define S390_A11_REGNUM 29
396
#define S390_A12_REGNUM 30
397
#define S390_A13_REGNUM 31
398
#define S390_A14_REGNUM 32
399
#define S390_A15_REGNUM 33
400
/* Floating Point Control Word.  */
401
#define S390_FPC_REGNUM 34
402
/* Floating Point Registers.  */
403
#define S390_F0_REGNUM 35
404
#define S390_F1_REGNUM 36
405
#define S390_F2_REGNUM 37
406
#define S390_F3_REGNUM 38
407
#define S390_F4_REGNUM 39
408
#define S390_F5_REGNUM 40
409
#define S390_F6_REGNUM 41
410
#define S390_F7_REGNUM 42
411
#define S390_F8_REGNUM 43
412
#define S390_F9_REGNUM 44
413
#define S390_F10_REGNUM 45
414
#define S390_F11_REGNUM 46
415
#define S390_F12_REGNUM 47
416
#define S390_F13_REGNUM 48
417
#define S390_F14_REGNUM 49
418
#define S390_F15_REGNUM 50
419
/* Total.  */
420
#define S390_NUM_REGS 51
421

    
422
/* Pseudo registers -- PC and condition code.  */
423
#define S390_PC_REGNUM S390_NUM_REGS
424
#define S390_CC_REGNUM (S390_NUM_REGS+1)
425
#define S390_NUM_PSEUDO_REGS 2
426
#define S390_NUM_TOTAL_REGS (S390_NUM_REGS+2)
427

    
428

    
429

    
430
/* Program Status Word.  */
431
#define S390_PSWM_REGNUM 0
432
#define S390_PSWA_REGNUM 1
433
/* General Purpose Registers.  */
434
#define S390_R0_REGNUM 2
435
#define S390_R1_REGNUM 3
436
#define S390_R2_REGNUM 4
437
#define S390_R3_REGNUM 5
438
#define S390_R4_REGNUM 6
439
#define S390_R5_REGNUM 7
440
#define S390_R6_REGNUM 8
441
#define S390_R7_REGNUM 9
442
#define S390_R8_REGNUM 10
443
#define S390_R9_REGNUM 11
444
#define S390_R10_REGNUM 12
445
#define S390_R11_REGNUM 13
446
#define S390_R12_REGNUM 14
447
#define S390_R13_REGNUM 15
448
#define S390_R14_REGNUM 16
449
#define S390_R15_REGNUM 17
450
/* Access Registers.  */
451
#define S390_A0_REGNUM 18
452
#define S390_A1_REGNUM 19
453
#define S390_A2_REGNUM 20
454
#define S390_A3_REGNUM 21
455
#define S390_A4_REGNUM 22
456
#define S390_A5_REGNUM 23
457
#define S390_A6_REGNUM 24
458
#define S390_A7_REGNUM 25
459
#define S390_A8_REGNUM 26
460
#define S390_A9_REGNUM 27
461
#define S390_A10_REGNUM 28
462
#define S390_A11_REGNUM 29
463
#define S390_A12_REGNUM 30
464
#define S390_A13_REGNUM 31
465
#define S390_A14_REGNUM 32
466
#define S390_A15_REGNUM 33
467
/* Floating Point Control Word.  */
468
#define S390_FPC_REGNUM 34
469
/* Floating Point Registers.  */
470
#define S390_F0_REGNUM 35
471
#define S390_F1_REGNUM 36
472
#define S390_F2_REGNUM 37
473
#define S390_F3_REGNUM 38
474
#define S390_F4_REGNUM 39
475
#define S390_F5_REGNUM 40
476
#define S390_F6_REGNUM 41
477
#define S390_F7_REGNUM 42
478
#define S390_F8_REGNUM 43
479
#define S390_F9_REGNUM 44
480
#define S390_F10_REGNUM 45
481
#define S390_F11_REGNUM 46
482
#define S390_F12_REGNUM 47
483
#define S390_F13_REGNUM 48
484
#define S390_F14_REGNUM 49
485
#define S390_F15_REGNUM 50
486
/* Total.  */
487
#define S390_NUM_REGS 51
488

    
489
/* Pseudo registers -- PC and condition code.  */
490
#define S390_PC_REGNUM S390_NUM_REGS
491
#define S390_CC_REGNUM (S390_NUM_REGS+1)
492
#define S390_NUM_PSEUDO_REGS 2
493
#define S390_NUM_TOTAL_REGS (S390_NUM_REGS+2)
494

    
495
/* CC optimization */
496

    
497
enum cc_op {
498
    CC_OP_CONST0 = 0,           /* CC is 0 */
499
    CC_OP_CONST1,               /* CC is 1 */
500
    CC_OP_CONST2,               /* CC is 2 */
501
    CC_OP_CONST3,               /* CC is 3 */
502

    
503
    CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
504
    CC_OP_STATIC,               /* CC value is env->cc_op */
505

    
506
    CC_OP_NZ,                   /* env->cc_dst != 0 */
507
    CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
508
    CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
509
    CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
510
    CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
511
    CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
512
    CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
513

    
514
    CC_OP_ADD_64,               /* overflow on add (64bit) */
515
    CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
516
    CC_OP_SUB_64,               /* overflow on substraction (64bit) */
517
    CC_OP_SUBU_64,              /* overflow on unsigned substraction (64bit) */
518
    CC_OP_ABS_64,               /* sign eval on abs (64bit) */
519
    CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
520

    
521
    CC_OP_ADD_32,               /* overflow on add (32bit) */
522
    CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
523
    CC_OP_SUB_32,               /* overflow on substraction (32bit) */
524
    CC_OP_SUBU_32,              /* overflow on unsigned substraction (32bit) */
525
    CC_OP_ABS_32,               /* sign eval on abs (64bit) */
526
    CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
527

    
528
    CC_OP_COMP_32,              /* complement */
529
    CC_OP_COMP_64,              /* complement */
530

    
531
    CC_OP_TM_32,                /* test under mask (32bit) */
532
    CC_OP_TM_64,                /* test under mask (64bit) */
533

    
534
    CC_OP_LTGT_F32,             /* FP compare (32bit) */
535
    CC_OP_LTGT_F64,             /* FP compare (64bit) */
536

    
537
    CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
538
    CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
539

    
540
    CC_OP_ICM,                  /* insert characters under mask */
541
    CC_OP_SLAG,                 /* Calculate shift left signed */
542
    CC_OP_MAX
543
};
544

    
545
static const char *cc_names[] = {
546
    [CC_OP_CONST0]    = "CC_OP_CONST0",
547
    [CC_OP_CONST1]    = "CC_OP_CONST1",
548
    [CC_OP_CONST2]    = "CC_OP_CONST2",
549
    [CC_OP_CONST3]    = "CC_OP_CONST3",
550
    [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
551
    [CC_OP_STATIC]    = "CC_OP_STATIC",
552
    [CC_OP_NZ]        = "CC_OP_NZ",
553
    [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
554
    [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
555
    [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
556
    [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
557
    [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
558
    [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
559
    [CC_OP_ADD_64]    = "CC_OP_ADD_64",
560
    [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
561
    [CC_OP_SUB_64]    = "CC_OP_SUB_64",
562
    [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
563
    [CC_OP_ABS_64]    = "CC_OP_ABS_64",
564
    [CC_OP_NABS_64]   = "CC_OP_NABS_64",
565
    [CC_OP_ADD_32]    = "CC_OP_ADD_32",
566
    [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
567
    [CC_OP_SUB_32]    = "CC_OP_SUB_32",
568
    [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
569
    [CC_OP_ABS_32]    = "CC_OP_ABS_32",
570
    [CC_OP_NABS_32]   = "CC_OP_NABS_32",
571
    [CC_OP_COMP_32]   = "CC_OP_COMP_32",
572
    [CC_OP_COMP_64]   = "CC_OP_COMP_64",
573
    [CC_OP_TM_32]     = "CC_OP_TM_32",
574
    [CC_OP_TM_64]     = "CC_OP_TM_64",
575
    [CC_OP_LTGT_F32]  = "CC_OP_LTGT_F32",
576
    [CC_OP_LTGT_F64]  = "CC_OP_LTGT_F64",
577
    [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
578
    [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
579
    [CC_OP_ICM]       = "CC_OP_ICM",
580
    [CC_OP_SLAG]      = "CC_OP_SLAG",
581
};
582

    
583
static inline const char *cc_name(int cc_op)
584
{
585
    return cc_names[cc_op];
586
}
587

    
588
/* SCLP PV interface defines */
589
#define SCLP_CMDW_READ_SCP_INFO         0x00020001
590
#define SCLP_CMDW_READ_SCP_INFO_FORCED  0x00120001
591

    
592
#define SCP_LENGTH                      0x00
593
#define SCP_FUNCTION_CODE               0x02
594
#define SCP_CONTROL_MASK                0x03
595
#define SCP_RESPONSE_CODE               0x06
596
#define SCP_MEM_CODE                    0x08
597
#define SCP_INCREMENT                   0x0a
598

    
599
typedef struct LowCore
600
{
601
    /* prefix area: defined by architecture */
602
    uint32_t        ccw1[2];                  /* 0x000 */
603
    uint32_t        ccw2[4];                  /* 0x008 */
604
    uint8_t         pad1[0x80-0x18];          /* 0x018 */
605
    uint32_t        ext_params;               /* 0x080 */
606
    uint16_t        cpu_addr;                 /* 0x084 */
607
    uint16_t        ext_int_code;             /* 0x086 */
608
    uint16_t        svc_ilc;                  /* 0x088 */
609
    uint16_t        svc_code;                 /* 0x08a */
610
    uint16_t        pgm_ilc;                  /* 0x08c */
611
    uint16_t        pgm_code;                 /* 0x08e */
612
    uint32_t        data_exc_code;            /* 0x090 */
613
    uint16_t        mon_class_num;            /* 0x094 */
614
    uint16_t        per_perc_atmid;           /* 0x096 */
615
    uint64_t        per_address;              /* 0x098 */
616
    uint8_t         exc_access_id;            /* 0x0a0 */
617
    uint8_t         per_access_id;            /* 0x0a1 */
618
    uint8_t         op_access_id;             /* 0x0a2 */
619
    uint8_t         ar_access_id;             /* 0x0a3 */
620
    uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
621
    uint64_t        trans_exc_code;           /* 0x0a8 */
622
    uint64_t        monitor_code;             /* 0x0b0 */
623
    uint16_t        subchannel_id;            /* 0x0b8 */
624
    uint16_t        subchannel_nr;            /* 0x0ba */
625
    uint32_t        io_int_parm;              /* 0x0bc */
626
    uint32_t        io_int_word;              /* 0x0c0 */
627
    uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
628
    uint32_t        stfl_fac_list;            /* 0x0c8 */
629
    uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
630
    uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
631
    uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
632
    uint32_t        external_damage_code;     /* 0x0f4 */
633
    uint64_t        failing_storage_address;  /* 0x0f8 */
634
    uint8_t         pad6[0x120-0x100];        /* 0x100 */
635
    PSW             restart_old_psw;          /* 0x120 */
636
    PSW             external_old_psw;         /* 0x130 */
637
    PSW             svc_old_psw;              /* 0x140 */
638
    PSW             program_old_psw;          /* 0x150 */
639
    PSW             mcck_old_psw;             /* 0x160 */
640
    PSW             io_old_psw;               /* 0x170 */
641
    uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
642
    PSW             restart_psw;              /* 0x1a0 */
643
    PSW             external_new_psw;         /* 0x1b0 */
644
    PSW             svc_new_psw;              /* 0x1c0 */
645
    PSW             program_new_psw;          /* 0x1d0 */
646
    PSW             mcck_new_psw;             /* 0x1e0 */
647
    PSW             io_new_psw;               /* 0x1f0 */
648
    PSW             return_psw;               /* 0x200 */
649
    uint8_t         irb[64];                  /* 0x210 */
650
    uint64_t        sync_enter_timer;         /* 0x250 */
651
    uint64_t        async_enter_timer;        /* 0x258 */
652
    uint64_t        exit_timer;               /* 0x260 */
653
    uint64_t        last_update_timer;        /* 0x268 */
654
    uint64_t        user_timer;               /* 0x270 */
655
    uint64_t        system_timer;             /* 0x278 */
656
    uint64_t        last_update_clock;        /* 0x280 */
657
    uint64_t        steal_clock;              /* 0x288 */
658
    PSW             return_mcck_psw;          /* 0x290 */
659
    uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
660
    /* System info area */
661
    uint64_t        save_area[16];            /* 0xc00 */
662
    uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
663
    uint64_t        kernel_stack;             /* 0xd40 */
664
    uint64_t        thread_info;              /* 0xd48 */
665
    uint64_t        async_stack;              /* 0xd50 */
666
    uint64_t        kernel_asce;              /* 0xd58 */
667
    uint64_t        user_asce;                /* 0xd60 */
668
    uint64_t        panic_stack;              /* 0xd68 */
669
    uint64_t        user_exec_asce;           /* 0xd70 */
670
    uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
671

    
672
    /* SMP info area: defined by DJB */
673
    uint64_t        clock_comparator;         /* 0xdc0 */
674
    uint64_t        ext_call_fast;            /* 0xdc8 */
675
    uint64_t        percpu_offset;            /* 0xdd0 */
676
    uint64_t        current_task;             /* 0xdd8 */
677
    uint32_t        softirq_pending;          /* 0xde0 */
678
    uint32_t        pad_0x0de4;               /* 0xde4 */
679
    uint64_t        int_clock;                /* 0xde8 */
680
    uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
681

    
682
    /* 0xe00 is used as indicator for dump tools */
683
    /* whether the kernel died with panic() or not */
684
    uint32_t        panic_magic;              /* 0xe00 */
685

    
686
    uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
687

    
688
    /* 64 bit extparam used for pfault, diag 250 etc  */
689
    uint64_t        ext_params2;               /* 0x11B8 */
690

    
691
    uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
692

    
693
    /* System info area */
694

    
695
    uint64_t        floating_pt_save_area[16]; /* 0x1200 */
696
    uint64_t        gpregs_save_area[16];      /* 0x1280 */
697
    uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
698
    uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
699
    uint32_t        prefixreg_save_area;       /* 0x1318 */
700
    uint32_t        fpt_creg_save_area;        /* 0x131c */
701
    uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
702
    uint32_t        tod_progreg_save_area;     /* 0x1324 */
703
    uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
704
    uint32_t        clock_comp_save_area[2];   /* 0x1330 */
705
    uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
706
    uint32_t        access_regs_save_area[16]; /* 0x1340 */
707
    uint64_t        cregs_save_area[16];       /* 0x1380 */
708

    
709
    /* align to the top of the prefix area */
710

    
711
    uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
712
} __attribute__((packed)) LowCore;
713

    
714
/* STSI */
715
#define STSI_LEVEL_MASK         0x00000000f0000000ULL
716
#define STSI_LEVEL_CURRENT      0x0000000000000000ULL
717
#define STSI_LEVEL_1            0x0000000010000000ULL
718
#define STSI_LEVEL_2            0x0000000020000000ULL
719
#define STSI_LEVEL_3            0x0000000030000000ULL
720
#define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
721
#define STSI_R0_SEL1_MASK       0x00000000000000ffULL
722
#define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
723
#define STSI_R1_SEL2_MASK       0x000000000000ffffULL
724

    
725
/* Basic Machine Configuration */
726
struct sysib_111 {
727
    uint32_t res1[8];
728
    uint8_t  manuf[16];
729
    uint8_t  type[4];
730
    uint8_t  res2[12];
731
    uint8_t  model[16];
732
    uint8_t  sequence[16];
733
    uint8_t  plant[4];
734
    uint8_t  res3[156];
735
};
736

    
737
/* Basic Machine CPU */
738
struct sysib_121 {
739
    uint32_t res1[80];
740
    uint8_t  sequence[16];
741
    uint8_t  plant[4];
742
    uint8_t  res2[2];
743
    uint16_t cpu_addr;
744
    uint8_t  res3[152];
745
};
746

    
747
/* Basic Machine CPUs */
748
struct sysib_122 {
749
    uint8_t res1[32];
750
    uint32_t capability;
751
    uint16_t total_cpus;
752
    uint16_t active_cpus;
753
    uint16_t standby_cpus;
754
    uint16_t reserved_cpus;
755
    uint16_t adjustments[2026];
756
};
757

    
758
/* LPAR CPU */
759
struct sysib_221 {
760
    uint32_t res1[80];
761
    uint8_t  sequence[16];
762
    uint8_t  plant[4];
763
    uint16_t cpu_id;
764
    uint16_t cpu_addr;
765
    uint8_t  res3[152];
766
};
767

    
768
/* LPAR CPUs */
769
struct sysib_222 {
770
    uint32_t res1[32];
771
    uint16_t lpar_num;
772
    uint8_t  res2;
773
    uint8_t  lcpuc;
774
    uint16_t total_cpus;
775
    uint16_t conf_cpus;
776
    uint16_t standby_cpus;
777
    uint16_t reserved_cpus;
778
    uint8_t  name[8];
779
    uint32_t caf;
780
    uint8_t  res3[16];
781
    uint16_t dedicated_cpus;
782
    uint16_t shared_cpus;
783
    uint8_t  res4[180];
784
};
785

    
786
/* VM CPUs */
787
struct sysib_322 {
788
    uint8_t  res1[31];
789
    uint8_t  count;
790
    struct {
791
        uint8_t  res2[4];
792
        uint16_t total_cpus;
793
        uint16_t conf_cpus;
794
        uint16_t standby_cpus;
795
        uint16_t reserved_cpus;
796
        uint8_t  name[8];
797
        uint32_t caf;
798
        uint8_t  cpi[16];
799
        uint8_t  res3[24];
800
    } vm[8];
801
    uint8_t res4[3552];
802
};
803

    
804
/* MMU defines */
805
#define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
806
#define _ASCE_SUBSPACE          0x200     /* subspace group control           */
807
#define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
808
#define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
809
#define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
810
#define _ASCE_REAL_SPACE        0x20      /* real space control               */
811
#define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
812
#define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
813
#define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
814
#define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
815
#define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
816
#define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
817

    
818
#define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
819
#define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
820
#define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
821
#define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
822
#define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
823
#define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
824
#define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
825

    
826
#define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
827
#define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
828
#define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
829

    
830
#define _PAGE_RO        0x200            /* HW read-only bit  */
831
#define _PAGE_INVALID   0x400            /* HW invalid bit    */
832

    
833

    
834

    
835
/* EBCDIC handling */
836
static const uint8_t ebcdic2ascii[] = {
837
    0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F,
838
    0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
839
    0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07,
840
    0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
841
    0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B,
842
    0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07,
843
    0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04,
844
    0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A,
845
    0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86,
846
    0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21,
847
    0x26, 0x82, 0x88, 0x89, 0x8A, 0xA1, 0x8C, 0x07,
848
    0x8D, 0xE1, 0x5D, 0x24, 0x2A, 0x29, 0x3B, 0x5E,
849
    0x2D, 0x2F, 0x07, 0x8E, 0x07, 0x07, 0x07, 0x8F,
850
    0x80, 0xA5, 0x07, 0x2C, 0x25, 0x5F, 0x3E, 0x3F,
851
    0x07, 0x90, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
852
    0x70, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22,
853
    0x07, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
854
    0x68, 0x69, 0xAE, 0xAF, 0x07, 0x07, 0x07, 0xF1,
855
    0xF8, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70,
856
    0x71, 0x72, 0xA6, 0xA7, 0x91, 0x07, 0x92, 0x07,
857
    0xE6, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
858
    0x79, 0x7A, 0xAD, 0xAB, 0x07, 0x07, 0x07, 0x07,
859
    0x9B, 0x9C, 0x9D, 0xFA, 0x07, 0x07, 0x07, 0xAC,
860
    0xAB, 0x07, 0xAA, 0x7C, 0x07, 0x07, 0x07, 0x07,
861
    0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
862
    0x48, 0x49, 0x07, 0x93, 0x94, 0x95, 0xA2, 0x07,
863
    0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50,
864
    0x51, 0x52, 0x07, 0x96, 0x81, 0x97, 0xA3, 0x98,
865
    0x5C, 0xF6, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
866
    0x59, 0x5A, 0xFD, 0x07, 0x99, 0x07, 0x07, 0x07,
867
    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
868
    0x38, 0x39, 0x07, 0x07, 0x9A, 0x07, 0x07, 0x07,
869
};
870

    
871
static const uint8_t ascii2ebcdic [] = {
872
    0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F,
873
    0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
874
    0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26,
875
    0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F,
876
    0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D,
877
    0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61,
878
    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
879
    0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F,
880
    0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
881
    0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6,
882
    0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
883
    0xE7, 0xE8, 0xE9, 0xBA, 0xE0, 0xBB, 0xB0, 0x6D,
884
    0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
885
    0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96,
886
    0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6,
887
    0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07,
888
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
889
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
890
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
891
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
892
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
893
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
894
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
895
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
896
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
897
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
898
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
899
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
900
    0x3F, 0x59, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
901
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
902
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
903
    0x90, 0x3F, 0x3F, 0x3F, 0x3F, 0xEA, 0x3F, 0xFF
904
};
905

    
906
static inline void ebcdic_put(uint8_t *p, const char *ascii, int len)
907
{
908
    int i;
909

    
910
    for (i = 0; i < len; i++) {
911
        p[i] = ascii2ebcdic[(int)ascii[i]];
912
    }
913
}
914

    
915
#define SIGP_SENSE             0x01
916
#define SIGP_EXTERNAL_CALL     0x02
917
#define SIGP_EMERGENCY         0x03
918
#define SIGP_START             0x04
919
#define SIGP_STOP              0x05
920
#define SIGP_RESTART           0x06
921
#define SIGP_STOP_STORE_STATUS 0x09
922
#define SIGP_INITIAL_CPU_RESET 0x0b
923
#define SIGP_CPU_RESET         0x0c
924
#define SIGP_SET_PREFIX        0x0d
925
#define SIGP_STORE_STATUS_ADDR 0x0e
926
#define SIGP_SET_ARCH          0x12
927

    
928
/* cpu status bits */
929
#define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
930
#define SIGP_STAT_INCORRECT_STATE   0x00000200UL
931
#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
932
#define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
933
#define SIGP_STAT_STOPPED           0x00000040UL
934
#define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
935
#define SIGP_STAT_CHECK_STOP        0x00000010UL
936
#define SIGP_STAT_INOPERATIVE       0x00000004UL
937
#define SIGP_STAT_INVALID_ORDER     0x00000002UL
938
#define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
939

    
940
void load_psw(CPUState *env, uint64_t mask, uint64_t addr);
941
int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc,
942
                  target_ulong *raddr, int *flags);
943
int sclp_service_call(CPUState *env, uint32_t sccb, uint64_t code);
944
uint32_t calc_cc(CPUState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
945
                 uint64_t vr);
946

    
947
#define TARGET_HAS_ICE 1
948

    
949
/* The value of the TOD clock for 1.1.1970. */
950
#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
951

    
952
/* Converts ns to s390's clock format */
953
static inline uint64_t time2tod(uint64_t ns) {
954
    return (ns << 9) / 125;
955
}
956

    
957
static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param,
958
                                  uint64_t param64)
959
{
960
    if (env->ext_index == MAX_EXT_QUEUE - 1) {
961
        /* ugh - can't queue anymore. Let's drop. */
962
        return;
963
    }
964

    
965
    env->ext_index++;
966
    assert(env->ext_index < MAX_EXT_QUEUE);
967

    
968
    env->ext_queue[env->ext_index].code = code;
969
    env->ext_queue[env->ext_index].param = param;
970
    env->ext_queue[env->ext_index].param64 = param64;
971

    
972
    env->pending_int |= INTERRUPT_EXT;
973
    cpu_interrupt(env, CPU_INTERRUPT_HARD);
974
}
975

    
976
#endif