root / target-mips / op_template.c @ 4e9f8537
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation micro-operations templates for reg load & store for qemu.
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3 | 5fafdf24 | ths | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 6af0bf9c | bellard | |
21 | 6af0bf9c | bellard | #if defined(REG)
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22 | 6af0bf9c | bellard | void glue(op_load_gpr_T0_gpr, REG) (void) |
23 | 6af0bf9c | bellard | { |
24 | ead9360e | ths | T0 = env->gpr[REG][env->current_tc]; |
25 | 6af0bf9c | bellard | RETURN(); |
26 | 6af0bf9c | bellard | } |
27 | 6af0bf9c | bellard | |
28 | 6af0bf9c | bellard | void glue(op_store_T0_gpr_gpr, REG) (void) |
29 | 6af0bf9c | bellard | { |
30 | ead9360e | ths | env->gpr[REG][env->current_tc] = T0; |
31 | 6af0bf9c | bellard | RETURN(); |
32 | 6af0bf9c | bellard | } |
33 | 6af0bf9c | bellard | |
34 | 6af0bf9c | bellard | void glue(op_load_gpr_T1_gpr, REG) (void) |
35 | 6af0bf9c | bellard | { |
36 | ead9360e | ths | T1 = env->gpr[REG][env->current_tc]; |
37 | 6af0bf9c | bellard | RETURN(); |
38 | 6af0bf9c | bellard | } |
39 | 6af0bf9c | bellard | |
40 | 6af0bf9c | bellard | void glue(op_store_T1_gpr_gpr, REG) (void) |
41 | 6af0bf9c | bellard | { |
42 | ead9360e | ths | env->gpr[REG][env->current_tc] = T1; |
43 | 6af0bf9c | bellard | RETURN(); |
44 | 6af0bf9c | bellard | } |
45 | 6af0bf9c | bellard | |
46 | 6af0bf9c | bellard | void glue(op_load_gpr_T2_gpr, REG) (void) |
47 | 6af0bf9c | bellard | { |
48 | ead9360e | ths | T2 = env->gpr[REG][env->current_tc]; |
49 | ead9360e | ths | RETURN(); |
50 | ead9360e | ths | } |
51 | ead9360e | ths | |
52 | ead9360e | ths | |
53 | ead9360e | ths | void glue(op_load_srsgpr_T0_gpr, REG) (void) |
54 | ead9360e | ths | { |
55 | ead9360e | ths | T0 = env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf];
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56 | ead9360e | ths | RETURN(); |
57 | ead9360e | ths | } |
58 | ead9360e | ths | |
59 | ead9360e | ths | void glue(op_store_T0_srsgpr_gpr, REG) (void) |
60 | ead9360e | ths | { |
61 | ead9360e | ths | env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf] = T0;
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62 | 6af0bf9c | bellard | RETURN(); |
63 | 6af0bf9c | bellard | } |
64 | 6af0bf9c | bellard | #endif
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65 | 6af0bf9c | bellard | |
66 | 6af0bf9c | bellard | #if defined (TN)
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67 | c570fd16 | ths | #define SET_RESET(treg, tregname) \
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68 | c570fd16 | ths | void glue(op_set, tregname)(void) \ |
69 | c570fd16 | ths | { \ |
70 | c631c88c | ths | treg = (int32_t)PARAM1; \ |
71 | c570fd16 | ths | RETURN(); \ |
72 | c570fd16 | ths | } \ |
73 | c570fd16 | ths | void glue(op_reset, tregname)(void) \ |
74 | c570fd16 | ths | { \ |
75 | c570fd16 | ths | treg = 0; \
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76 | c570fd16 | ths | RETURN(); \ |
77 | c570fd16 | ths | } \ |
78 | 6af0bf9c | bellard | |
79 | c570fd16 | ths | SET_RESET(T0, _T0) |
80 | c570fd16 | ths | SET_RESET(T1, _T1) |
81 | c570fd16 | ths | SET_RESET(T2, _T2) |
82 | c570fd16 | ths | |
83 | c570fd16 | ths | #undef SET_RESET
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84 | 9b9e4393 | ths | |
85 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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86 | 9b9e4393 | ths | #define SET64(treg, tregname) \
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87 | 9b9e4393 | ths | void glue(op_set64, tregname)(void) \ |
88 | 9b9e4393 | ths | { \ |
89 | 9b9e4393 | ths | treg = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2; \
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90 | 9b9e4393 | ths | RETURN(); \ |
91 | 9b9e4393 | ths | } |
92 | 9b9e4393 | ths | |
93 | 9b9e4393 | ths | SET64(T0, _T0) |
94 | 9b9e4393 | ths | SET64(T1, _T1) |
95 | 9b9e4393 | ths | SET64(T2, _T2) |
96 | 9b9e4393 | ths | |
97 | 9b9e4393 | ths | #undef SET64
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98 | 9b9e4393 | ths | |
99 | 9b9e4393 | ths | #endif
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100 | 6af0bf9c | bellard | #endif |