Revision 4ecc3190 target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 740 | 740 |
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) |
| 741 | 741 |
{
|
| 742 | 742 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 743 |
if (SH(ctx->opcode) != 0) |
|
| 743 | 744 |
gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31)); |
| 744 | 745 |
if (Rc(ctx->opcode) != 0) |
| 745 | 746 |
gen_op_set_Rc0(); |
| ... | ... | |
| 749 | 750 |
__GEN_LOGICAL2(srw, 0x18, 0x10); |
| 750 | 751 |
|
| 751 | 752 |
/*** Floating-Point arithmetic ***/ |
| 752 |
#define _GEN_FLOAT_ACB(name, op1, op2) \
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|
| 753 |
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
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|
| 753 | 754 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \ |
| 754 | 755 |
{ \
|
| 755 | 756 |
if (!ctx->fpu_enabled) { \
|
| ... | ... | |
| 760 | 761 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
| 761 | 762 |
gen_op_load_fpr_FT1(rC(ctx->opcode)); \ |
| 762 | 763 |
gen_op_load_fpr_FT2(rB(ctx->opcode)); \ |
| 763 |
gen_op_f##name(); \ |
|
| 764 |
gen_op_f##op(); \ |
|
| 765 |
if (isfloat) { \
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|
| 766 |
gen_op_frsp(); \ |
|
| 767 |
} \ |
|
| 764 | 768 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
| 765 | 769 |
if (Rc(ctx->opcode)) \ |
| 766 | 770 |
gen_op_set_Rc1(); \ |
| 767 | 771 |
} |
| 768 | 772 |
|
| 769 | 773 |
#define GEN_FLOAT_ACB(name, op2) \ |
| 770 |
_GEN_FLOAT_ACB(name, 0x3F, op2); \
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|
| 771 |
_GEN_FLOAT_ACB(name##s, 0x3B, op2);
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|
| 774 |
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
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|
| 775 |
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
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|
| 772 | 776 |
|
| 773 |
#define _GEN_FLOAT_AB(name, op1, op2, inval) \
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|
| 777 |
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
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|
| 774 | 778 |
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
| 775 | 779 |
{ \
|
| 776 | 780 |
if (!ctx->fpu_enabled) { \
|
| ... | ... | |
| 780 | 784 |
gen_op_reset_scrfx(); \ |
| 781 | 785 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
| 782 | 786 |
gen_op_load_fpr_FT1(rB(ctx->opcode)); \ |
| 783 |
gen_op_f##name(); \ |
|
| 787 |
gen_op_f##op(); \ |
|
| 788 |
if (isfloat) { \
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|
| 789 |
gen_op_frsp(); \ |
|
| 790 |
} \ |
|
| 784 | 791 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
| 785 | 792 |
if (Rc(ctx->opcode)) \ |
| 786 | 793 |
gen_op_set_Rc1(); \ |
| 787 | 794 |
} |
| 788 | 795 |
#define GEN_FLOAT_AB(name, op2, inval) \ |
| 789 |
_GEN_FLOAT_AB(name, 0x3F, op2, inval); \
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|
| 790 |
_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
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|
| 796 |
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
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| 797 |
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
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|
| 791 | 798 |
|
| 792 |
#define _GEN_FLOAT_AC(name, op1, op2, inval) \
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|
| 799 |
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
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|
| 793 | 800 |
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
| 794 | 801 |
{ \
|
| 795 | 802 |
if (!ctx->fpu_enabled) { \
|
| ... | ... | |
| 799 | 806 |
gen_op_reset_scrfx(); \ |
| 800 | 807 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
| 801 | 808 |
gen_op_load_fpr_FT1(rC(ctx->opcode)); \ |
| 802 |
gen_op_f##name(); \ |
|
| 809 |
gen_op_f##op(); \ |
|
| 810 |
if (isfloat) { \
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|
| 811 |
gen_op_frsp(); \ |
|
| 812 |
} \ |
|
| 803 | 813 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
| 804 | 814 |
if (Rc(ctx->opcode)) \ |
| 805 | 815 |
gen_op_set_Rc1(); \ |
| 806 | 816 |
} |
| 807 | 817 |
#define GEN_FLOAT_AC(name, op2, inval) \ |
| 808 |
_GEN_FLOAT_AC(name, 0x3F, op2, inval); \
|
|
| 809 |
_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
|
|
| 818 |
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
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|
| 819 |
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
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|
| 810 | 820 |
|
| 811 | 821 |
#define GEN_FLOAT_B(name, op2, op3) \ |
| 812 | 822 |
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \ |
| ... | ... | |
| 823 | 833 |
gen_op_set_Rc1(); \ |
| 824 | 834 |
} |
| 825 | 835 |
|
| 826 |
#define GEN_FLOAT_BS(name, op2) \
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|
| 827 |
GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
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|
| 836 |
#define GEN_FLOAT_BS(name, op1, op2) \
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| 837 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
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|
| 828 | 838 |
{ \
|
| 829 | 839 |
if (!ctx->fpu_enabled) { \
|
| 830 | 840 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
| ... | ... | |
| 840 | 850 |
|
| 841 | 851 |
/* fadd - fadds */ |
| 842 | 852 |
GEN_FLOAT_AB(add, 0x15, 0x000007C0); |
| 843 |
/* fdiv */ |
|
| 853 |
/* fdiv - fdivs */
|
|
| 844 | 854 |
GEN_FLOAT_AB(div, 0x12, 0x000007C0); |
| 845 |
/* fmul */ |
|
| 855 |
/* fmul - fmuls */
|
|
| 846 | 856 |
GEN_FLOAT_AC(mul, 0x19, 0x0000F800); |
| 847 | 857 |
|
| 848 | 858 |
/* fres */ |
| 849 |
GEN_FLOAT_BS(res, 0x18); |
|
| 859 |
GEN_FLOAT_BS(res, 0x3B, 0x18);
|
|
| 850 | 860 |
|
| 851 | 861 |
/* frsqrte */ |
| 852 |
GEN_FLOAT_BS(rsqrte, 0x1A); |
|
| 862 |
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
|
|
| 853 | 863 |
|
| 854 | 864 |
/* fsel */ |
| 855 |
_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
|
|
| 856 |
/* fsub */ |
|
| 865 |
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
|
|
| 866 |
/* fsub - fsubs */
|
|
| 857 | 867 |
GEN_FLOAT_AB(sub, 0x14, 0x000007C0); |
| 858 | 868 |
/* Optional: */ |
| 859 | 869 |
/* fsqrt */ |
| 860 |
GEN_FLOAT_BS(sqrt, 0x16); |
|
| 870 |
GEN_FLOAT_BS(sqrt, 0x3F, 0x16);
|
|
| 861 | 871 |
|
| 862 | 872 |
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT) |
| 863 | 873 |
{
|
| ... | ... | |
| 867 | 877 |
} |
| 868 | 878 |
gen_op_reset_scrfx(); |
| 869 | 879 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); |
| 870 |
gen_op_fsqrts(); |
|
| 880 |
gen_op_fsqrt(); |
|
| 881 |
gen_op_frsp(); |
|
| 871 | 882 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); |
| 872 | 883 |
if (Rc(ctx->opcode)) |
| 873 | 884 |
gen_op_set_Rc1(); |
| 874 | 885 |
} |
| 875 | 886 |
|
| 876 | 887 |
/*** Floating-Point multiply-and-add ***/ |
| 877 |
/* fmadd */ |
|
| 888 |
/* fmadd - fmadds */
|
|
| 878 | 889 |
GEN_FLOAT_ACB(madd, 0x1D); |
| 879 |
/* fmsub */ |
|
| 890 |
/* fmsub - fmsubs */
|
|
| 880 | 891 |
GEN_FLOAT_ACB(msub, 0x1C); |
| 881 |
/* fnmadd */ |
|
| 892 |
/* fnmadd - fnmadds */
|
|
| 882 | 893 |
GEN_FLOAT_ACB(nmadd, 0x1F); |
| 883 |
/* fnmsub */ |
|
| 894 |
/* fnmsub - fnmsubs */
|
|
| 884 | 895 |
GEN_FLOAT_ACB(nmsub, 0x1E); |
| 885 | 896 |
|
| 886 | 897 |
/*** Floating-Point round & convert ***/ |
| ... | ... | |
| 1426 | 1437 |
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
| 1427 | 1438 |
{ \
|
| 1428 | 1439 |
uint32_t simm = SIMM(ctx->opcode); \ |
| 1440 |
if (!ctx->fpu_enabled) { \
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|
| 1441 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
|
| 1442 |
return; \ |
|
| 1443 |
} \ |
|
| 1429 | 1444 |
if (rA(ctx->opcode) == 0) { \
|
| 1430 | 1445 |
gen_op_set_T0(simm); \ |
| 1431 | 1446 |
} else { \
|
| ... | ... | |
| 1441 | 1456 |
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
| 1442 | 1457 |
{ \
|
| 1443 | 1458 |
uint32_t simm = SIMM(ctx->opcode); \ |
| 1459 |
if (!ctx->fpu_enabled) { \
|
|
| 1460 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
|
| 1461 |
return; \ |
|
| 1462 |
} \ |
|
| 1444 | 1463 |
if (rA(ctx->opcode) == 0 || \ |
| 1445 | 1464 |
rA(ctx->opcode) == rD(ctx->opcode)) { \
|
| 1446 | 1465 |
RET_INVAL(ctx); \ |
| ... | ... | |
| 1457 | 1476 |
#define GEN_LDUXF(width, opc) \ |
| 1458 | 1477 |
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
| 1459 | 1478 |
{ \
|
| 1479 |
if (!ctx->fpu_enabled) { \
|
|
| 1480 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
|
| 1481 |
return; \ |
|
| 1482 |
} \ |
|
| 1460 | 1483 |
if (rA(ctx->opcode) == 0 || \ |
| 1461 | 1484 |
rA(ctx->opcode) == rD(ctx->opcode)) { \
|
| 1462 | 1485 |
RET_INVAL(ctx); \ |
| ... | ... | |
| 1473 | 1496 |
#define GEN_LDXF(width, opc2, opc3) \ |
| 1474 | 1497 |
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
| 1475 | 1498 |
{ \
|
| 1499 |
if (!ctx->fpu_enabled) { \
|
|
| 1500 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
|
| 1501 |
return; \ |
|
| 1502 |
} \ |
|
| 1476 | 1503 |
if (rA(ctx->opcode) == 0) { \
|
| 1477 | 1504 |
gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
| 1478 | 1505 |
} else { \
|
| ... | ... | |
| 1501 | 1528 |
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
| 1502 | 1529 |
{ \
|
| 1503 | 1530 |
uint32_t simm = SIMM(ctx->opcode); \ |
| 1531 |
if (!ctx->fpu_enabled) { \
|
|
| 1532 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
|
| 1533 |
return; \ |
|
| 1534 |
} \ |
|
| 1504 | 1535 |
if (rA(ctx->opcode) == 0) { \
|
| 1505 | 1536 |
gen_op_set_T0(simm); \ |
| 1506 | 1537 |
} else { \
|
| ... | ... | |
| 1516 | 1547 |
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
| 1517 | 1548 |
{ \
|
| 1518 | 1549 |
uint32_t simm = SIMM(ctx->opcode); \ |
| 1550 |
if (!ctx->fpu_enabled) { \
|
|
| 1551 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
|
| 1552 |
return; \ |
|
| 1553 |
} \ |
|
| 1519 | 1554 |
if (rA(ctx->opcode) == 0) { \
|
| 1520 | 1555 |
RET_INVAL(ctx); \ |
| 1521 | 1556 |
return; \ |
| ... | ... | |
| 1531 | 1566 |
#define GEN_STUXF(width, opc) \ |
| 1532 | 1567 |
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
| 1533 | 1568 |
{ \
|
| 1569 |
if (!ctx->fpu_enabled) { \
|
|
| 1570 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
|
| 1571 |
return; \ |
|
| 1572 |
} \ |
|
| 1534 | 1573 |
if (rA(ctx->opcode) == 0) { \
|
| 1535 | 1574 |
RET_INVAL(ctx); \ |
| 1536 | 1575 |
return; \ |
| ... | ... | |
| 1546 | 1585 |
#define GEN_STXF(width, opc2, opc3) \ |
| 1547 | 1586 |
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
| 1548 | 1587 |
{ \
|
| 1588 |
if (!ctx->fpu_enabled) { \
|
|
| 1589 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
|
| 1590 |
return; \ |
|
| 1591 |
} \ |
|
| 1549 | 1592 |
if (rA(ctx->opcode) == 0) { \
|
| 1550 | 1593 |
gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
| 1551 | 1594 |
} else { \
|
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