root / target-ppc / helper.c @ 4ecc3190
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/*
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* PPC emulation helpers for qemu.
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*
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* Copyright (c) 2003 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_EXCEPTIONS
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|
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/*****************************************************************************/
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/* PPC MMU emulation */
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|
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/* Perform BAT hit & translation */
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static int get_bat (CPUState *env, uint32_t *real, int *prot, |
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uint32_t virtual, int rw, int type) |
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{
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uint32_t *BATlt, *BATut, *BATu, *BATl; |
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uint32_t base, BEPIl, BEPIu, bl; |
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int i;
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int ret = -1; |
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|
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#if defined (DEBUG_BATS)
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if (loglevel > 0) { |
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fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual); |
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} |
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#endif
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switch (type) {
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case ACCESS_CODE:
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BATlt = env->IBAT[1];
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BATut = env->IBAT[0];
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break;
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default:
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BATlt = env->DBAT[1];
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BATut = env->DBAT[0];
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break;
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} |
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#if defined (DEBUG_BATS)
|
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if (loglevel > 0) { |
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fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual); |
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} |
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#endif
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base = virtual & 0xFFFC0000;
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for (i = 0; i < 4; i++) { |
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BATu = &BATut[i]; |
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BATl = &BATlt[i]; |
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15; |
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#if defined (DEBUG_BATS)
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if (loglevel > 0) { |
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fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
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*BATu, *BATl); |
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} |
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#endif
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if ((virtual & 0xF0000000) == BEPIu && |
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((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
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/* BAT matches */
|
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if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
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(msr_pr == 1 && (*BATu & 0x00000001))) { |
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/* Get physical address */
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*real = (*BATl & 0xF0000000) |
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((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
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(virtual & 0x0001F000);
|
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if (*BATl & 0x00000001) |
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*prot = PAGE_READ; |
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if (*BATl & 0x00000002) |
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*prot = PAGE_WRITE | PAGE_READ; |
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#if defined (DEBUG_BATS)
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if (loglevel > 0) { |
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fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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i, *real, *prot & PAGE_READ ? 'R' : '-', |
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*prot & PAGE_WRITE ? 'W' : '-'); |
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} |
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#endif
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ret = 0;
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break;
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} |
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} |
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} |
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if (ret < 0) { |
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#if defined (DEBUG_BATS)
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printf("no BAT match for 0x%08x:\n", virtual);
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for (i = 0; i < 4; i++) { |
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BATu = &BATut[i]; |
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BATl = &BATlt[i]; |
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15; |
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printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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"0x%08x 0x%08x 0x%08x\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
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*BATu, *BATl, BEPIu, BEPIl, bl); |
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} |
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#endif
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} |
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/* No hit */
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return ret;
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} |
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|
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/* PTE table lookup */
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static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va, |
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int h, int key, int rw) |
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{
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uint32_t pte0, pte1, keep = 0, access = 0; |
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int i, good = -1, store = 0; |
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int ret = -1; /* No entry found */ |
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|
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for (i = 0; i < 8; i++) { |
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pte0 = ldl_phys(base + (i * 8));
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pte1 = ldl_phys(base + (i * 8) + 4); |
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#if defined (DEBUG_MMU)
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if (loglevel > 0) { |
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fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
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"%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1, |
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pte0 >> 31, h, (pte0 >> 6) & 1, va); |
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} |
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#endif
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/* Check validity and table match */
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if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) { |
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/* Check vsid & api */
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if ((pte0 & 0x7FFFFFBF) == va) { |
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if (good == -1) { |
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good = i; |
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keep = pte1; |
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} else {
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/* All matches should have equal RPN, WIMG & PP */
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if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) { |
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if (loglevel > 0) |
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fprintf(logfile, "Bad RPN/WIMG/PP\n");
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return -1; |
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} |
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} |
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/* Check access rights */
|
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if (key == 0) { |
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access = PAGE_READ; |
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if ((pte1 & 0x00000003) != 0x3) |
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access |= PAGE_WRITE; |
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} else {
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switch (pte1 & 0x00000003) { |
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case 0x0: |
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access = 0;
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break;
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case 0x1: |
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case 0x3: |
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access = PAGE_READ; |
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break;
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case 0x2: |
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access = PAGE_READ | PAGE_WRITE; |
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break;
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} |
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} |
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if (ret < 0) { |
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if ((rw == 0 && (access & PAGE_READ)) || |
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(rw == 1 && (access & PAGE_WRITE))) {
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#if defined (DEBUG_MMU)
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if (loglevel > 0) |
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fprintf(logfile, "PTE access granted !\n");
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#endif
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good = i; |
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keep = pte1; |
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ret = 0;
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} else {
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/* Access right violation */
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ret = -2;
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#if defined (DEBUG_MMU)
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if (loglevel > 0) |
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fprintf(logfile, "PTE access rejected\n");
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#endif
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} |
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*prot = access; |
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} |
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} |
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} |
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} |
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if (good != -1) { |
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*RPN = keep & 0xFFFFF000;
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#if defined (DEBUG_MMU)
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if (loglevel > 0) { |
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fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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*RPN, *prot, ret); |
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} |
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#endif
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/* Update page flags */
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if (!(keep & 0x00000100)) { |
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/* Access flag */
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keep |= 0x00000100;
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store = 1;
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} |
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if (!(keep & 0x00000080)) { |
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if (rw && ret == 0) { |
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/* Change flag */
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keep |= 0x00000080;
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store = 1;
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} else {
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/* Force page fault for first write access */
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*prot &= ~PAGE_WRITE; |
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} |
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} |
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if (store) {
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stl_phys_notdirty(base + (good * 8) + 4, keep); |
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} |
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} |
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return ret;
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} |
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|
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static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask) |
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{
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return (sdr1 & 0xFFFF0000) | (hash & mask); |
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} |
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|
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/* Perform segment based translation */
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static int get_segment (CPUState *env, uint32_t *real, int *prot, |
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uint32_t virtual, int rw, int type) |
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{
|
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uint32_t pg_addr, sdr, ptem, vsid, pgidx; |
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uint32_t hash, mask; |
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uint32_t sr; |
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int key;
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int ret = -1, ret2; |
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|
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sr = env->sr[virtual >> 28];
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#if defined (DEBUG_MMU)
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if (loglevel > 0) { |
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fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
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"lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
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virtual, virtual >> 28, sr, env->nip,
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env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
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} |
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#endif
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key = (((sr & 0x20000000) && msr_pr == 1) || |
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((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
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if ((sr & 0x80000000) == 0) { |
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#if defined (DEBUG_MMU)
|
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if (loglevel > 0) |
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fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
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key, sr & 0x10000000);
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#endif
|
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || (sr & 0x10000000) == 0) { |
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/* Page address translation */
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vsid = sr & 0x00FFFFFF;
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pgidx = (virtual >> 12) & 0xFFFF; |
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sdr = env->sdr1; |
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hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6; |
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mask = ((sdr & 0x000001FF) << 16) | 0xFFC0; |
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pg_addr = get_pgaddr(sdr, hash, mask); |
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ptem = (vsid << 7) | (pgidx >> 10); |
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#if defined (DEBUG_MMU)
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if (loglevel > 0) { |
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fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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"hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
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pg_addr); |
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} |
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#endif
|
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/* Primary table lookup */
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ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
|
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if (ret < 0) { |
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/* Secondary table lookup */
|
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hash = (~hash) & 0x01FFFFC0;
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pg_addr = get_pgaddr(sdr, hash, mask); |
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#if defined (DEBUG_MMU)
|
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if (virtual != 0xEFFFFFFF && loglevel > 0) { |
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fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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"hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
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hash, pg_addr); |
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} |
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#endif
|
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ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
|
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if (ret2 != -1) |
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ret = ret2; |
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} |
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} else {
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#if defined (DEBUG_MMU)
|
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if (loglevel > 0) |
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fprintf(logfile, "No access allowed\n");
|
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#endif
|
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ret = -3;
|
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} |
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} else {
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#if defined (DEBUG_MMU)
|
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if (loglevel > 0) |
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fprintf(logfile, "direct store...\n");
|
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#endif
|
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/* Direct-store segment : absolutely *BUGGY* for now */
|
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switch (type) {
|
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case ACCESS_INT:
|
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/* Integer load/store : only access allowed */
|
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break;
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case ACCESS_CODE:
|
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/* No code fetch is allowed in direct-store areas */
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return -4; |
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case ACCESS_FLOAT:
|
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/* Floating point load/store */
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return -4; |
| 315 |
case ACCESS_RES:
|
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/* lwarx, ldarx or srwcx. */
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return -4; |
| 318 |
case ACCESS_CACHE:
|
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
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/* Should make the instruction do no-op.
|
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* As it already do no-op, it's quite easy :-)
|
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*/
|
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*real = virtual; |
| 324 |
return 0; |
| 325 |
case ACCESS_EXT:
|
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/* eciwx or ecowx */
|
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return -4; |
| 328 |
default:
|
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if (logfile) {
|
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fprintf(logfile, "ERROR: instruction should not need "
|
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"address translation\n");
|
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} |
| 333 |
printf("ERROR: instruction should not need "
|
| 334 |
"address translation\n");
|
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return -4; |
| 336 |
} |
| 337 |
if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) { |
| 338 |
*real = virtual; |
| 339 |
ret = 2;
|
| 340 |
} else {
|
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ret = -2;
|
| 342 |
} |
| 343 |
} |
| 344 |
|
| 345 |
return ret;
|
| 346 |
} |
| 347 |
|
| 348 |
int get_physical_address (CPUState *env, uint32_t *physical, int *prot, |
| 349 |
uint32_t address, int rw, int access_type) |
| 350 |
{
|
| 351 |
int ret;
|
| 352 |
#if 0
|
| 353 |
if (loglevel > 0) {
|
| 354 |
fprintf(logfile, "%s\n", __func__);
|
| 355 |
}
|
| 356 |
#endif
|
| 357 |
if ((access_type == ACCESS_CODE && msr_ir == 0) || |
| 358 |
(access_type != ACCESS_CODE && msr_dr == 0)) {
|
| 359 |
/* No address translation */
|
| 360 |
*physical = address & ~0xFFF;
|
| 361 |
*prot = PAGE_READ | PAGE_WRITE; |
| 362 |
ret = 0;
|
| 363 |
} else {
|
| 364 |
/* Try to find a BAT */
|
| 365 |
ret = get_bat(env, physical, prot, address, rw, access_type); |
| 366 |
if (ret < 0) { |
| 367 |
/* We didn't match any BAT entry */
|
| 368 |
ret = get_segment(env, physical, prot, address, rw, access_type); |
| 369 |
} |
| 370 |
} |
| 371 |
#if 0
|
| 372 |
if (loglevel > 0) {
|
| 373 |
fprintf(logfile, "%s address %08x => %08x\n",
|
| 374 |
__func__, address, *physical);
|
| 375 |
}
|
| 376 |
#endif
|
| 377 |
return ret;
|
| 378 |
} |
| 379 |
|
| 380 |
#if defined(CONFIG_USER_ONLY)
|
| 381 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
| 382 |
{
|
| 383 |
return addr;
|
| 384 |
} |
| 385 |
#else
|
| 386 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
| 387 |
{
|
| 388 |
uint32_t phys_addr; |
| 389 |
int prot;
|
| 390 |
|
| 391 |
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
| 392 |
return -1; |
| 393 |
return phys_addr;
|
| 394 |
} |
| 395 |
#endif
|
| 396 |
|
| 397 |
#if !defined(CONFIG_USER_ONLY)
|
| 398 |
|
| 399 |
#define MMUSUFFIX _mmu
|
| 400 |
#define GETPC() (__builtin_return_address(0)) |
| 401 |
|
| 402 |
#define SHIFT 0 |
| 403 |
#include "softmmu_template.h" |
| 404 |
|
| 405 |
#define SHIFT 1 |
| 406 |
#include "softmmu_template.h" |
| 407 |
|
| 408 |
#define SHIFT 2 |
| 409 |
#include "softmmu_template.h" |
| 410 |
|
| 411 |
#define SHIFT 3 |
| 412 |
#include "softmmu_template.h" |
| 413 |
|
| 414 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
| 415 |
NULL, it means that the function was called in C code (i.e. not
|
| 416 |
from generated code or from helper.c) */
|
| 417 |
/* XXX: fix it to restore all registers */
|
| 418 |
void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
| 419 |
{
|
| 420 |
TranslationBlock *tb; |
| 421 |
CPUState *saved_env; |
| 422 |
unsigned long pc; |
| 423 |
int ret;
|
| 424 |
|
| 425 |
/* XXX: hack to restore env in all cases, even if not called from
|
| 426 |
generated code */
|
| 427 |
saved_env = env; |
| 428 |
env = cpu_single_env; |
| 429 |
#if 0
|
| 430 |
{
|
| 431 |
unsigned long tlb_addrr, tlb_addrw;
|
| 432 |
int index;
|
| 433 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
| 434 |
tlb_addrr = env->tlb_read[is_user][index].address;
|
| 435 |
tlb_addrw = env->tlb_write[is_user][index].address;
|
| 436 |
if (loglevel) {
|
| 437 |
fprintf(logfile,
|
| 438 |
"%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
| 439 |
"(0x%08lx 0x%08lx)\n", __func__, env,
|
| 440 |
&env->tlb_read[is_user][index], index, addr,
|
| 441 |
tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
| 442 |
tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
| 443 |
}
|
| 444 |
}
|
| 445 |
#endif
|
| 446 |
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
| 447 |
if (ret) {
|
| 448 |
if (retaddr) {
|
| 449 |
/* now we have a real cpu fault */
|
| 450 |
pc = (unsigned long)retaddr; |
| 451 |
tb = tb_find_pc(pc); |
| 452 |
if (tb) {
|
| 453 |
/* the PC is inside the translated code. It means that we have
|
| 454 |
a virtual CPU fault */
|
| 455 |
cpu_restore_state(tb, env, pc, NULL);
|
| 456 |
} |
| 457 |
} |
| 458 |
do_raise_exception_err(env->exception_index, env->error_code); |
| 459 |
} |
| 460 |
#if 0
|
| 461 |
{
|
| 462 |
unsigned long tlb_addrr, tlb_addrw;
|
| 463 |
int index;
|
| 464 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
| 465 |
tlb_addrr = env->tlb_read[is_user][index].address;
|
| 466 |
tlb_addrw = env->tlb_write[is_user][index].address;
|
| 467 |
printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
| 468 |
"(0x%08lx 0x%08lx)\n", __func__, env,
|
| 469 |
&env->tlb_read[is_user][index], index, addr,
|
| 470 |
tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
| 471 |
tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
| 472 |
}
|
| 473 |
#endif
|
| 474 |
env = saved_env; |
| 475 |
} |
| 476 |
|
| 477 |
void cpu_ppc_init_mmu(CPUState *env)
|
| 478 |
{
|
| 479 |
/* Nothing to do: all translation are disabled */
|
| 480 |
} |
| 481 |
#endif
|
| 482 |
|
| 483 |
/* Perform address translation */
|
| 484 |
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
| 485 |
int is_user, int is_softmmu) |
| 486 |
{
|
| 487 |
uint32_t physical; |
| 488 |
int prot;
|
| 489 |
int exception = 0, error_code = 0; |
| 490 |
int access_type;
|
| 491 |
int ret = 0; |
| 492 |
|
| 493 |
if (rw == 2) { |
| 494 |
/* code access */
|
| 495 |
rw = 0;
|
| 496 |
access_type = ACCESS_CODE; |
| 497 |
} else {
|
| 498 |
/* data access */
|
| 499 |
/* XXX: put correct access by using cpu_restore_state()
|
| 500 |
correctly */
|
| 501 |
access_type = ACCESS_INT; |
| 502 |
// access_type = env->access_type;
|
| 503 |
} |
| 504 |
if (env->user_mode_only) {
|
| 505 |
/* user mode only emulation */
|
| 506 |
ret = -2;
|
| 507 |
goto do_fault;
|
| 508 |
} |
| 509 |
ret = get_physical_address(env, &physical, &prot, |
| 510 |
address, rw, access_type); |
| 511 |
if (ret == 0) { |
| 512 |
ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
|
| 513 |
is_user, is_softmmu); |
| 514 |
} else if (ret < 0) { |
| 515 |
do_fault:
|
| 516 |
#if defined (DEBUG_MMU)
|
| 517 |
if (loglevel > 0) |
| 518 |
cpu_dump_state(env, logfile, fprintf, 0);
|
| 519 |
#endif
|
| 520 |
if (access_type == ACCESS_CODE) {
|
| 521 |
exception = EXCP_ISI; |
| 522 |
switch (ret) {
|
| 523 |
case -1: |
| 524 |
/* No matches in page tables */
|
| 525 |
error_code = EXCP_ISI_TRANSLATE; |
| 526 |
break;
|
| 527 |
case -2: |
| 528 |
/* Access rights violation */
|
| 529 |
error_code = EXCP_ISI_PROT; |
| 530 |
break;
|
| 531 |
case -3: |
| 532 |
/* No execute protection violation */
|
| 533 |
error_code = EXCP_ISI_NOEXEC; |
| 534 |
break;
|
| 535 |
case -4: |
| 536 |
/* Direct store exception */
|
| 537 |
/* No code fetch is allowed in direct-store areas */
|
| 538 |
error_code = EXCP_ISI_DIRECT; |
| 539 |
break;
|
| 540 |
} |
| 541 |
} else {
|
| 542 |
exception = EXCP_DSI; |
| 543 |
switch (ret) {
|
| 544 |
case -1: |
| 545 |
/* No matches in page tables */
|
| 546 |
error_code = EXCP_DSI_TRANSLATE; |
| 547 |
break;
|
| 548 |
case -2: |
| 549 |
/* Access rights violation */
|
| 550 |
error_code = EXCP_DSI_PROT; |
| 551 |
break;
|
| 552 |
case -4: |
| 553 |
/* Direct store exception */
|
| 554 |
switch (access_type) {
|
| 555 |
case ACCESS_FLOAT:
|
| 556 |
/* Floating point load/store */
|
| 557 |
exception = EXCP_ALIGN; |
| 558 |
error_code = EXCP_ALIGN_FP; |
| 559 |
break;
|
| 560 |
case ACCESS_RES:
|
| 561 |
/* lwarx, ldarx or srwcx. */
|
| 562 |
exception = EXCP_DSI; |
| 563 |
error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT; |
| 564 |
break;
|
| 565 |
case ACCESS_EXT:
|
| 566 |
/* eciwx or ecowx */
|
| 567 |
exception = EXCP_DSI; |
| 568 |
error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | |
| 569 |
EXCP_DSI_ECXW; |
| 570 |
break;
|
| 571 |
default:
|
| 572 |
printf("DSI: invalid exception (%d)\n", ret);
|
| 573 |
exception = EXCP_PROGRAM; |
| 574 |
error_code = EXCP_INVAL | EXCP_INVAL_INVAL; |
| 575 |
break;
|
| 576 |
} |
| 577 |
} |
| 578 |
if (rw)
|
| 579 |
error_code |= EXCP_DSI_STORE; |
| 580 |
/* Store fault address */
|
| 581 |
env->spr[DAR] = address; |
| 582 |
} |
| 583 |
#if 0
|
| 584 |
printf("%s: set exception to %d %02x\n",
|
| 585 |
__func__, exception, error_code);
|
| 586 |
#endif
|
| 587 |
env->exception_index = exception; |
| 588 |
env->error_code = error_code; |
| 589 |
ret = 1;
|
| 590 |
} |
| 591 |
return ret;
|
| 592 |
} |
| 593 |
|
| 594 |
uint32_t _load_xer (CPUState *env) |
| 595 |
{
|
| 596 |
return (xer_so << XER_SO) |
|
| 597 |
(xer_ov << XER_OV) | |
| 598 |
(xer_ca << XER_CA) | |
| 599 |
(xer_bc << XER_BC); |
| 600 |
} |
| 601 |
|
| 602 |
void _store_xer (CPUState *env, uint32_t value)
|
| 603 |
{
|
| 604 |
xer_so = (value >> XER_SO) & 0x01;
|
| 605 |
xer_ov = (value >> XER_OV) & 0x01;
|
| 606 |
xer_ca = (value >> XER_CA) & 0x01;
|
| 607 |
xer_bc = (value >> XER_BC) & 0x1f;
|
| 608 |
} |
| 609 |
|
| 610 |
uint32_t _load_msr (CPUState *env) |
| 611 |
{
|
| 612 |
return (msr_pow << MSR_POW) |
|
| 613 |
(msr_ile << MSR_ILE) | |
| 614 |
(msr_ee << MSR_EE) | |
| 615 |
(msr_pr << MSR_PR) | |
| 616 |
(msr_fp << MSR_FP) | |
| 617 |
(msr_me << MSR_ME) | |
| 618 |
(msr_fe0 << MSR_FE0) | |
| 619 |
(msr_se << MSR_SE) | |
| 620 |
(msr_be << MSR_BE) | |
| 621 |
(msr_fe1 << MSR_FE1) | |
| 622 |
(msr_ip << MSR_IP) | |
| 623 |
(msr_ir << MSR_IR) | |
| 624 |
(msr_dr << MSR_DR) | |
| 625 |
(msr_ri << MSR_RI) | |
| 626 |
(msr_le << MSR_LE); |
| 627 |
} |
| 628 |
|
| 629 |
void _store_msr (CPUState *env, uint32_t value)
|
| 630 |
{
|
| 631 |
#if 0 // TRY
|
| 632 |
if (((value >> MSR_IR) & 0x01) != msr_ir ||
|
| 633 |
((value >> MSR_DR) & 0x01) != msr_dr)
|
| 634 |
{
|
| 635 |
/* Flush all tlb when changing translation mode or privilege level */
|
| 636 |
tlb_flush(env, 1);
|
| 637 |
}
|
| 638 |
#endif
|
| 639 |
msr_pow = (value >> MSR_POW) & 0x03;
|
| 640 |
msr_ile = (value >> MSR_ILE) & 0x01;
|
| 641 |
msr_ee = (value >> MSR_EE) & 0x01;
|
| 642 |
msr_pr = (value >> MSR_PR) & 0x01;
|
| 643 |
msr_fp = (value >> MSR_FP) & 0x01;
|
| 644 |
msr_me = (value >> MSR_ME) & 0x01;
|
| 645 |
msr_fe0 = (value >> MSR_FE0) & 0x01;
|
| 646 |
msr_se = (value >> MSR_SE) & 0x01;
|
| 647 |
msr_be = (value >> MSR_BE) & 0x01;
|
| 648 |
msr_fe1 = (value >> MSR_FE1) & 0x01;
|
| 649 |
msr_ip = (value >> MSR_IP) & 0x01;
|
| 650 |
msr_ir = (value >> MSR_IR) & 0x01;
|
| 651 |
msr_dr = (value >> MSR_DR) & 0x01;
|
| 652 |
msr_ri = (value >> MSR_RI) & 0x01;
|
| 653 |
msr_le = (value >> MSR_LE) & 0x01;
|
| 654 |
/* XXX: should enter PM state if msr_pow has been set */
|
| 655 |
} |
| 656 |
|
| 657 |
#if defined (CONFIG_USER_ONLY)
|
| 658 |
void do_interrupt (CPUState *env)
|
| 659 |
{
|
| 660 |
env->exception_index = -1;
|
| 661 |
} |
| 662 |
#else
|
| 663 |
void do_interrupt (CPUState *env)
|
| 664 |
{
|
| 665 |
uint32_t msr; |
| 666 |
int excp;
|
| 667 |
|
| 668 |
excp = env->exception_index; |
| 669 |
msr = _load_msr(env); |
| 670 |
#if defined (DEBUG_EXCEPTIONS)
|
| 671 |
if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) |
| 672 |
{
|
| 673 |
if (loglevel > 0) { |
| 674 |
fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
| 675 |
env->nip, excp << 8, env->error_code);
|
| 676 |
} |
| 677 |
if (loglevel > 0) |
| 678 |
cpu_dump_state(env, logfile, fprintf, 0);
|
| 679 |
} |
| 680 |
#endif
|
| 681 |
if (loglevel & CPU_LOG_INT) {
|
| 682 |
fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
| 683 |
env->nip, excp << 8, env->error_code);
|
| 684 |
} |
| 685 |
/* Generate informations in save/restore registers */
|
| 686 |
switch (excp) {
|
| 687 |
case EXCP_NONE:
|
| 688 |
/* Do nothing */
|
| 689 |
#if defined (DEBUG_EXCEPTIONS)
|
| 690 |
printf("%s: escape EXCP_NONE\n", __func__);
|
| 691 |
#endif
|
| 692 |
return;
|
| 693 |
case EXCP_RESET:
|
| 694 |
if (msr_ip)
|
| 695 |
excp += 0xFFC00;
|
| 696 |
goto store_next;
|
| 697 |
case EXCP_MACHINE_CHECK:
|
| 698 |
if (msr_me == 0) { |
| 699 |
cpu_abort(env, "Machine check exception while not allowed\n");
|
| 700 |
} |
| 701 |
msr_me = 0;
|
| 702 |
break;
|
| 703 |
case EXCP_DSI:
|
| 704 |
/* Store exception cause */
|
| 705 |
/* data location address has been stored
|
| 706 |
* when the fault has been detected
|
| 707 |
*/
|
| 708 |
msr &= ~0xFFFF0000;
|
| 709 |
env->spr[DSISR] = 0;
|
| 710 |
if (env->error_code & EXCP_DSI_TRANSLATE)
|
| 711 |
env->spr[DSISR] |= 0x40000000;
|
| 712 |
else if (env->error_code & EXCP_DSI_PROT) |
| 713 |
env->spr[DSISR] |= 0x08000000;
|
| 714 |
else if (env->error_code & EXCP_DSI_NOTSUP) { |
| 715 |
env->spr[DSISR] |= 0x80000000;
|
| 716 |
if (env->error_code & EXCP_DSI_DIRECT)
|
| 717 |
env->spr[DSISR] |= 0x04000000;
|
| 718 |
} |
| 719 |
if (env->error_code & EXCP_DSI_STORE)
|
| 720 |
env->spr[DSISR] |= 0x02000000;
|
| 721 |
if ((env->error_code & 0xF) == EXCP_DSI_DABR) |
| 722 |
env->spr[DSISR] |= 0x00400000;
|
| 723 |
if (env->error_code & EXCP_DSI_ECXW)
|
| 724 |
env->spr[DSISR] |= 0x00100000;
|
| 725 |
#if defined (DEBUG_EXCEPTIONS)
|
| 726 |
if (loglevel) {
|
| 727 |
fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
|
| 728 |
env->spr[DSISR], env->spr[DAR]); |
| 729 |
} else {
|
| 730 |
printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
|
| 731 |
env->spr[DSISR], env->spr[DAR], env->nip); |
| 732 |
} |
| 733 |
#endif
|
| 734 |
goto store_next;
|
| 735 |
case EXCP_ISI:
|
| 736 |
/* Store exception cause */
|
| 737 |
msr &= ~0xFFFF0000;
|
| 738 |
if (env->error_code == EXCP_ISI_TRANSLATE)
|
| 739 |
msr |= 0x40000000;
|
| 740 |
else if (env->error_code == EXCP_ISI_NOEXEC || |
| 741 |
env->error_code == EXCP_ISI_GUARD || |
| 742 |
env->error_code == EXCP_ISI_DIRECT) |
| 743 |
msr |= 0x10000000;
|
| 744 |
else
|
| 745 |
msr |= 0x08000000;
|
| 746 |
#if defined (DEBUG_EXCEPTIONS)
|
| 747 |
if (loglevel) {
|
| 748 |
fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
|
| 749 |
msr, env->nip); |
| 750 |
} else {
|
| 751 |
printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
|
| 752 |
msr, env->nip, env->spr[V_TBL]); |
| 753 |
} |
| 754 |
#endif
|
| 755 |
goto store_next;
|
| 756 |
case EXCP_EXTERNAL:
|
| 757 |
if (msr_ee == 0) { |
| 758 |
#if defined (DEBUG_EXCEPTIONS)
|
| 759 |
if (loglevel > 0) { |
| 760 |
fprintf(logfile, "Skipping hardware interrupt\n");
|
| 761 |
} |
| 762 |
#endif
|
| 763 |
/* Requeue it */
|
| 764 |
do_raise_exception(EXCP_EXTERNAL); |
| 765 |
return;
|
| 766 |
} |
| 767 |
goto store_next;
|
| 768 |
case EXCP_ALIGN:
|
| 769 |
/* Store exception cause */
|
| 770 |
/* Get rS/rD and rA from faulting opcode */
|
| 771 |
env->spr[DSISR] |= |
| 772 |
(ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
| 773 |
/* data location address has been stored
|
| 774 |
* when the fault has been detected
|
| 775 |
*/
|
| 776 |
goto store_current;
|
| 777 |
case EXCP_PROGRAM:
|
| 778 |
msr &= ~0xFFFF0000;
|
| 779 |
switch (env->error_code & ~0xF) { |
| 780 |
case EXCP_FP:
|
| 781 |
if (msr_fe0 == 0 && msr_fe1 == 0) { |
| 782 |
#if defined (DEBUG_EXCEPTIONS)
|
| 783 |
printf("Ignore floating point exception\n");
|
| 784 |
#endif
|
| 785 |
return;
|
| 786 |
} |
| 787 |
msr |= 0x00100000;
|
| 788 |
/* Set FX */
|
| 789 |
env->fpscr[7] |= 0x8; |
| 790 |
/* Finally, update FEX */
|
| 791 |
if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
| 792 |
((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
| 793 |
env->fpscr[7] |= 0x4; |
| 794 |
break;
|
| 795 |
case EXCP_INVAL:
|
| 796 |
// printf("Invalid instruction at 0x%08x\n", env->nip);
|
| 797 |
msr |= 0x00080000;
|
| 798 |
break;
|
| 799 |
case EXCP_PRIV:
|
| 800 |
msr |= 0x00040000;
|
| 801 |
break;
|
| 802 |
case EXCP_TRAP:
|
| 803 |
msr |= 0x00020000;
|
| 804 |
break;
|
| 805 |
default:
|
| 806 |
/* Should never occur */
|
| 807 |
break;
|
| 808 |
} |
| 809 |
msr |= 0x00010000;
|
| 810 |
goto store_current;
|
| 811 |
case EXCP_NO_FP:
|
| 812 |
msr &= ~0xFFFF0000;
|
| 813 |
goto store_current;
|
| 814 |
case EXCP_DECR:
|
| 815 |
if (msr_ee == 0) { |
| 816 |
/* Requeue it */
|
| 817 |
do_raise_exception(EXCP_DECR); |
| 818 |
return;
|
| 819 |
} |
| 820 |
goto store_next;
|
| 821 |
case EXCP_SYSCALL:
|
| 822 |
if (loglevel & CPU_LOG_INT) {
|
| 823 |
fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
| 824 |
env->gpr[0], env->gpr[3], env->gpr[4], |
| 825 |
env->gpr[5], env->gpr[6]); |
| 826 |
if (env->gpr[0] == 4 && env->gpr[3] == 1) { |
| 827 |
int len, addr, i;
|
| 828 |
uint8_t c; |
| 829 |
|
| 830 |
fprintf(logfile, "write: ");
|
| 831 |
addr = env->gpr[4];
|
| 832 |
len = env->gpr[5];
|
| 833 |
if (len > 64) |
| 834 |
len = 64;
|
| 835 |
for(i = 0; i < len; i++) { |
| 836 |
c = 0;
|
| 837 |
cpu_memory_rw_debug(env, addr + i, &c, 1, 0); |
| 838 |
if (c < 32 || c > 126) |
| 839 |
c = '.';
|
| 840 |
fprintf(logfile, "%c", c);
|
| 841 |
} |
| 842 |
fprintf(logfile, "\n");
|
| 843 |
} |
| 844 |
} |
| 845 |
goto store_next;
|
| 846 |
case EXCP_TRACE:
|
| 847 |
goto store_next;
|
| 848 |
case EXCP_FP_ASSIST:
|
| 849 |
goto store_next;
|
| 850 |
case EXCP_MTMSR:
|
| 851 |
/* Nothing to do */
|
| 852 |
return;
|
| 853 |
case EXCP_BRANCH:
|
| 854 |
/* Nothing to do */
|
| 855 |
return;
|
| 856 |
case EXCP_RFI:
|
| 857 |
/* Restore user-mode state */
|
| 858 |
#if defined (DEBUG_EXCEPTIONS)
|
| 859 |
if (msr_pr == 1) |
| 860 |
printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
|
| 861 |
#endif
|
| 862 |
return;
|
| 863 |
store_current:
|
| 864 |
/* SRR0 is set to current instruction */
|
| 865 |
env->spr[SRR0] = (uint32_t)env->nip - 4;
|
| 866 |
break;
|
| 867 |
store_next:
|
| 868 |
/* SRR0 is set to next instruction */
|
| 869 |
env->spr[SRR0] = (uint32_t)env->nip; |
| 870 |
break;
|
| 871 |
} |
| 872 |
env->spr[SRR1] = msr; |
| 873 |
/* reload MSR with correct bits */
|
| 874 |
msr_pow = 0;
|
| 875 |
msr_ee = 0;
|
| 876 |
msr_pr = 0;
|
| 877 |
msr_fp = 0;
|
| 878 |
msr_fe0 = 0;
|
| 879 |
msr_se = 0;
|
| 880 |
msr_be = 0;
|
| 881 |
msr_fe1 = 0;
|
| 882 |
msr_ir = 0;
|
| 883 |
msr_dr = 0;
|
| 884 |
msr_ri = 0;
|
| 885 |
msr_le = msr_ile; |
| 886 |
/* Jump to handler */
|
| 887 |
env->nip = excp << 8;
|
| 888 |
env->exception_index = EXCP_NONE; |
| 889 |
/* Invalidate all TLB as we may have changed translation mode */
|
| 890 |
/* ensure that no TB jump will be modified as
|
| 891 |
the program flow was changed */
|
| 892 |
#ifdef __sparc__
|
| 893 |
tmp_T0 = 0;
|
| 894 |
#else
|
| 895 |
T0 = 0;
|
| 896 |
#endif
|
| 897 |
env->exception_index = -1;
|
| 898 |
} |
| 899 |
#endif /* !CONFIG_USER_ONLY */ |