Revision 4f5e19e6 hw/grackle_pci.c
| b/hw/grackle_pci.c | ||
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#include "sysbus.h" |
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#include "ppc_mac.h" |
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#include "pci.h" |
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#include "pci_host.h" |
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/* debug Grackle */ |
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//#define DEBUG_GRACKLE |
| ... | ... | |
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#define GRACKLE_DPRINTF(fmt, ...) |
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#endif |
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typedef target_phys_addr_t pci_addr_t; |
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#include "pci_host.h" |
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typedef struct GrackleState {
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SysBusDevice busdev; |
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PCIHostState host_state; |
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&pci_grackle_config_readl, |
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}; |
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static CPUWriteMemoryFunc * const pci_grackle_write[] = {
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&pci_host_data_writeb, |
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&pci_host_data_writew, |
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&pci_host_data_writel, |
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}; |
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static CPUReadMemoryFunc * const pci_grackle_read[] = {
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&pci_host_data_readb, |
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&pci_host_data_readw, |
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&pci_host_data_readl, |
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}; |
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/* Don't know if this matches real hardware, but it agrees with OHW. */ |
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static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) |
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{
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| ... | ... | |
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pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, |
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pci_grackle_config_write, s); |
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pci_mem_data = cpu_register_io_memory(pci_grackle_read, |
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pci_grackle_write, |
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&s->host_state); |
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pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
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sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
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sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
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|
| ... | ... | |
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pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, |
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pci_grackle_config_write, s); |
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pci_mem_data = cpu_register_io_memory(pci_grackle_read, |
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pci_grackle_write, |
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&s->host_state); |
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pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
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sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
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sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
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return 0; |
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