Revision 4f5e19e6 hw/unin_pci.c
| b/hw/unin_pci.c | ||
|---|---|---|
| 24 | 24 |
#include "hw.h" |
| 25 | 25 |
#include "ppc_mac.h" |
| 26 | 26 |
#include "pci.h" |
| 27 |
#include "pci_host.h" |
|
| 27 | 28 |
|
| 28 | 29 |
/* debug UniNorth */ |
| 29 | 30 |
//#define DEBUG_UNIN |
| ... | ... | |
| 35 | 36 |
#define UNIN_DPRINTF(fmt, ...) |
| 36 | 37 |
#endif |
| 37 | 38 |
|
| 38 |
typedef target_phys_addr_t pci_addr_t; |
|
| 39 |
#include "pci_host.h" |
|
| 40 |
|
|
| 41 | 39 |
typedef struct UNINState {
|
| 42 | 40 |
SysBusDevice busdev; |
| 43 | 41 |
PCIHostState host_state; |
| ... | ... | |
| 83 | 81 |
&pci_unin_main_config_readl, |
| 84 | 82 |
}; |
| 85 | 83 |
|
| 86 |
static CPUWriteMemoryFunc * const pci_unin_main_write[] = {
|
|
| 87 |
&pci_host_data_writeb, |
|
| 88 |
&pci_host_data_writew, |
|
| 89 |
&pci_host_data_writel, |
|
| 90 |
}; |
|
| 91 |
|
|
| 92 |
static CPUReadMemoryFunc * const pci_unin_main_read[] = {
|
|
| 93 |
&pci_host_data_readb, |
|
| 94 |
&pci_host_data_readw, |
|
| 95 |
&pci_host_data_readl, |
|
| 96 |
}; |
|
| 97 |
|
|
| 98 | 84 |
static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, |
| 99 | 85 |
uint32_t val) |
| 100 | 86 |
{
|
| ... | ... | |
| 123 | 109 |
&pci_unin_config_readl, |
| 124 | 110 |
}; |
| 125 | 111 |
|
| 126 |
static CPUWriteMemoryFunc * const pci_unin_write[] = {
|
|
| 127 |
&pci_host_data_writeb, |
|
| 128 |
&pci_host_data_writew, |
|
| 129 |
&pci_host_data_writel, |
|
| 130 |
}; |
|
| 131 |
|
|
| 132 |
static CPUReadMemoryFunc * const pci_unin_read[] = {
|
|
| 133 |
&pci_host_data_readb, |
|
| 134 |
&pci_host_data_readw, |
|
| 135 |
&pci_host_data_readl, |
|
| 136 |
}; |
|
| 137 |
|
|
| 138 | 112 |
/* Don't know if this matches real hardware, but it agrees with OHW. */ |
| 139 | 113 |
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
| 140 | 114 |
{
|
| ... | ... | |
| 180 | 154 |
|
| 181 | 155 |
pci_mem_config = cpu_register_io_memory(pci_unin_main_config_read, |
| 182 | 156 |
pci_unin_main_config_write, s); |
| 183 |
pci_mem_data = cpu_register_io_memory(pci_unin_main_read, |
|
| 184 |
pci_unin_main_write, &s->host_state); |
|
| 157 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
|
| 185 | 158 |
|
| 186 | 159 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 187 | 160 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| ... | ... | |
| 202 | 175 |
// XXX: s = &pci_bridge[2]; |
| 203 | 176 |
pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
| 204 | 177 |
pci_unin_config_write, s); |
| 205 |
pci_mem_data = cpu_register_io_memory(pci_unin_main_read, |
|
| 206 |
pci_unin_main_write, &s->host_state); |
|
| 178 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
|
| 207 | 179 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 208 | 180 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| 209 | 181 |
return 0; |
| ... | ... | |
| 219 | 191 |
|
| 220 | 192 |
pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
| 221 | 193 |
pci_unin_config_write, s); |
| 222 |
pci_mem_data = cpu_register_io_memory(pci_unin_main_read, |
|
| 223 |
pci_unin_main_write, &s->host_state); |
|
| 194 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
|
| 224 | 195 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 225 | 196 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| 226 | 197 |
return 0; |
| ... | ... | |
| 236 | 207 |
|
| 237 | 208 |
pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
| 238 | 209 |
pci_unin_config_write, s); |
| 239 |
pci_mem_data = cpu_register_io_memory(pci_unin_read, |
|
| 240 |
pci_unin_write, s); |
|
| 210 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
|
| 241 | 211 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 242 | 212 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| 243 | 213 |
return 0; |
Also available in: Unified diff