root / target-sparc / cpu.h @ 4f690853
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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | af7bf89b | bellard | #include "config.h" |
5 | af7bf89b | bellard | |
6 | af7bf89b | bellard | #if !defined(TARGET_SPARC64)
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7 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
8 | af7bf89b | bellard | #define TARGET_FPREGS 32 |
9 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
10 | af7bf89b | bellard | #else
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11 | af7bf89b | bellard | #define TARGET_LONG_BITS 64 |
12 | af7bf89b | bellard | #define TARGET_FPREGS 64 |
13 | 33b37802 | blueswir1 | #define TARGET_PAGE_BITS 13 /* 8k */ |
14 | af7bf89b | bellard | #endif
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15 | 3cf1e035 | bellard | |
16 | c2764719 | pbrook | #define CPUState struct CPUSPARCState |
17 | c2764719 | pbrook | |
18 | 7a3f1944 | bellard | #include "cpu-defs.h" |
19 | 7a3f1944 | bellard | |
20 | 7a0e1f41 | bellard | #include "softfloat.h" |
21 | 7a0e1f41 | bellard | |
22 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
23 | 1fddef4b | bellard | |
24 | 9042c0e2 | ths | #if !defined(TARGET_SPARC64)
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25 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARC
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26 | 9042c0e2 | ths | #else
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27 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARCV9
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28 | 9042c0e2 | ths | #endif
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29 | 9042c0e2 | ths | |
30 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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31 | 7a3f1944 | bellard | |
32 | cf495bcf | bellard | /* trap definitions */
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33 | 3475187d | bellard | #ifndef TARGET_SPARC64
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34 | 878d3096 | bellard | #define TT_TFAULT 0x01 |
35 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
36 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
37 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
38 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
39 | 5fafdf24 | ths | #define TT_WIN_UNF 0x06 |
40 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x07 |
41 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
42 | 878d3096 | bellard | #define TT_DFAULT 0x09 |
43 | e32f879d | blueswir1 | #define TT_TOVF 0x0a |
44 | 878d3096 | bellard | #define TT_EXTINT 0x10 |
45 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x21 |
46 | 64a88d5d | blueswir1 | #define TT_UNIMP_FLUSH 0x25 |
47 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x29 |
48 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
49 | fcc72045 | blueswir1 | #define TT_NCP_INSN 0x24 |
50 | cf495bcf | bellard | #define TT_TRAP 0x80 |
51 | 3475187d | bellard | #else
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52 | 8194f35a | Igor Kovalenko | #define TT_POWER_ON_RESET 0x01 |
53 | 3475187d | bellard | #define TT_TFAULT 0x08 |
54 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x0a |
55 | 3475187d | bellard | #define TT_ILL_INSN 0x10 |
56 | 64a88d5d | blueswir1 | #define TT_UNIMP_FLUSH TT_ILL_INSN
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57 | 3475187d | bellard | #define TT_PRIV_INSN 0x11 |
58 | 3475187d | bellard | #define TT_NFPU_INSN 0x20 |
59 | 3475187d | bellard | #define TT_FP_EXCP 0x21 |
60 | e32f879d | blueswir1 | #define TT_TOVF 0x23 |
61 | 3475187d | bellard | #define TT_CLRWIN 0x24 |
62 | 3475187d | bellard | #define TT_DIV_ZERO 0x28 |
63 | 3475187d | bellard | #define TT_DFAULT 0x30 |
64 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x32 |
65 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x34 |
66 | 83469015 | bellard | #define TT_PRIV_ACT 0x37 |
67 | 3475187d | bellard | #define TT_EXTINT 0x40 |
68 | 74b9decc | blueswir1 | #define TT_IVEC 0x60 |
69 | e19e4efe | blueswir1 | #define TT_TMISS 0x64 |
70 | e19e4efe | blueswir1 | #define TT_DMISS 0x68 |
71 | 74b9decc | blueswir1 | #define TT_DPROT 0x6c |
72 | 3475187d | bellard | #define TT_SPILL 0x80 |
73 | 3475187d | bellard | #define TT_FILL 0xc0 |
74 | 3475187d | bellard | #define TT_WOTHER 0x10 |
75 | 3475187d | bellard | #define TT_TRAP 0x100 |
76 | 3475187d | bellard | #endif
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77 | 7a3f1944 | bellard | |
78 | 4b8b8b76 | blueswir1 | #define PSR_NEG_SHIFT 23 |
79 | 4b8b8b76 | blueswir1 | #define PSR_NEG (1 << PSR_NEG_SHIFT) |
80 | 4b8b8b76 | blueswir1 | #define PSR_ZERO_SHIFT 22 |
81 | 4b8b8b76 | blueswir1 | #define PSR_ZERO (1 << PSR_ZERO_SHIFT) |
82 | 4b8b8b76 | blueswir1 | #define PSR_OVF_SHIFT 21 |
83 | 4b8b8b76 | blueswir1 | #define PSR_OVF (1 << PSR_OVF_SHIFT) |
84 | 4b8b8b76 | blueswir1 | #define PSR_CARRY_SHIFT 20 |
85 | 4b8b8b76 | blueswir1 | #define PSR_CARRY (1 << PSR_CARRY_SHIFT) |
86 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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87 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
88 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
89 | e8af50a3 | bellard | #define PSR_S (1<<7) |
90 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
91 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
92 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
93 | e8af50a3 | bellard | |
94 | 8393617c | Blue Swirl | #define CC_SRC (env->cc_src)
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95 | 8393617c | Blue Swirl | #define CC_SRC2 (env->cc_src2)
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96 | 8393617c | Blue Swirl | #define CC_DST (env->cc_dst)
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97 | 8393617c | Blue Swirl | #define CC_OP (env->cc_op)
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98 | 8393617c | Blue Swirl | |
99 | 8393617c | Blue Swirl | enum {
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100 | 8393617c | Blue Swirl | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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101 | 8393617c | Blue Swirl | CC_OP_FLAGS, /* all cc are back in status register */
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102 | 8393617c | Blue Swirl | CC_OP_DIV, /* modify N, Z and V, C = 0*/
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103 | 8393617c | Blue Swirl | CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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104 | 8393617c | Blue Swirl | CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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105 | 8393617c | Blue Swirl | CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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106 | 8393617c | Blue Swirl | CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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107 | 8393617c | Blue Swirl | CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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108 | 8393617c | Blue Swirl | CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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109 | 8393617c | Blue Swirl | CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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110 | 8393617c | Blue Swirl | CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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111 | 8393617c | Blue Swirl | CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
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112 | 8393617c | Blue Swirl | CC_OP_NB, |
113 | 8393617c | Blue Swirl | }; |
114 | 8393617c | Blue Swirl | |
115 | e8af50a3 | bellard | /* Trap base register */
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116 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
117 | e8af50a3 | bellard | |
118 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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119 | 5210977a | Igor Kovalenko | #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ |
120 | 5210977a | Igor Kovalenko | #define PS_IG (1<<11) /* v9, zero on UA2007 */ |
121 | 5210977a | Igor Kovalenko | #define PS_MG (1<<10) /* v9, zero on UA2007 */ |
122 | 5210977a | Igor Kovalenko | #define PS_CLE (1<<9) /* UA2007 */ |
123 | 5210977a | Igor Kovalenko | #define PS_TLE (1<<8) /* UA2007 */ |
124 | 6ef905f6 | blueswir1 | #define PS_RMO (1<<7) |
125 | 5210977a | Igor Kovalenko | #define PS_RED (1<<5) /* v9, zero on UA2007 */ |
126 | 5210977a | Igor Kovalenko | #define PS_PEF (1<<4) /* enable fpu */ |
127 | 5210977a | Igor Kovalenko | #define PS_AM (1<<3) /* address mask */ |
128 | 3475187d | bellard | #define PS_PRIV (1<<2) |
129 | 3475187d | bellard | #define PS_IE (1<<1) |
130 | 5210977a | Igor Kovalenko | #define PS_AG (1<<0) /* v9, zero on UA2007 */ |
131 | a80dde08 | bellard | |
132 | a80dde08 | bellard | #define FPRS_FEF (1<<2) |
133 | 6f27aba6 | blueswir1 | |
134 | 6f27aba6 | blueswir1 | #define HS_PRIV (1<<2) |
135 | 3475187d | bellard | #endif
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136 | 3475187d | bellard | |
137 | e8af50a3 | bellard | /* Fcc */
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138 | ba6a9d8c | blueswir1 | #define FSR_RD1 (1ULL << 31) |
139 | ba6a9d8c | blueswir1 | #define FSR_RD0 (1ULL << 30) |
140 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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141 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
142 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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143 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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144 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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145 | e8af50a3 | bellard | |
146 | ba6a9d8c | blueswir1 | #define FSR_NVM (1ULL << 27) |
147 | ba6a9d8c | blueswir1 | #define FSR_OFM (1ULL << 26) |
148 | ba6a9d8c | blueswir1 | #define FSR_UFM (1ULL << 25) |
149 | ba6a9d8c | blueswir1 | #define FSR_DZM (1ULL << 24) |
150 | ba6a9d8c | blueswir1 | #define FSR_NXM (1ULL << 23) |
151 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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152 | e8af50a3 | bellard | |
153 | ba6a9d8c | blueswir1 | #define FSR_NVA (1ULL << 9) |
154 | ba6a9d8c | blueswir1 | #define FSR_OFA (1ULL << 8) |
155 | ba6a9d8c | blueswir1 | #define FSR_UFA (1ULL << 7) |
156 | ba6a9d8c | blueswir1 | #define FSR_DZA (1ULL << 6) |
157 | ba6a9d8c | blueswir1 | #define FSR_NXA (1ULL << 5) |
158 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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159 | e8af50a3 | bellard | |
160 | ba6a9d8c | blueswir1 | #define FSR_NVC (1ULL << 4) |
161 | ba6a9d8c | blueswir1 | #define FSR_OFC (1ULL << 3) |
162 | ba6a9d8c | blueswir1 | #define FSR_UFC (1ULL << 2) |
163 | ba6a9d8c | blueswir1 | #define FSR_DZC (1ULL << 1) |
164 | ba6a9d8c | blueswir1 | #define FSR_NXC (1ULL << 0) |
165 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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166 | e8af50a3 | bellard | |
167 | ba6a9d8c | blueswir1 | #define FSR_FTT2 (1ULL << 16) |
168 | ba6a9d8c | blueswir1 | #define FSR_FTT1 (1ULL << 15) |
169 | ba6a9d8c | blueswir1 | #define FSR_FTT0 (1ULL << 14) |
170 | 47ad35f1 | blueswir1 | //gcc warns about constant overflow for ~FSR_FTT_MASK
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171 | 47ad35f1 | blueswir1 | //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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172 | 47ad35f1 | blueswir1 | #ifdef TARGET_SPARC64
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173 | 47ad35f1 | blueswir1 | #define FSR_FTT_NMASK 0xfffffffffffe3fffULL |
174 | 47ad35f1 | blueswir1 | #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL |
175 | 3a3b925d | blueswir1 | #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL |
176 | 3a3b925d | blueswir1 | #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL |
177 | 3a3b925d | blueswir1 | #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL |
178 | 47ad35f1 | blueswir1 | #else
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179 | 47ad35f1 | blueswir1 | #define FSR_FTT_NMASK 0xfffe3fffULL |
180 | 47ad35f1 | blueswir1 | #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL |
181 | 3a3b925d | blueswir1 | #define FSR_LDFSR_OLDMASK 0x000fc000ULL |
182 | 47ad35f1 | blueswir1 | #endif
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183 | 3a3b925d | blueswir1 | #define FSR_LDFSR_MASK 0xcfc00fffULL |
184 | ba6a9d8c | blueswir1 | #define FSR_FTT_IEEE_EXCP (1ULL << 14) |
185 | ba6a9d8c | blueswir1 | #define FSR_FTT_UNIMPFPOP (3ULL << 14) |
186 | ba6a9d8c | blueswir1 | #define FSR_FTT_SEQ_ERROR (4ULL << 14) |
187 | ba6a9d8c | blueswir1 | #define FSR_FTT_INVAL_FPR (6ULL << 14) |
188 | e8af50a3 | bellard | |
189 | 4b8b8b76 | blueswir1 | #define FSR_FCC1_SHIFT 11 |
190 | ba6a9d8c | blueswir1 | #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) |
191 | 4b8b8b76 | blueswir1 | #define FSR_FCC0_SHIFT 10 |
192 | ba6a9d8c | blueswir1 | #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) |
193 | e8af50a3 | bellard | |
194 | e8af50a3 | bellard | /* MMU */
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195 | 0f8a249a | blueswir1 | #define MMU_E (1<<0) |
196 | 0f8a249a | blueswir1 | #define MMU_NF (1<<1) |
197 | e8af50a3 | bellard | |
198 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
199 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
200 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
201 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
202 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
203 | e8af50a3 | bellard | |
204 | 0f8a249a | blueswir1 | #define PG_ACCESSED_BIT 5 |
205 | 0f8a249a | blueswir1 | #define PG_MODIFIED_BIT 6 |
206 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
207 | e8af50a3 | bellard | |
208 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
209 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
210 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
211 | e8af50a3 | bellard | |
212 | 1a14026e | blueswir1 | /* 3 <= NWINDOWS <= 32. */
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213 | 1a14026e | blueswir1 | #define MIN_NWINDOWS 3 |
214 | 1a14026e | blueswir1 | #define MAX_NWINDOWS 32 |
215 | cf495bcf | bellard | |
216 | 6f27aba6 | blueswir1 | #if !defined(TARGET_SPARC64)
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217 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
218 | 6f27aba6 | blueswir1 | #else
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219 | 6f27aba6 | blueswir1 | #define NB_MMU_MODES 3 |
220 | 375ee38b | blueswir1 | typedef struct trap_state { |
221 | 375ee38b | blueswir1 | uint64_t tpc; |
222 | 375ee38b | blueswir1 | uint64_t tnpc; |
223 | 375ee38b | blueswir1 | uint64_t tstate; |
224 | 375ee38b | blueswir1 | uint32_t tt; |
225 | 375ee38b | blueswir1 | } trap_state; |
226 | 6f27aba6 | blueswir1 | #endif
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227 | 6ebbf390 | j_mayer | |
228 | 5578ceab | blueswir1 | typedef struct sparc_def_t { |
229 | 5578ceab | blueswir1 | const char *name; |
230 | 5578ceab | blueswir1 | target_ulong iu_version; |
231 | 5578ceab | blueswir1 | uint32_t fpu_version; |
232 | 5578ceab | blueswir1 | uint32_t mmu_version; |
233 | 5578ceab | blueswir1 | uint32_t mmu_bm; |
234 | 5578ceab | blueswir1 | uint32_t mmu_ctpr_mask; |
235 | 5578ceab | blueswir1 | uint32_t mmu_cxr_mask; |
236 | 5578ceab | blueswir1 | uint32_t mmu_sfsr_mask; |
237 | 5578ceab | blueswir1 | uint32_t mmu_trcr_mask; |
238 | 963262de | blueswir1 | uint32_t mxcc_version; |
239 | 5578ceab | blueswir1 | uint32_t features; |
240 | 5578ceab | blueswir1 | uint32_t nwindows; |
241 | 5578ceab | blueswir1 | uint32_t maxtl; |
242 | 5578ceab | blueswir1 | } sparc_def_t; |
243 | 5578ceab | blueswir1 | |
244 | 5578ceab | blueswir1 | #define CPU_FEATURE_FLOAT (1 << 0) |
245 | 5578ceab | blueswir1 | #define CPU_FEATURE_FLOAT128 (1 << 1) |
246 | 5578ceab | blueswir1 | #define CPU_FEATURE_SWAP (1 << 2) |
247 | 5578ceab | blueswir1 | #define CPU_FEATURE_MUL (1 << 3) |
248 | 5578ceab | blueswir1 | #define CPU_FEATURE_DIV (1 << 4) |
249 | 5578ceab | blueswir1 | #define CPU_FEATURE_FLUSH (1 << 5) |
250 | 5578ceab | blueswir1 | #define CPU_FEATURE_FSQRT (1 << 6) |
251 | 5578ceab | blueswir1 | #define CPU_FEATURE_FMUL (1 << 7) |
252 | 5578ceab | blueswir1 | #define CPU_FEATURE_VIS1 (1 << 8) |
253 | 5578ceab | blueswir1 | #define CPU_FEATURE_VIS2 (1 << 9) |
254 | 5578ceab | blueswir1 | #define CPU_FEATURE_FSMULD (1 << 10) |
255 | 5578ceab | blueswir1 | #define CPU_FEATURE_HYPV (1 << 11) |
256 | 5578ceab | blueswir1 | #define CPU_FEATURE_CMT (1 << 12) |
257 | 5578ceab | blueswir1 | #define CPU_FEATURE_GL (1 << 13) |
258 | 5578ceab | blueswir1 | #ifndef TARGET_SPARC64
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259 | 5578ceab | blueswir1 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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260 | 5578ceab | blueswir1 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
261 | 5578ceab | blueswir1 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
262 | 5578ceab | blueswir1 | CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) |
263 | 5578ceab | blueswir1 | #else
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264 | 5578ceab | blueswir1 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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265 | 5578ceab | blueswir1 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
266 | 5578ceab | blueswir1 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
267 | 5578ceab | blueswir1 | CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ |
268 | 5578ceab | blueswir1 | CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) |
269 | 5578ceab | blueswir1 | enum {
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270 | 5578ceab | blueswir1 | mmu_us_12, // Ultrasparc < III (64 entry TLB)
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271 | 5578ceab | blueswir1 | mmu_us_3, // Ultrasparc III (512 entry TLB)
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272 | 5578ceab | blueswir1 | mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
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273 | 5578ceab | blueswir1 | mmu_sun4v, // T1, T2
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274 | 5578ceab | blueswir1 | }; |
275 | 5578ceab | blueswir1 | #endif
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276 | 5578ceab | blueswir1 | |
277 | f707726e | Igor Kovalenko | #define TTE_VALID_BIT (1ULL << 63) |
278 | f707726e | Igor Kovalenko | #define TTE_USED_BIT (1ULL << 41) |
279 | f707726e | Igor Kovalenko | #define TTE_LOCKED_BIT (1ULL << 6) |
280 | 2a90358f | Blue Swirl | #define TTE_GLOBAL_BIT (1ULL << 0) |
281 | f707726e | Igor Kovalenko | |
282 | f707726e | Igor Kovalenko | #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
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283 | f707726e | Igor Kovalenko | #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
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284 | f707726e | Igor Kovalenko | #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
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285 | 2a90358f | Blue Swirl | #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
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286 | f707726e | Igor Kovalenko | |
287 | f707726e | Igor Kovalenko | #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
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288 | f707726e | Igor Kovalenko | #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
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289 | f707726e | Igor Kovalenko | |
290 | 6e8e7d4c | Igor Kovalenko | typedef struct SparcTLBEntry { |
291 | 6e8e7d4c | Igor Kovalenko | uint64_t tag; |
292 | 6e8e7d4c | Igor Kovalenko | uint64_t tte; |
293 | 6e8e7d4c | Igor Kovalenko | } SparcTLBEntry; |
294 | 6e8e7d4c | Igor Kovalenko | |
295 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
296 | af7bf89b | bellard | target_ulong gregs[8]; /* general registers */ |
297 | af7bf89b | bellard | target_ulong *regwptr; /* pointer to current register window */
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298 | af7bf89b | bellard | target_ulong pc; /* program counter */
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299 | af7bf89b | bellard | target_ulong npc; /* next program counter */
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300 | af7bf89b | bellard | target_ulong y; /* multiply/divide register */
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301 | dc99a3f2 | blueswir1 | |
302 | dc99a3f2 | blueswir1 | /* emulator internal flags handling */
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303 | d9bdab86 | blueswir1 | target_ulong cc_src, cc_src2; |
304 | dc99a3f2 | blueswir1 | target_ulong cc_dst; |
305 | 8393617c | Blue Swirl | uint32_t cc_op; |
306 | dc99a3f2 | blueswir1 | |
307 | 7c60cc4b | bellard | target_ulong t0, t1; /* temporaries live across basic blocks */
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308 | 7c60cc4b | bellard | target_ulong cond; /* conditional branch result (XXX: save it in a
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309 | 7c60cc4b | bellard | temporary register when possible) */
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310 | 7c60cc4b | bellard | |
311 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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312 | 3475187d | bellard | target_ulong fsr; /* FPU state register */
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313 | 7c60cc4b | bellard | float32 fpr[TARGET_FPREGS]; /* floating point registers */
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314 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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315 | cf495bcf | bellard | from PSR) */
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316 | 5210977a | Igor Kovalenko | #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
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317 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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318 | 5210977a | Igor Kovalenko | #endif
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319 | 3475187d | bellard | target_ulong tbr; /* trap base register */
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320 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
321 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
322 | 5210977a | Igor Kovalenko | #if !defined(TARGET_SPARC64)
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323 | e8af50a3 | bellard | int psret; /* enable traps */ |
324 | 5210977a | Igor Kovalenko | #endif
|
325 | 327ac2e7 | blueswir1 | uint32_t psrpil; /* interrupt blocking level */
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326 | 327ac2e7 | blueswir1 | uint32_t pil_in; /* incoming interrupt level bitmap */
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327 | e80cfcfc | bellard | int psref; /* enable fpu */ |
328 | 62724a37 | blueswir1 | target_ulong version; |
329 | cf495bcf | bellard | int interrupt_index;
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330 | 1a14026e | blueswir1 | uint32_t nwindows; |
331 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
|
332 | 1a14026e | blueswir1 | target_ulong regbase[MAX_NWINDOWS * 16 + 8]; |
333 | d720b93d | bellard | |
334 | a316d335 | bellard | CPU_COMMON |
335 | a316d335 | bellard | |
336 | e8af50a3 | bellard | /* MMU regs */
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337 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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338 | 3475187d | bellard | uint64_t lsu; |
339 | 3475187d | bellard | #define DMMU_E 0x8 |
340 | 3475187d | bellard | #define IMMU_E 0x4 |
341 | 6e8e7d4c | Igor Kovalenko | //typedef struct SparcMMU
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342 | 6e8e7d4c | Igor Kovalenko | union {
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343 | 6e8e7d4c | Igor Kovalenko | uint64_t immuregs[16];
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344 | 6e8e7d4c | Igor Kovalenko | struct {
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345 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb_tag_target; |
346 | 6e8e7d4c | Igor Kovalenko | uint64_t unused_mmu_primary_context; // use DMMU
|
347 | 6e8e7d4c | Igor Kovalenko | uint64_t unused_mmu_secondary_context; // use DMMU
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348 | 6e8e7d4c | Igor Kovalenko | uint64_t sfsr; |
349 | 6e8e7d4c | Igor Kovalenko | uint64_t sfar; |
350 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb; |
351 | 6e8e7d4c | Igor Kovalenko | uint64_t tag_access; |
352 | 6e8e7d4c | Igor Kovalenko | } immu; |
353 | 6e8e7d4c | Igor Kovalenko | }; |
354 | 6e8e7d4c | Igor Kovalenko | union {
|
355 | 6e8e7d4c | Igor Kovalenko | uint64_t dmmuregs[16];
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356 | 6e8e7d4c | Igor Kovalenko | struct {
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357 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb_tag_target; |
358 | 6e8e7d4c | Igor Kovalenko | uint64_t mmu_primary_context; |
359 | 6e8e7d4c | Igor Kovalenko | uint64_t mmu_secondary_context; |
360 | 6e8e7d4c | Igor Kovalenko | uint64_t sfsr; |
361 | 6e8e7d4c | Igor Kovalenko | uint64_t sfar; |
362 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb; |
363 | 6e8e7d4c | Igor Kovalenko | uint64_t tag_access; |
364 | 6e8e7d4c | Igor Kovalenko | } dmmu; |
365 | 6e8e7d4c | Igor Kovalenko | }; |
366 | 6e8e7d4c | Igor Kovalenko | SparcTLBEntry itlb[64];
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367 | 6e8e7d4c | Igor Kovalenko | SparcTLBEntry dtlb[64];
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368 | fb79ceb9 | blueswir1 | uint32_t mmu_version; |
369 | 3475187d | bellard | #else
|
370 | 3dd9a152 | blueswir1 | uint32_t mmuregs[32];
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371 | 952a328f | blueswir1 | uint64_t mxccdata[4];
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372 | 952a328f | blueswir1 | uint64_t mxccregs[8];
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373 | 4017190e | blueswir1 | uint64_t mmubpregs[4];
|
374 | 3ebf5aaf | blueswir1 | uint64_t prom_addr; |
375 | 3475187d | bellard | #endif
|
376 | e8af50a3 | bellard | /* temporary float registers */
|
377 | 65ce8c2f | bellard | float64 dt0, dt1; |
378 | 1f587329 | blueswir1 | float128 qt0, qt1; |
379 | 7a0e1f41 | bellard | float_status fp_status; |
380 | af7bf89b | bellard | #if defined(TARGET_SPARC64)
|
381 | c19148bd | blueswir1 | #define MAXTL_MAX 8 |
382 | c19148bd | blueswir1 | #define MAXTL_MASK (MAXTL_MAX - 1) |
383 | c19148bd | blueswir1 | trap_state ts[MAXTL_MAX]; |
384 | 0f8a249a | blueswir1 | uint32_t xcc; /* Extended integer condition codes */
|
385 | 3475187d | bellard | uint32_t asi; |
386 | 3475187d | bellard | uint32_t pstate; |
387 | 3475187d | bellard | uint32_t tl; |
388 | c19148bd | blueswir1 | uint32_t maxtl; |
389 | 3475187d | bellard | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
390 | 83469015 | bellard | uint64_t agregs[8]; /* alternate general registers */ |
391 | 83469015 | bellard | uint64_t bgregs[8]; /* backup for normal global registers */ |
392 | 83469015 | bellard | uint64_t igregs[8]; /* interrupt general registers */ |
393 | 83469015 | bellard | uint64_t mgregs[8]; /* mmu general registers */ |
394 | 3475187d | bellard | uint64_t fprs; |
395 | 83469015 | bellard | uint64_t tick_cmpr, stick_cmpr; |
396 | 20c9f095 | blueswir1 | void *tick, *stick;
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397 | 709f2c1b | Igor V. Kovalenko | #define TICK_NPT_MASK 0x8000000000000000ULL |
398 | 709f2c1b | Igor V. Kovalenko | #define TICK_INT_DIS 0x8000000000000000ULL |
399 | 725cb90b | bellard | uint64_t gsr; |
400 | e9ebed4d | blueswir1 | uint32_t gl; // UA2005
|
401 | e9ebed4d | blueswir1 | /* UA 2005 hyperprivileged registers */
|
402 | c19148bd | blueswir1 | uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
403 | 20c9f095 | blueswir1 | void *hstick; // UA 2005 |
404 | 9d926598 | blueswir1 | uint32_t softint; |
405 | 8fa211e8 | blueswir1 | #define SOFTINT_TIMER 1 |
406 | 8fa211e8 | blueswir1 | #define SOFTINT_STIMER (1 << 16) |
407 | 709f2c1b | Igor V. Kovalenko | #define SOFTINT_INTRMASK (0xFFFE) |
408 | 709f2c1b | Igor V. Kovalenko | #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
|
409 | 3475187d | bellard | #endif
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410 | 5578ceab | blueswir1 | sparc_def_t *def; |
411 | 7a3f1944 | bellard | } CPUSPARCState; |
412 | 64a88d5d | blueswir1 | |
413 | 91736d37 | blueswir1 | /* helper.c */
|
414 | aaed909a | bellard | CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
415 | 91736d37 | blueswir1 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
416 | 62724a37 | blueswir1 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, |
417 | 62724a37 | blueswir1 | ...)); |
418 | 48585ec5 | blueswir1 | void cpu_lock(void); |
419 | 48585ec5 | blueswir1 | void cpu_unlock(void); |
420 | 48585ec5 | blueswir1 | int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, |
421 | 48585ec5 | blueswir1 | int mmu_idx, int is_softmmu); |
422 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
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423 | 48585ec5 | blueswir1 | target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
|
424 | 48585ec5 | blueswir1 | void dump_mmu(CPUSPARCState *env);
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425 | 91736d37 | blueswir1 | |
426 | 91736d37 | blueswir1 | /* translate.c */
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427 | 91736d37 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env);
|
428 | 91736d37 | blueswir1 | |
429 | 91736d37 | blueswir1 | /* cpu-exec.c */
|
430 | 91736d37 | blueswir1 | int cpu_sparc_exec(CPUSPARCState *s);
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431 | 7a3f1944 | bellard | |
432 | 5210977a | Igor Kovalenko | #if !defined (TARGET_SPARC64)
|
433 | 62724a37 | blueswir1 | #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
|
434 | 0f8a249a | blueswir1 | (env->psref? PSR_EF : 0) | \
|
435 | 0f8a249a | blueswir1 | (env->psrpil << 8) | \
|
436 | 0f8a249a | blueswir1 | (env->psrs? PSR_S : 0) | \
|
437 | 0f8a249a | blueswir1 | (env->psrps? PSR_PS : 0) | \
|
438 | 0f8a249a | blueswir1 | (env->psret? PSR_ET : 0) | env->cwp)
|
439 | 5210977a | Igor Kovalenko | #else
|
440 | 5210977a | Igor Kovalenko | #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
|
441 | 5210977a | Igor Kovalenko | (env->psref? PSR_EF : 0) | \
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442 | 5210977a | Igor Kovalenko | (env->psrpil << 8) | \
|
443 | 5210977a | Igor Kovalenko | (env->psrs? PSR_S : 0) | \
|
444 | 5210977a | Igor Kovalenko | (env->psrps? PSR_PS : 0) | \
|
445 | 5210977a | Igor Kovalenko | env->cwp) |
446 | 5210977a | Igor Kovalenko | #endif
|
447 | b4ff5987 | bellard | |
448 | b4ff5987 | bellard | #ifndef NO_CPU_IO_DEFS
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449 | 4c6aa085 | Blue Swirl | |
450 | 4c6aa085 | Blue Swirl | static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) |
451 | 4c6aa085 | Blue Swirl | { |
452 | 4c6aa085 | Blue Swirl | if (unlikely(cwp >= env1->nwindows))
|
453 | 4c6aa085 | Blue Swirl | cwp -= env1->nwindows; |
454 | 4c6aa085 | Blue Swirl | return cwp;
|
455 | 4c6aa085 | Blue Swirl | } |
456 | 4c6aa085 | Blue Swirl | |
457 | 4c6aa085 | Blue Swirl | static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) |
458 | 4c6aa085 | Blue Swirl | { |
459 | 4c6aa085 | Blue Swirl | if (unlikely(cwp < 0)) |
460 | 4c6aa085 | Blue Swirl | cwp += env1->nwindows; |
461 | 4c6aa085 | Blue Swirl | return cwp;
|
462 | 4c6aa085 | Blue Swirl | } |
463 | 4c6aa085 | Blue Swirl | #endif
|
464 | 4c6aa085 | Blue Swirl | |
465 | 91736d37 | blueswir1 | static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
466 | 91736d37 | blueswir1 | { |
467 | 91736d37 | blueswir1 | dst[0] = src[0]; |
468 | 91736d37 | blueswir1 | dst[1] = src[1]; |
469 | 91736d37 | blueswir1 | dst[2] = src[2]; |
470 | 91736d37 | blueswir1 | dst[3] = src[3]; |
471 | 91736d37 | blueswir1 | dst[4] = src[4]; |
472 | 91736d37 | blueswir1 | dst[5] = src[5]; |
473 | 91736d37 | blueswir1 | dst[6] = src[6]; |
474 | 91736d37 | blueswir1 | dst[7] = src[7]; |
475 | 91736d37 | blueswir1 | } |
476 | 91736d37 | blueswir1 | |
477 | 91736d37 | blueswir1 | static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp) |
478 | 91736d37 | blueswir1 | { |
479 | 91736d37 | blueswir1 | /* put the modified wrap registers at their proper location */
|
480 | 91736d37 | blueswir1 | if (env1->cwp == env1->nwindows - 1) |
481 | 91736d37 | blueswir1 | memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
|
482 | 91736d37 | blueswir1 | env1->cwp = new_cwp; |
483 | 91736d37 | blueswir1 | /* put the wrap registers at their temporary location */
|
484 | 91736d37 | blueswir1 | if (new_cwp == env1->nwindows - 1) |
485 | 91736d37 | blueswir1 | memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
|
486 | 91736d37 | blueswir1 | env1->regwptr = env1->regbase + (new_cwp * 16);
|
487 | 91736d37 | blueswir1 | } |
488 | 1a14026e | blueswir1 | |
489 | 4c6aa085 | Blue Swirl | /* sun4m.c, sun4u.c */
|
490 | 4c6aa085 | Blue Swirl | void cpu_check_irqs(CPUSPARCState *env);
|
491 | 1a14026e | blueswir1 | |
492 | 4c6aa085 | Blue Swirl | static inline void PUT_PSR(CPUSPARCState *env1, target_ulong val) |
493 | 1a14026e | blueswir1 | { |
494 | 4c6aa085 | Blue Swirl | env1->psr = val & PSR_ICC; |
495 | 4c6aa085 | Blue Swirl | env1->psref = (val & PSR_EF)? 1 : 0; |
496 | 4c6aa085 | Blue Swirl | env1->psrpil = (val & PSR_PIL) >> 8;
|
497 | 4c6aa085 | Blue Swirl | #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
|
498 | 4c6aa085 | Blue Swirl | cpu_check_irqs(env1); |
499 | b4ff5987 | bellard | #endif
|
500 | 4c6aa085 | Blue Swirl | env1->psrs = (val & PSR_S)? 1 : 0; |
501 | 4c6aa085 | Blue Swirl | env1->psrps = (val & PSR_PS)? 1 : 0; |
502 | 5210977a | Igor Kovalenko | #if !defined (TARGET_SPARC64)
|
503 | 4c6aa085 | Blue Swirl | env1->psret = (val & PSR_ET)? 1 : 0; |
504 | 5210977a | Igor Kovalenko | #endif
|
505 | 4c6aa085 | Blue Swirl | cpu_set_cwp(env1, val & PSR_CWP); |
506 | 4c6aa085 | Blue Swirl | env1->cc_op = CC_OP_FLAGS; |
507 | 4c6aa085 | Blue Swirl | } |
508 | b4ff5987 | bellard | |
509 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
510 | 17d996e1 | blueswir1 | #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) |
511 | 0f8a249a | blueswir1 | #define PUT_CCR(env, val) do { int _tmp = val; \ |
512 | 77f193da | blueswir1 | env->xcc = (_tmp >> 4) << 20; \ |
513 | 0f8a249a | blueswir1 | env->psr = (_tmp & 0xf) << 20; \ |
514 | 8393617c | Blue Swirl | CC_OP = CC_OP_FLAGS; \ |
515 | 3475187d | bellard | } while (0) |
516 | 1a14026e | blueswir1 | #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp) |
517 | 1a14026e | blueswir1 | |
518 | 0bbd4a0d | blueswir1 | #ifndef NO_CPU_IO_DEFS
|
519 | 1a14026e | blueswir1 | static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) |
520 | 1a14026e | blueswir1 | { |
521 | 1a14026e | blueswir1 | if (unlikely(cwp >= env1->nwindows || cwp < 0)) |
522 | 4f690853 | Igor V. Kovalenko | cwp %= env1->nwindows; |
523 | 1a14026e | blueswir1 | cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
|
524 | 1a14026e | blueswir1 | } |
525 | 0bbd4a0d | blueswir1 | #endif
|
526 | 3475187d | bellard | #endif
|
527 | 3475187d | bellard | |
528 | 91736d37 | blueswir1 | /* cpu-exec.c */
|
529 | c227f099 | Anthony Liguori | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
530 | e18231a3 | blueswir1 | int is_asi, int size); |
531 | f0d5e471 | blueswir1 | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
532 | 7a3f1944 | bellard | |
533 | 9467d44c | ths | #define cpu_init cpu_sparc_init
|
534 | 9467d44c | ths | #define cpu_exec cpu_sparc_exec
|
535 | 9467d44c | ths | #define cpu_gen_code cpu_sparc_gen_code
|
536 | 9467d44c | ths | #define cpu_signal_handler cpu_sparc_signal_handler
|
537 | c732abe2 | j_mayer | #define cpu_list sparc_cpu_list
|
538 | 9467d44c | ths | |
539 | 0b8f1b10 | blueswir1 | #define CPU_SAVE_VERSION 5 |
540 | b3c7724c | pbrook | |
541 | 6ebbf390 | j_mayer | /* MMU modes definitions */
|
542 | 6f27aba6 | blueswir1 | #define MMU_MODE0_SUFFIX _user
|
543 | 6f27aba6 | blueswir1 | #define MMU_MODE1_SUFFIX _kernel
|
544 | 6f27aba6 | blueswir1 | #ifdef TARGET_SPARC64
|
545 | 6f27aba6 | blueswir1 | #define MMU_MODE2_SUFFIX _hypv
|
546 | 6f27aba6 | blueswir1 | #endif
|
547 | 9e31b9e2 | blueswir1 | #define MMU_USER_IDX 0 |
548 | 9e31b9e2 | blueswir1 | #define MMU_KERNEL_IDX 1 |
549 | 9e31b9e2 | blueswir1 | #define MMU_HYPV_IDX 2 |
550 | 9e31b9e2 | blueswir1 | |
551 | 22548760 | blueswir1 | static inline int cpu_mmu_index(CPUState *env1) |
552 | 6ebbf390 | j_mayer | { |
553 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
554 | 9e31b9e2 | blueswir1 | return MMU_USER_IDX;
|
555 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
|
556 | 22548760 | blueswir1 | return env1->psrs;
|
557 | 6f27aba6 | blueswir1 | #else
|
558 | 22548760 | blueswir1 | if (!env1->psrs)
|
559 | 9e31b9e2 | blueswir1 | return MMU_USER_IDX;
|
560 | 22548760 | blueswir1 | else if ((env1->hpstate & HS_PRIV) == 0) |
561 | 9e31b9e2 | blueswir1 | return MMU_KERNEL_IDX;
|
562 | 6f27aba6 | blueswir1 | else
|
563 | 9e31b9e2 | blueswir1 | return MMU_HYPV_IDX;
|
564 | 6f27aba6 | blueswir1 | #endif
|
565 | 6f27aba6 | blueswir1 | } |
566 | 6f27aba6 | blueswir1 | |
567 | 2df6c2d0 | Igor V. Kovalenko | static inline int cpu_interrupts_enabled(CPUState *env1) |
568 | 2df6c2d0 | Igor V. Kovalenko | { |
569 | 2df6c2d0 | Igor V. Kovalenko | #if !defined (TARGET_SPARC64)
|
570 | 2df6c2d0 | Igor V. Kovalenko | if (env1->psret != 0) |
571 | 2df6c2d0 | Igor V. Kovalenko | return 1; |
572 | 2df6c2d0 | Igor V. Kovalenko | #else
|
573 | 2df6c2d0 | Igor V. Kovalenko | if (env1->pstate & PS_IE)
|
574 | 2df6c2d0 | Igor V. Kovalenko | return 1; |
575 | 2df6c2d0 | Igor V. Kovalenko | #endif
|
576 | 2df6c2d0 | Igor V. Kovalenko | |
577 | 2df6c2d0 | Igor V. Kovalenko | return 0; |
578 | 2df6c2d0 | Igor V. Kovalenko | } |
579 | 2df6c2d0 | Igor V. Kovalenko | |
580 | d532b26c | Igor V. Kovalenko | static inline int cpu_pil_allowed(CPUState *env1, int pil) |
581 | d532b26c | Igor V. Kovalenko | { |
582 | d532b26c | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
|
583 | d532b26c | Igor V. Kovalenko | /* level 15 is non-maskable on sparc v8 */
|
584 | d532b26c | Igor V. Kovalenko | return pil == 15 || pil > env1->psrpil; |
585 | d532b26c | Igor V. Kovalenko | #else
|
586 | d532b26c | Igor V. Kovalenko | return pil > env1->psrpil;
|
587 | d532b26c | Igor V. Kovalenko | #endif
|
588 | d532b26c | Igor V. Kovalenko | } |
589 | d532b26c | Igor V. Kovalenko | |
590 | 22548760 | blueswir1 | static inline int cpu_fpu_enabled(CPUState *env1) |
591 | 6f27aba6 | blueswir1 | { |
592 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
593 | 6f27aba6 | blueswir1 | return 1; |
594 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
|
595 | 22548760 | blueswir1 | return env1->psref;
|
596 | 6f27aba6 | blueswir1 | #else
|
597 | 22548760 | blueswir1 | return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0); |
598 | 6f27aba6 | blueswir1 | #endif
|
599 | 6ebbf390 | j_mayer | } |
600 | 6ebbf390 | j_mayer | |
601 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
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602 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
603 | 6e68e076 | pbrook | { |
604 | f8ed7070 | pbrook | if (newsp)
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605 | 6e68e076 | pbrook | env->regwptr[22] = newsp;
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606 | 6e68e076 | pbrook | env->regwptr[0] = 0; |
607 | 6e68e076 | pbrook | /* FIXME: Do we also need to clear CF? */
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608 | 6e68e076 | pbrook | /* XXXXX */
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609 | 6e68e076 | pbrook | printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
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610 | 6e68e076 | pbrook | } |
611 | 6e68e076 | pbrook | #endif
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612 | 6e68e076 | pbrook | |
613 | 7a3f1944 | bellard | #include "cpu-all.h" |
614 | 622ed360 | aliguori | #include "exec-all.h" |
615 | 7a3f1944 | bellard | |
616 | f4b1a842 | blueswir1 | #ifdef TARGET_SPARC64
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617 | f4b1a842 | blueswir1 | /* sun4u.c */
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618 | f4b1a842 | blueswir1 | void cpu_tick_set_count(void *opaque, uint64_t count); |
619 | f4b1a842 | blueswir1 | uint64_t cpu_tick_get_count(void *opaque);
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620 | f4b1a842 | blueswir1 | void cpu_tick_set_limit(void *opaque, uint64_t limit); |
621 | 8194f35a | Igor Kovalenko | trap_state* cpu_tsptr(CPUState* env); |
622 | f4b1a842 | blueswir1 | #endif
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623 | f4b1a842 | blueswir1 | |
624 | 622ed360 | aliguori | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
625 | 622ed360 | aliguori | { |
626 | 622ed360 | aliguori | env->pc = tb->pc; |
627 | 622ed360 | aliguori | env->npc = tb->cs_base; |
628 | 622ed360 | aliguori | } |
629 | 622ed360 | aliguori | |
630 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
631 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
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632 | 6b917547 | aliguori | { |
633 | 6b917547 | aliguori | *pc = env->pc; |
634 | 6b917547 | aliguori | *cs_base = env->npc; |
635 | 6b917547 | aliguori | #ifdef TARGET_SPARC64
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636 | 6b917547 | aliguori | // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
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637 | 6b917547 | aliguori | *flags = ((env->pstate & PS_AM) << 2)
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638 | 6b917547 | aliguori | | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) |
639 | 6b917547 | aliguori | | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
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640 | 6b917547 | aliguori | #else
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641 | 6b917547 | aliguori | // FPU enable . Supervisor
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642 | 6b917547 | aliguori | *flags = (env->psref << 4) | env->psrs;
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643 | 6b917547 | aliguori | #endif
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644 | 6b917547 | aliguori | } |
645 | 6b917547 | aliguori | |
646 | 7a3f1944 | bellard | #endif |