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1
/*
2
 *  PowerPC emulation helpers for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include "exec.h"
21

    
22
#include "helper_regs.h"
23
#include "op_helper.h"
24

    
25
#define MEMSUFFIX _raw
26
#include "op_helper.h"
27
#include "op_helper_mem.h"
28
#if !defined(CONFIG_USER_ONLY)
29
#define MEMSUFFIX _user
30
#include "op_helper.h"
31
#include "op_helper_mem.h"
32
#define MEMSUFFIX _kernel
33
#include "op_helper.h"
34
#include "op_helper_mem.h"
35
#if defined(TARGET_PPC64H)
36
#define MEMSUFFIX _hypv
37
#include "op_helper.h"
38
#include "op_helper_mem.h"
39
#endif
40
#endif
41

    
42
//#define DEBUG_OP
43
//#define DEBUG_EXCEPTIONS
44
//#define DEBUG_SOFTWARE_TLB
45

    
46
/*****************************************************************************/
47
/* Exceptions processing helpers */
48

    
49
void do_raise_exception_err (uint32_t exception, int error_code)
50
{
51
#if 0
52
    printf("Raise exception %3x code : %d\n", exception, error_code);
53
#endif
54
    env->exception_index = exception;
55
    env->error_code = error_code;
56
    cpu_loop_exit();
57
}
58

    
59
void do_raise_exception (uint32_t exception)
60
{
61
    do_raise_exception_err(exception, 0);
62
}
63

    
64
void cpu_dump_EA (target_ulong EA);
65
void do_print_mem_EA (target_ulong EA)
66
{
67
    cpu_dump_EA(EA);
68
}
69

    
70
/*****************************************************************************/
71
/* Registers load and stores */
72
void do_load_cr (void)
73
{
74
    T0 = (env->crf[0] << 28) |
75
        (env->crf[1] << 24) |
76
        (env->crf[2] << 20) |
77
        (env->crf[3] << 16) |
78
        (env->crf[4] << 12) |
79
        (env->crf[5] << 8) |
80
        (env->crf[6] << 4) |
81
        (env->crf[7] << 0);
82
}
83

    
84
void do_store_cr (uint32_t mask)
85
{
86
    int i, sh;
87

    
88
    for (i = 0, sh = 7; i < 8; i++, sh--) {
89
        if (mask & (1 << sh))
90
            env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
91
    }
92
}
93

    
94
#if defined(TARGET_PPC64)
95
void do_store_pri (int prio)
96
{
97
    env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
98
    env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
99
}
100
#endif
101

    
102
target_ulong ppc_load_dump_spr (int sprn)
103
{
104
    if (loglevel != 0) {
105
        fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
106
                sprn, sprn, env->spr[sprn]);
107
    }
108

    
109
    return env->spr[sprn];
110
}
111

    
112
void ppc_store_dump_spr (int sprn, target_ulong val)
113
{
114
    if (loglevel != 0) {
115
        fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
116
                sprn, sprn, env->spr[sprn], val);
117
    }
118
    env->spr[sprn] = val;
119
}
120

    
121
/*****************************************************************************/
122
/* Fixed point operations helpers */
123
void do_adde (void)
124
{
125
    T2 = T0;
126
    T0 += T1 + xer_ca;
127
    if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
128
                 (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
129
        xer_ca = 0;
130
    } else {
131
        xer_ca = 1;
132
    }
133
}
134

    
135
#if defined(TARGET_PPC64)
136
void do_adde_64 (void)
137
{
138
    T2 = T0;
139
    T0 += T1 + xer_ca;
140
    if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
141
                 (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
142
        xer_ca = 0;
143
    } else {
144
        xer_ca = 1;
145
    }
146
}
147
#endif
148

    
149
void do_addmeo (void)
150
{
151
    T1 = T0;
152
    T0 += xer_ca + (-1);
153
    if (likely(!((uint32_t)T1 &
154
                 ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
155
        xer_ov = 0;
156
    } else {
157
        xer_ov = 1;
158
        xer_so = 1;
159
    }
160
    if (likely(T1 != 0))
161
        xer_ca = 1;
162
}
163

    
164
#if defined(TARGET_PPC64)
165
void do_addmeo_64 (void)
166
{
167
    T1 = T0;
168
    T0 += xer_ca + (-1);
169
    if (likely(!((uint64_t)T1 &
170
                 ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
171
        xer_ov = 0;
172
    } else {
173
        xer_ov = 1;
174
        xer_so = 1;
175
    }
176
    if (likely(T1 != 0))
177
        xer_ca = 1;
178
}
179
#endif
180

    
181
void do_divwo (void)
182
{
183
    if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
184
                 (int32_t)T1 == 0))) {
185
        xer_ov = 0;
186
        T0 = (int32_t)T0 / (int32_t)T1;
187
    } else {
188
        xer_ov = 1;
189
        xer_so = 1;
190
        T0 = (-1) * ((uint32_t)T0 >> 31);
191
    }
192
}
193

    
194
#if defined(TARGET_PPC64)
195
void do_divdo (void)
196
{
197
    if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
198
                 (int64_t)T1 == 0))) {
199
        xer_ov = 0;
200
        T0 = (int64_t)T0 / (int64_t)T1;
201
    } else {
202
        xer_ov = 1;
203
        xer_so = 1;
204
        T0 = (-1ULL) * ((uint64_t)T0 >> 63);
205
    }
206
}
207
#endif
208

    
209
void do_divwuo (void)
210
{
211
    if (likely((uint32_t)T1 != 0)) {
212
        xer_ov = 0;
213
        T0 = (uint32_t)T0 / (uint32_t)T1;
214
    } else {
215
        xer_ov = 1;
216
        xer_so = 1;
217
        T0 = 0;
218
    }
219
}
220

    
221
#if defined(TARGET_PPC64)
222
void do_divduo (void)
223
{
224
    if (likely((uint64_t)T1 != 0)) {
225
        xer_ov = 0;
226
        T0 = (uint64_t)T0 / (uint64_t)T1;
227
    } else {
228
        xer_ov = 1;
229
        xer_so = 1;
230
        T0 = 0;
231
    }
232
}
233
#endif
234

    
235
void do_mullwo (void)
236
{
237
    int64_t res = (int64_t)T0 * (int64_t)T1;
238

    
239
    if (likely((int32_t)res == res)) {
240
        xer_ov = 0;
241
    } else {
242
        xer_ov = 1;
243
        xer_so = 1;
244
    }
245
    T0 = (int32_t)res;
246
}
247

    
248
#if defined(TARGET_PPC64)
249
void do_mulldo (void)
250
{
251
    int64_t th;
252
    uint64_t tl;
253

    
254
    muls64(&tl, &th, T0, T1);
255
    /* If th != 0 && th != -1, then we had an overflow */
256
    if (likely((th + 1) <= 1)) {
257
        xer_ov = 0;
258
    } else {
259
        xer_ov = 1;
260
        xer_so = 1;
261
    }
262
    T0 = (int64_t)tl;
263
}
264
#endif
265

    
266
void do_nego (void)
267
{
268
    if (likely((int32_t)T0 != INT32_MIN)) {
269
        xer_ov = 0;
270
        T0 = -(int32_t)T0;
271
    } else {
272
        xer_ov = 1;
273
        xer_so = 1;
274
    }
275
}
276

    
277
#if defined(TARGET_PPC64)
278
void do_nego_64 (void)
279
{
280
    if (likely((int64_t)T0 != INT64_MIN)) {
281
        xer_ov = 0;
282
        T0 = -(int64_t)T0;
283
    } else {
284
        xer_ov = 1;
285
        xer_so = 1;
286
    }
287
}
288
#endif
289

    
290
void do_subfe (void)
291
{
292
    T0 = T1 + ~T0 + xer_ca;
293
    if (likely((uint32_t)T0 >= (uint32_t)T1 &&
294
               (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
295
        xer_ca = 0;
296
    } else {
297
        xer_ca = 1;
298
    }
299
}
300

    
301
#if defined(TARGET_PPC64)
302
void do_subfe_64 (void)
303
{
304
    T0 = T1 + ~T0 + xer_ca;
305
    if (likely((uint64_t)T0 >= (uint64_t)T1 &&
306
               (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
307
        xer_ca = 0;
308
    } else {
309
        xer_ca = 1;
310
    }
311
}
312
#endif
313

    
314
void do_subfmeo (void)
315
{
316
    T1 = T0;
317
    T0 = ~T0 + xer_ca - 1;
318
    if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
319
                 (1UL << 31)))) {
320
        xer_ov = 0;
321
    } else {
322
        xer_ov = 1;
323
        xer_so = 1;
324
    }
325
    if (likely((uint32_t)T1 != UINT32_MAX))
326
        xer_ca = 1;
327
}
328

    
329
#if defined(TARGET_PPC64)
330
void do_subfmeo_64 (void)
331
{
332
    T1 = T0;
333
    T0 = ~T0 + xer_ca - 1;
334
    if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
335
                 (1ULL << 63)))) {
336
        xer_ov = 0;
337
    } else {
338
        xer_ov = 1;
339
        xer_so = 1;
340
    }
341
    if (likely((uint64_t)T1 != UINT64_MAX))
342
        xer_ca = 1;
343
}
344
#endif
345

    
346
void do_subfzeo (void)
347
{
348
    T1 = T0;
349
    T0 = ~T0 + xer_ca;
350
    if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
351
                 ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
352
        xer_ov = 0;
353
    } else {
354
        xer_ov = 1;
355
        xer_so = 1;
356
    }
357
    if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
358
        xer_ca = 0;
359
    } else {
360
        xer_ca = 1;
361
    }
362
}
363

    
364
#if defined(TARGET_PPC64)
365
void do_subfzeo_64 (void)
366
{
367
    T1 = T0;
368
    T0 = ~T0 + xer_ca;
369
    if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
370
                 ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
371
        xer_ov = 0;
372
    } else {
373
        xer_ov = 1;
374
        xer_so = 1;
375
    }
376
    if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
377
        xer_ca = 0;
378
    } else {
379
        xer_ca = 1;
380
    }
381
}
382
#endif
383

    
384
/* shift right arithmetic helper */
385
void do_sraw (void)
386
{
387
    int32_t ret;
388

    
389
    if (likely(!(T1 & 0x20UL))) {
390
        if (likely((uint32_t)T1 != 0)) {
391
            ret = (int32_t)T0 >> (T1 & 0x1fUL);
392
            if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
393
                xer_ca = 0;
394
            } else {
395
                xer_ca = 1;
396
            }
397
        } else {
398
            ret = T0;
399
            xer_ca = 0;
400
        }
401
    } else {
402
        ret = (-1) * ((uint32_t)T0 >> 31);
403
        if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
404
            xer_ca = 0;
405
        } else {
406
            xer_ca = 1;
407
        }
408
    }
409
    T0 = ret;
410
}
411

    
412
#if defined(TARGET_PPC64)
413
void do_srad (void)
414
{
415
    int64_t ret;
416

    
417
    if (likely(!(T1 & 0x40UL))) {
418
        if (likely((uint64_t)T1 != 0)) {
419
            ret = (int64_t)T0 >> (T1 & 0x3FUL);
420
            if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
421
                xer_ca = 0;
422
            } else {
423
                xer_ca = 1;
424
            }
425
        } else {
426
            ret = T0;
427
            xer_ca = 0;
428
        }
429
    } else {
430
        ret = (-1) * ((uint64_t)T0 >> 63);
431
        if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
432
            xer_ca = 0;
433
        } else {
434
            xer_ca = 1;
435
        }
436
    }
437
    T0 = ret;
438
}
439
#endif
440

    
441
static always_inline int popcnt (uint32_t val)
442
{
443
    int i;
444

    
445
    for (i = 0; val != 0;)
446
        val = val ^ (val - 1);
447

    
448
    return i;
449
}
450

    
451
void do_popcntb (void)
452
{
453
    uint32_t ret;
454
    int i;
455

    
456
    ret = 0;
457
    for (i = 0; i < 32; i += 8)
458
        ret |= popcnt((T0 >> i) & 0xFF) << i;
459
    T0 = ret;
460
}
461

    
462
#if defined(TARGET_PPC64)
463
void do_popcntb_64 (void)
464
{
465
    uint64_t ret;
466
    int i;
467

    
468
    ret = 0;
469
    for (i = 0; i < 64; i += 8)
470
        ret |= popcnt((T0 >> i) & 0xFF) << i;
471
    T0 = ret;
472
}
473
#endif
474

    
475
/*****************************************************************************/
476
/* Floating point operations helpers */
477
static inline int fpisneg (float64 f)
478
{
479
    union {
480
        float64 f;
481
        uint64_t u;
482
    } u;
483

    
484
    u.f = f;
485

    
486
    return u.u >> 63 != 0;
487
}
488

    
489
static inline int isden (float f)
490
{
491
    union {
492
        float64 f;
493
        uint64_t u;
494
    } u;
495

    
496
    u.f = f;
497

    
498
    return ((u.u >> 52) & 0x7FF) == 0;
499
}
500

    
501
static inline int iszero (float64 f)
502
{
503
    union {
504
        float64 f;
505
        uint64_t u;
506
    } u;
507

    
508
    u.f = f;
509

    
510
    return (u.u & ~0x8000000000000000ULL) == 0;
511
}
512

    
513
static inline int isinfinity (float64 f)
514
{
515
    union {
516
        float64 f;
517
        uint64_t u;
518
    } u;
519

    
520
    u.f = f;
521

    
522
    return ((u.u >> 52) & 0x3FF) == 0x3FF &&
523
        (u.u & 0x000FFFFFFFFFFFFFULL) == 0;
524
}
525

    
526
void do_compute_fprf (int set_fprf)
527
{
528
    int isneg;
529

    
530
    isneg = fpisneg(FT0);
531
    if (unlikely(float64_is_nan(FT0))) {
532
        if (float64_is_signaling_nan(FT0)) {
533
            /* Signaling NaN: flags are undefined */
534
            T0 = 0x00;
535
        } else {
536
            /* Quiet NaN */
537
            T0 = 0x11;
538
        }
539
    } else if (unlikely(isinfinity(FT0))) {
540
        /* +/- infinity */
541
        if (isneg)
542
            T0 = 0x09;
543
        else
544
            T0 = 0x05;
545
    } else {
546
        if (iszero(FT0)) {
547
            /* +/- zero */
548
            if (isneg)
549
                T0 = 0x12;
550
            else
551
                T0 = 0x02;
552
        } else {
553
            if (isden(FT0)) {
554
                /* Denormalized numbers */
555
                T0 = 0x10;
556
            } else {
557
                /* Normalized numbers */
558
                T0 = 0x00;
559
            }
560
            if (isneg) {
561
                T0 |= 0x08;
562
            } else {
563
                T0 |= 0x04;
564
            }
565
        }
566
    }
567
    if (set_fprf) {
568
        /* We update FPSCR_FPRF */
569
        env->fpscr &= ~(0x1F << FPSCR_FPRF);
570
        env->fpscr |= T0 << FPSCR_FPRF;
571
    }
572
    /* We just need fpcc to update Rc1 */
573
    T0 &= 0xF;
574
}
575

    
576
/* Floating-point invalid operations exception */
577
static always_inline void fload_invalid_op_excp (int op)
578
{
579
    int ve;
580

    
581
    ve = fpscr_ve;
582
    if (op & POWERPC_EXCP_FP_VXSNAN) {
583
        /* Operation on signaling NaN */
584
        env->fpscr |= 1 << FPSCR_VXSNAN;
585
    }
586
    if (op & POWERPC_EXCP_FP_VXSOFT) {
587
        /* Software-defined condition */
588
        env->fpscr |= 1 << FPSCR_VXSOFT;
589
    }
590
    switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
591
    case POWERPC_EXCP_FP_VXISI:
592
        /* Magnitude subtraction of infinities */
593
        env->fpscr |= 1 << FPSCR_VXISI;
594
        goto update_arith;
595
    case POWERPC_EXCP_FP_VXIDI:
596
        /* Division of infinity by infinity */
597
        env->fpscr |= 1 << FPSCR_VXIDI;
598
        goto update_arith;
599
    case POWERPC_EXCP_FP_VXZDZ:
600
        /* Division of zero by zero */
601
        env->fpscr |= 1 << FPSCR_VXZDZ;
602
        goto update_arith;
603
    case POWERPC_EXCP_FP_VXIMZ:
604
        /* Multiplication of zero by infinity */
605
        env->fpscr |= 1 << FPSCR_VXIMZ;
606
        goto update_arith;
607
    case POWERPC_EXCP_FP_VXVC:
608
        /* Ordered comparison of NaN */
609
        env->fpscr |= 1 << FPSCR_VXVC;
610
        env->fpscr &= ~(0xF << FPSCR_FPCC);
611
        env->fpscr |= 0x11 << FPSCR_FPCC;
612
        /* We must update the target FPR before raising the exception */
613
        if (ve != 0) {
614
            env->exception_index = POWERPC_EXCP_PROGRAM;
615
            env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
616
            /* Update the floating-point enabled exception summary */
617
            env->fpscr |= 1 << FPSCR_FEX;
618
            /* Exception is differed */
619
            ve = 0;
620
        }
621
        break;
622
    case POWERPC_EXCP_FP_VXSQRT:
623
        /* Square root of a negative number */
624
        env->fpscr |= 1 << FPSCR_VXSQRT;
625
    update_arith:
626
        env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
627
        if (ve == 0) {
628
            /* Set the result to quiet NaN */
629
            FT0 = (uint64_t)-1;
630
            env->fpscr &= ~(0xF << FPSCR_FPCC);
631
            env->fpscr |= 0x11 << FPSCR_FPCC;
632
        }
633
        break;
634
    case POWERPC_EXCP_FP_VXCVI:
635
        /* Invalid conversion */
636
        env->fpscr |= 1 << FPSCR_VXCVI;
637
        env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
638
        if (ve == 0) {
639
            /* Set the result to quiet NaN */
640
            FT0 = (uint64_t)-1;
641
            env->fpscr &= ~(0xF << FPSCR_FPCC);
642
            env->fpscr |= 0x11 << FPSCR_FPCC;
643
        }
644
        break;
645
    }
646
    /* Update the floating-point invalid operation summary */
647
    env->fpscr |= 1 << FPSCR_VX;
648
    /* Update the floating-point exception summary */
649
    env->fpscr |= 1 << FPSCR_FX;
650
    if (ve != 0) {
651
        /* Update the floating-point enabled exception summary */
652
        env->fpscr |= 1 << FPSCR_FEX;
653
        if (msr_fe0 != 0 || msr_fe1 != 0)
654
            do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
655
    }
656
}
657

    
658
static always_inline void float_zero_divide_excp (void)
659
{
660
    union {
661
        float64 f;
662
        uint64_t u;
663
    } u0, u1;
664
    
665

    
666
    env->fpscr |= 1 << FPSCR_ZX;
667
    env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
668
    /* Update the floating-point exception summary */
669
    env->fpscr |= 1 << FPSCR_FX;
670
    if (fpscr_ze != 0) {
671
        /* Update the floating-point enabled exception summary */
672
        env->fpscr |= 1 << FPSCR_FEX;
673
        if (msr_fe0 != 0 || msr_fe1 != 0) {
674
            do_raise_exception_err(POWERPC_EXCP_PROGRAM,
675
                                   POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
676
        }
677
    } else {
678
        /* Set the result to infinity */
679
        u0.f = FT0;
680
        u1.f = FT1;
681
        u0.u = ((u0.u ^ u1.u) & 0x8000000000000000ULL);
682
        u0.u |= 0x3FFULL << 52;
683
        FT0 = u0.f;
684
    }
685
}
686

    
687
static always_inline void float_overflow_excp (void)
688
{
689
    env->fpscr |= 1 << FPSCR_OX;
690
    /* Update the floating-point exception summary */
691
    env->fpscr |= 1 << FPSCR_FX;
692
    if (fpscr_oe != 0) {
693
        /* XXX: should adjust the result */
694
        /* Update the floating-point enabled exception summary */
695
        env->fpscr |= 1 << FPSCR_FEX;
696
        /* We must update the target FPR before raising the exception */
697
        env->exception_index = POWERPC_EXCP_PROGRAM;
698
        env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
699
    } else {
700
        env->fpscr |= 1 << FPSCR_XX;
701
        env->fpscr |= 1 << FPSCR_FI;
702
    }
703
}
704

    
705
static always_inline void float_underflow_excp (void)
706
{
707
    env->fpscr |= 1 << FPSCR_UX;
708
    /* Update the floating-point exception summary */
709
    env->fpscr |= 1 << FPSCR_FX;
710
    if (fpscr_ue != 0) {
711
        /* XXX: should adjust the result */
712
        /* Update the floating-point enabled exception summary */
713
        env->fpscr |= 1 << FPSCR_FEX;
714
        /* We must update the target FPR before raising the exception */
715
        env->exception_index = POWERPC_EXCP_PROGRAM;
716
        env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
717
    }
718
}
719

    
720
static always_inline void float_inexact_excp (void)
721
{
722
    env->fpscr |= 1 << FPSCR_XX;
723
    /* Update the floating-point exception summary */
724
    env->fpscr |= 1 << FPSCR_FX;
725
    if (fpscr_xe != 0) {
726
        /* Update the floating-point enabled exception summary */
727
        env->fpscr |= 1 << FPSCR_FEX;
728
        /* We must update the target FPR before raising the exception */
729
        env->exception_index = POWERPC_EXCP_PROGRAM;
730
        env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
731
    }
732
}
733

    
734
static always_inline void fpscr_set_rounding_mode (void)
735
{
736
    int rnd_type;
737

    
738
    /* Set rounding mode */
739
    switch (fpscr_rn) {
740
    case 0:
741
        /* Best approximation (round to nearest) */
742
        rnd_type = float_round_nearest_even;
743
        break;
744
    case 1:
745
        /* Smaller magnitude (round toward zero) */
746
        rnd_type = float_round_to_zero;
747
        break;
748
    case 2:
749
        /* Round toward +infinite */
750
        rnd_type = float_round_up;
751
        break;
752
    default:
753
    case 3:
754
        /* Round toward -infinite */
755
        rnd_type = float_round_down;
756
        break;
757
    }
758
    set_float_rounding_mode(rnd_type, &env->fp_status);
759
}
760

    
761
void do_fpscr_setbit (int bit)
762
{
763
    int prev;
764

    
765
    prev = (env->fpscr >> bit) & 1;
766
    env->fpscr |= 1 << bit;
767
    if (prev == 0) {
768
        switch (bit) {
769
        case FPSCR_VX:
770
            env->fpscr |= 1 << FPSCR_FX;
771
            if (fpscr_ve)
772
                goto raise_ve;
773
        case FPSCR_OX:
774
            env->fpscr |= 1 << FPSCR_FX;
775
            if (fpscr_oe)
776
                goto raise_oe;
777
            break;
778
        case FPSCR_UX:
779
            env->fpscr |= 1 << FPSCR_FX;
780
            if (fpscr_ue)
781
                goto raise_ue;
782
            break;
783
        case FPSCR_ZX:
784
            env->fpscr |= 1 << FPSCR_FX;
785
            if (fpscr_ze)
786
                goto raise_ze;
787
            break;
788
        case FPSCR_XX:
789
            env->fpscr |= 1 << FPSCR_FX;
790
            if (fpscr_xe)
791
                goto raise_xe;
792
            break;
793
        case FPSCR_VXSNAN:
794
        case FPSCR_VXISI:
795
        case FPSCR_VXIDI:
796
        case FPSCR_VXZDZ:
797
        case FPSCR_VXIMZ:
798
        case FPSCR_VXVC:
799
        case FPSCR_VXSOFT:
800
        case FPSCR_VXSQRT:
801
        case FPSCR_VXCVI:
802
            env->fpscr |= 1 << FPSCR_VX;
803
            env->fpscr |= 1 << FPSCR_FX;
804
            if (fpscr_ve != 0)
805
                goto raise_ve;
806
            break;
807
        case FPSCR_VE:
808
            if (fpscr_vx != 0) {
809
            raise_ve:
810
                env->error_code = POWERPC_EXCP_FP;
811
                if (fpscr_vxsnan)
812
                    env->error_code |= POWERPC_EXCP_FP_VXSNAN;
813
                if (fpscr_vxisi)
814
                    env->error_code |= POWERPC_EXCP_FP_VXISI;
815
                if (fpscr_vxidi)
816
                    env->error_code |= POWERPC_EXCP_FP_VXIDI;
817
                if (fpscr_vxzdz)
818
                    env->error_code |= POWERPC_EXCP_FP_VXZDZ;
819
                if (fpscr_vximz)
820
                    env->error_code |= POWERPC_EXCP_FP_VXIMZ;
821
                if (fpscr_vxvc)
822
                    env->error_code |= POWERPC_EXCP_FP_VXVC;
823
                if (fpscr_vxsoft)
824
                    env->error_code |= POWERPC_EXCP_FP_VXSOFT;
825
                if (fpscr_vxsqrt)
826
                    env->error_code |= POWERPC_EXCP_FP_VXSQRT;
827
                if (fpscr_vxcvi)
828
                    env->error_code |= POWERPC_EXCP_FP_VXCVI;
829
                goto raise_excp;
830
            }
831
            break;
832
        case FPSCR_OE:
833
            if (fpscr_ox != 0) {
834
            raise_oe:
835
                env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
836
                goto raise_excp;
837
            }
838
            break;
839
        case FPSCR_UE:
840
            if (fpscr_ux != 0) {
841
            raise_ue:
842
                env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
843
                goto raise_excp;
844
            }
845
            break;
846
        case FPSCR_ZE:
847
            if (fpscr_zx != 0) {
848
            raise_ze:
849
                env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
850
                goto raise_excp;
851
            }
852
            break;
853
        case FPSCR_XE:
854
            if (fpscr_xx != 0) {
855
            raise_xe:
856
                env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
857
                goto raise_excp;
858
            }
859
            break;
860
        case FPSCR_RN1:
861
        case FPSCR_RN:
862
            fpscr_set_rounding_mode();
863
            break;
864
        default:
865
            break;
866
        raise_excp:
867
            /* Update the floating-point enabled exception summary */
868
            env->fpscr |= 1 << FPSCR_FEX;
869
                /* We have to update Rc1 before raising the exception */
870
            env->exception_index = POWERPC_EXCP_PROGRAM;
871
            break;
872
        }
873
    }
874
}
875

    
876
#if defined(WORDS_BIGENDIAN)
877
#define WORD0 0
878
#define WORD1 1
879
#else
880
#define WORD0 1
881
#define WORD1 0
882
#endif
883
void do_store_fpscr (uint32_t mask)
884
{
885
    /*
886
     * We use only the 32 LSB of the incoming fpr
887
     */
888
    union {
889
        double d;
890
        struct {
891
            uint32_t u[2];
892
        } s;
893
    } u;
894
    uint32_t prev, new;
895
    int i;
896

    
897
    u.d = FT0;
898
    prev = env->fpscr;
899
    new = u.s.u[WORD1];
900
    new &= ~0x90000000;
901
    new |= prev & 0x90000000;
902
    for (i = 0; i < 7; i++) {
903
        if (mask & (1 << i)) {
904
            env->fpscr &= ~(0xF << (4 * i));
905
            env->fpscr |= new & (0xF << (4 * i));
906
        }
907
    }
908
    /* Update VX and FEX */
909
    if (fpscr_ix != 0)
910
        env->fpscr |= 1 << FPSCR_VX;
911
    if ((fpscr_ex & fpscr_eex) != 0) {
912
        env->fpscr |= 1 << FPSCR_FEX;
913
        env->exception_index = POWERPC_EXCP_PROGRAM;
914
        /* XXX: we should compute it properly */
915
        env->error_code = POWERPC_EXCP_FP;
916
    }
917
    fpscr_set_rounding_mode();
918
}
919
#undef WORD0
920
#undef WORD1
921

    
922
#ifdef CONFIG_SOFTFLOAT
923
void do_float_check_status (void)
924
{
925
    if (env->exception_index == POWERPC_EXCP_PROGRAM &&
926
        (env->error_code & POWERPC_EXCP_FP)) {
927
        /* Differred floating-point exception after target FPR update */
928
        if (msr_fe0 != 0 || msr_fe1 != 0)
929
            do_raise_exception_err(env->exception_index, env->error_code);
930
    } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
931
        float_overflow_excp();
932
    } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
933
        float_underflow_excp();
934
    } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
935
        float_inexact_excp();
936
    }
937
}
938
#endif
939

    
940
#if USE_PRECISE_EMULATION
941
void do_fadd (void)
942
{
943
    if (unlikely(float64_is_signaling_nan(FT0) ||
944
                 float64_is_signaling_nan(FT1))) {
945
        /* sNaN addition */
946
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
947
    } else if (likely(isfinite(FT0) || isfinite(FT1) ||
948
                      fpisneg(FT0) == fpisneg(FT1))) {
949
        FT0 = float64_add(FT0, FT1, &env->fp_status);
950
    } else {
951
        /* Magnitude subtraction of infinities */
952
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
953
    }
954
}
955

    
956
void do_fsub (void)
957
{
958
    if (unlikely(float64_is_signaling_nan(FT0) ||
959
                 float64_is_signaling_nan(FT1))) {
960
        /* sNaN subtraction */
961
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
962
    } else if (likely(isfinite(FT0) || isfinite(FT1) ||
963
                      fpisneg(FT0) != fpisneg(FT1))) {
964
        FT0 = float64_sub(FT0, FT1, &env->fp_status);
965
    } else {
966
        /* Magnitude subtraction of infinities */
967
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
968
    }
969
}
970

    
971
void do_fmul (void)
972
{
973
    if (unlikely(float64_is_signaling_nan(FT0) ||
974
                 float64_is_signaling_nan(FT1))) {
975
        /* sNaN multiplication */
976
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
977
    } else if (unlikely((ifinf(FT0) && iszero(FT1)) ||
978
                        (inzero(FT0) && isinfinity(FT1)))) {
979
        /* Multiplication of zero by infinity */
980
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
981
    } else {
982
        FT0 = float64_mul(FT0, FT1, &env->fp_status);
983
    }
984
}
985

    
986
void do_fdiv (void)
987
{
988
    if (unlikely(float64_is_signaling_nan(FT0) ||
989
                 float64_is_signaling_nan(FT1))) {
990
        /* sNaN division */
991
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
992
    } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
993
        /* Division of infinity by infinity */
994
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
995
    } else if (unlikely(iszero(FT1))) {
996
        if (iszero(FT0)) {
997
            /* Division of zero by zero */
998
            fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
999
        } else {
1000
            /* Division by zero */
1001
            float_zero_divide_excp();
1002
        }
1003
    } else {
1004
        FT0 = float64_div(FT0, FT1, &env->fp_status);
1005
    }
1006
}
1007
#endif /* USE_PRECISE_EMULATION */
1008

    
1009
void do_fctiw (void)
1010
{
1011
    union {
1012
        double d;
1013
        uint64_t i;
1014
    } p;
1015

    
1016
    if (unlikely(float64_is_signaling_nan(FT0))) {
1017
        /* sNaN conversion */
1018
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1019
    } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1020
        /* qNan / infinity conversion */
1021
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1022
    } else {
1023
        p.i = float64_to_int32(FT0, &env->fp_status);
1024
#if USE_PRECISE_EMULATION
1025
        /* XXX: higher bits are not supposed to be significant.
1026
         *     to make tests easier, return the same as a real PowerPC 750
1027
         */
1028
        p.i |= 0xFFF80000ULL << 32;
1029
#endif
1030
        FT0 = p.d;
1031
    }
1032
}
1033

    
1034
void do_fctiwz (void)
1035
{
1036
    union {
1037
        double d;
1038
        uint64_t i;
1039
    } p;
1040

    
1041
    if (unlikely(float64_is_signaling_nan(FT0))) {
1042
        /* sNaN conversion */
1043
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1044
    } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1045
        /* qNan / infinity conversion */
1046
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1047
    } else {
1048
        p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
1049
#if USE_PRECISE_EMULATION
1050
        /* XXX: higher bits are not supposed to be significant.
1051
         *     to make tests easier, return the same as a real PowerPC 750
1052
         */
1053
        p.i |= 0xFFF80000ULL << 32;
1054
#endif
1055
        FT0 = p.d;
1056
    }
1057
}
1058

    
1059
#if defined(TARGET_PPC64)
1060
void do_fcfid (void)
1061
{
1062
    union {
1063
        double d;
1064
        uint64_t i;
1065
    } p;
1066

    
1067
    p.d = FT0;
1068
    FT0 = int64_to_float64(p.i, &env->fp_status);
1069
}
1070

    
1071
void do_fctid (void)
1072
{
1073
    union {
1074
        double d;
1075
        uint64_t i;
1076
    } p;
1077

    
1078
    if (unlikely(float64_is_signaling_nan(FT0))) {
1079
        /* sNaN conversion */
1080
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1081
    } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1082
        /* qNan / infinity conversion */
1083
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1084
    } else {
1085
        p.i = float64_to_int64(FT0, &env->fp_status);
1086
        FT0 = p.d;
1087
    }
1088
}
1089

    
1090
void do_fctidz (void)
1091
{
1092
    union {
1093
        double d;
1094
        uint64_t i;
1095
    } p;
1096

    
1097
    if (unlikely(float64_is_signaling_nan(FT0))) {
1098
        /* sNaN conversion */
1099
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1100
    } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1101
        /* qNan / infinity conversion */
1102
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1103
    } else {
1104
        p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
1105
        FT0 = p.d;
1106
    }
1107
}
1108

    
1109
#endif
1110

    
1111
static always_inline void do_fri (int rounding_mode)
1112
{
1113
    if (unlikely(float64_is_signaling_nan(FT0))) {
1114
        /* sNaN round */
1115
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1116
    } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1117
        /* qNan / infinity round */
1118
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1119
    } else {
1120
        set_float_rounding_mode(rounding_mode, &env->fp_status);
1121
        FT0 = float64_round_to_int(FT0, &env->fp_status);
1122
        /* Restore rounding mode from FPSCR */
1123
        fpscr_set_rounding_mode();
1124
    }
1125
}
1126

    
1127
void do_frin (void)
1128
{
1129
    do_fri(float_round_nearest_even);
1130
}
1131

    
1132
void do_friz (void)
1133
{
1134
    do_fri(float_round_to_zero);
1135
}
1136

    
1137
void do_frip (void)
1138
{
1139
    do_fri(float_round_up);
1140
}
1141

    
1142
void do_frim (void)
1143
{
1144
    do_fri(float_round_down);
1145
}
1146

    
1147
#if USE_PRECISE_EMULATION
1148
void do_fmadd (void)
1149
{
1150
    if (unlikely(float64_is_signaling_nan(FT0) ||
1151
                 float64_is_signaling_nan(FT1) ||
1152
                 float64_is_signaling_nan(FT2))) {
1153
        /* sNaN operation */
1154
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1155
    } else {
1156
#ifdef FLOAT128
1157
        /* This is the way the PowerPC specification defines it */
1158
        float128 ft0_128, ft1_128;
1159

    
1160
        ft0_128 = float64_to_float128(FT0, &env->fp_status);
1161
        ft1_128 = float64_to_float128(FT1, &env->fp_status);
1162
        ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1163
        ft1_128 = float64_to_float128(FT2, &env->fp_status);
1164
        ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1165
        FT0 = float128_to_float64(ft0_128, &env->fp_status);
1166
#else
1167
        /* This is OK on x86 hosts */
1168
        FT0 = (FT0 * FT1) + FT2;
1169
#endif
1170
    }
1171
}
1172

    
1173
void do_fmsub (void)
1174
{
1175
    if (unlikely(float64_is_signaling_nan(FT0) ||
1176
                 float64_is_signaling_nan(FT1) ||
1177
                 float64_is_signaling_nan(FT2))) {
1178
        /* sNaN operation */
1179
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1180
    } else {
1181
#ifdef FLOAT128
1182
        /* This is the way the PowerPC specification defines it */
1183
        float128 ft0_128, ft1_128;
1184

    
1185
        ft0_128 = float64_to_float128(FT0, &env->fp_status);
1186
        ft1_128 = float64_to_float128(FT1, &env->fp_status);
1187
        ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1188
        ft1_128 = float64_to_float128(FT2, &env->fp_status);
1189
        ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1190
        FT0 = float128_to_float64(ft0_128, &env->fp_status);
1191
#else
1192
        /* This is OK on x86 hosts */
1193
        FT0 = (FT0 * FT1) - FT2;
1194
#endif
1195
    }
1196
}
1197
#endif /* USE_PRECISE_EMULATION */
1198

    
1199
void do_fnmadd (void)
1200
{
1201
    if (unlikely(float64_is_signaling_nan(FT0) ||
1202
                 float64_is_signaling_nan(FT1) ||
1203
                 float64_is_signaling_nan(FT2))) {
1204
        /* sNaN operation */
1205
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1206
    } else {
1207
#if USE_PRECISE_EMULATION
1208
#ifdef FLOAT128
1209
        /* This is the way the PowerPC specification defines it */
1210
        float128 ft0_128, ft1_128;
1211

    
1212
        ft0_128 = float64_to_float128(FT0, &env->fp_status);
1213
        ft1_128 = float64_to_float128(FT1, &env->fp_status);
1214
        ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1215
        ft1_128 = float64_to_float128(FT2, &env->fp_status);
1216
        ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1217
        FT0 = float128_to_float64(ft0_128, &env->fp_status);
1218
#else
1219
        /* This is OK on x86 hosts */
1220
        FT0 = (FT0 * FT1) + FT2;
1221
#endif
1222
#else
1223
        FT0 = float64_mul(FT0, FT1, &env->fp_status);
1224
        FT0 = float64_add(FT0, FT2, &env->fp_status);
1225
#endif
1226
        if (likely(!isnan(FT0)))
1227
            FT0 = float64_chs(FT0);
1228
    }
1229
}
1230

    
1231
void do_fnmsub (void)
1232
{
1233
    if (unlikely(float64_is_signaling_nan(FT0) ||
1234
                 float64_is_signaling_nan(FT1) ||
1235
                 float64_is_signaling_nan(FT2))) {
1236
        /* sNaN operation */
1237
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1238
    } else {
1239
#if USE_PRECISE_EMULATION
1240
#ifdef FLOAT128
1241
        /* This is the way the PowerPC specification defines it */
1242
        float128 ft0_128, ft1_128;
1243

    
1244
        ft0_128 = float64_to_float128(FT0, &env->fp_status);
1245
        ft1_128 = float64_to_float128(FT1, &env->fp_status);
1246
        ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1247
        ft1_128 = float64_to_float128(FT2, &env->fp_status);
1248
        ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1249
        FT0 = float128_to_float64(ft0_128, &env->fp_status);
1250
#else
1251
        /* This is OK on x86 hosts */
1252
        FT0 = (FT0 * FT1) - FT2;
1253
#endif
1254
#else
1255
        FT0 = float64_mul(FT0, FT1, &env->fp_status);
1256
        FT0 = float64_sub(FT0, FT2, &env->fp_status);
1257
#endif
1258
        if (likely(!isnan(FT0)))
1259
            FT0 = float64_chs(FT0);
1260
    }
1261
}
1262

    
1263
#if USE_PRECISE_EMULATION
1264
void do_frsp (void)
1265
{
1266
    if (unlikely(float64_is_signaling_nan(FT0))) {
1267
        /* sNaN square root */
1268
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1269
    } else {
1270
        FT0 = float64_to_float32(FT0, &env->fp_status);
1271
    }
1272
}
1273
#endif /* USE_PRECISE_EMULATION */
1274

    
1275
void do_fsqrt (void)
1276
{
1277
    if (unlikely(float64_is_signaling_nan(FT0))) {
1278
        /* sNaN square root */
1279
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1280
    } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1281
        /* Square root of a negative nonzero number */
1282
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1283
    } else {
1284
        FT0 = float64_sqrt(FT0, &env->fp_status);
1285
    }
1286
}
1287

    
1288
void do_fre (void)
1289
{
1290
    union {
1291
        double d;
1292
        uint64_t i;
1293
    } p;
1294

    
1295
    if (unlikely(float64_is_signaling_nan(FT0))) {
1296
        /* sNaN reciprocal */
1297
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1298
    } else if (unlikely(iszero(FT0))) {
1299
        /* Zero reciprocal */
1300
        float_zero_divide_excp();
1301
    } else if (likely(isnormal(FT0))) {
1302
        FT0 = float64_div(1.0, FT0, &env->fp_status);
1303
    } else {
1304
        p.d = FT0;
1305
        if (p.i == 0x8000000000000000ULL) {
1306
            p.i = 0xFFF0000000000000ULL;
1307
        } else if (p.i == 0x0000000000000000ULL) {
1308
            p.i = 0x7FF0000000000000ULL;
1309
        } else if (isnan(FT0)) {
1310
            p.i = 0x7FF8000000000000ULL;
1311
        } else if (fpisneg(FT0)) {
1312
            p.i = 0x8000000000000000ULL;
1313
        } else {
1314
            p.i = 0x0000000000000000ULL;
1315
        }
1316
        FT0 = p.d;
1317
    }
1318
}
1319

    
1320
void do_fres (void)
1321
{
1322
    union {
1323
        double d;
1324
        uint64_t i;
1325
    } p;
1326

    
1327
    if (unlikely(float64_is_signaling_nan(FT0))) {
1328
        /* sNaN reciprocal */
1329
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1330
    } else if (unlikely(iszero(FT0))) {
1331
        /* Zero reciprocal */
1332
        float_zero_divide_excp();
1333
    } else if (likely(isnormal(FT0))) {
1334
#if USE_PRECISE_EMULATION
1335
        FT0 = float64_div(1.0, FT0, &env->fp_status);
1336
        FT0 = float64_to_float32(FT0, &env->fp_status);
1337
#else
1338
        FT0 = float32_div(1.0, FT0, &env->fp_status);
1339
#endif
1340
    } else {
1341
        p.d = FT0;
1342
        if (p.i == 0x8000000000000000ULL) {
1343
            p.i = 0xFFF0000000000000ULL;
1344
        } else if (p.i == 0x0000000000000000ULL) {
1345
            p.i = 0x7FF0000000000000ULL;
1346
        } else if (isnan(FT0)) {
1347
            p.i = 0x7FF8000000000000ULL;
1348
        } else if (fpisneg(FT0)) {
1349
            p.i = 0x8000000000000000ULL;
1350
        } else {
1351
            p.i = 0x0000000000000000ULL;
1352
        }
1353
        FT0 = p.d;
1354
    }
1355
}
1356

    
1357
void do_frsqrte (void)
1358
{
1359
    union {
1360
        double d;
1361
        uint64_t i;
1362
    } p;
1363

    
1364
    if (unlikely(float64_is_signaling_nan(FT0))) {
1365
        /* sNaN reciprocal square root */
1366
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1367
    } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1368
        /* Reciprocal square root of a negative nonzero number */
1369
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1370
    } else if (likely(isnormal(FT0))) {
1371
        FT0 = float64_sqrt(FT0, &env->fp_status);
1372
        FT0 = float32_div(1.0, FT0, &env->fp_status);
1373
    } else {
1374
        p.d = FT0;
1375
        if (p.i == 0x8000000000000000ULL) {
1376
            p.i = 0xFFF0000000000000ULL;
1377
        } else if (p.i == 0x0000000000000000ULL) {
1378
            p.i = 0x7FF0000000000000ULL;
1379
        } else if (isnan(FT0)) {
1380
            p.i |= 0x000FFFFFFFFFFFFFULL;
1381
        } else if (fpisneg(FT0)) {
1382
            p.i = 0x7FF8000000000000ULL;
1383
        } else {
1384
            p.i = 0x0000000000000000ULL;
1385
        }
1386
        FT0 = p.d;
1387
    }
1388
}
1389

    
1390
void do_fsel (void)
1391
{
1392
    if (!fpisneg(FT0) || iszero(FT0))
1393
        FT0 = FT1;
1394
    else
1395
        FT0 = FT2;
1396
}
1397

    
1398
void do_fcmpu (void)
1399
{
1400
    if (unlikely(float64_is_signaling_nan(FT0) ||
1401
                 float64_is_signaling_nan(FT1))) {
1402
        /* sNaN comparison */
1403
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1404
    } else {
1405
        if (float64_lt(FT0, FT1, &env->fp_status)) {
1406
            T0 = 0x08UL;
1407
        } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1408
            T0 = 0x04UL;
1409
        } else {
1410
            T0 = 0x02UL;
1411
        }
1412
    }
1413
    env->fpscr &= ~(0x0F << FPSCR_FPRF);
1414
    env->fpscr |= T0 << FPSCR_FPRF;
1415
}
1416

    
1417
void do_fcmpo (void)
1418
{
1419
    if (unlikely(float64_is_nan(FT0) ||
1420
                 float64_is_nan(FT1))) {
1421
        if (float64_is_signaling_nan(FT0) ||
1422
            float64_is_signaling_nan(FT1)) {
1423
            /* sNaN comparison */
1424
            fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1425
                                  POWERPC_EXCP_FP_VXVC);
1426
        } else {
1427
            /* qNaN comparison */
1428
            fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1429
        }
1430
    } else {
1431
        if (float64_lt(FT0, FT1, &env->fp_status)) {
1432
            T0 = 0x08UL;
1433
        } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1434
            T0 = 0x04UL;
1435
        } else {
1436
            T0 = 0x02UL;
1437
        }
1438
    }
1439
    env->fpscr &= ~(0x0F << FPSCR_FPRF);
1440
    env->fpscr |= T0 << FPSCR_FPRF;
1441
}
1442

    
1443
#if !defined (CONFIG_USER_ONLY)
1444
void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1445

    
1446
void do_store_msr (void)
1447
{
1448
    T0 = hreg_store_msr(env, T0);
1449
    if (T0 != 0) {
1450
        env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1451
        do_raise_exception(T0);
1452
    }
1453
}
1454

    
1455
static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1456
                                    target_ulong msrm, int keep_msrh)
1457
{
1458
#if defined(TARGET_PPC64)
1459
    if (msr & (1ULL << MSR_SF)) {
1460
        nip = (uint64_t)nip;
1461
        msr &= (uint64_t)msrm;
1462
    } else {
1463
        nip = (uint32_t)nip;
1464
        msr = (uint32_t)(msr & msrm);
1465
        if (keep_msrh)
1466
            msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1467
    }
1468
#else
1469
    nip = (uint32_t)nip;
1470
    msr &= (uint32_t)msrm;
1471
#endif
1472
    /* XXX: beware: this is false if VLE is supported */
1473
    env->nip = nip & ~((target_ulong)0x00000003);
1474
    hreg_store_msr(env, msr);
1475
#if defined (DEBUG_OP)
1476
    cpu_dump_rfi(env->nip, env->msr);
1477
#endif
1478
    /* No need to raise an exception here,
1479
     * as rfi is always the last insn of a TB
1480
     */
1481
    env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1482
}
1483

    
1484
void do_rfi (void)
1485
{
1486
    __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1487
             ~((target_ulong)0xFFFF0000), 1);
1488
}
1489

    
1490
#if defined(TARGET_PPC64)
1491
void do_rfid (void)
1492
{
1493
    __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1494
             ~((target_ulong)0xFFFF0000), 0);
1495
}
1496
#endif
1497
#if defined(TARGET_PPC64H)
1498
void do_hrfid (void)
1499
{
1500
    __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1501
             ~((target_ulong)0xFFFF0000), 0);
1502
}
1503
#endif
1504
#endif
1505

    
1506
void do_tw (int flags)
1507
{
1508
    if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1509
                  ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1510
                  ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1511
                  ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
1512
                  ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
1513
        do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1514
    }
1515
}
1516

    
1517
#if defined(TARGET_PPC64)
1518
void do_td (int flags)
1519
{
1520
    if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1521
                  ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1522
                  ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1523
                  ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1524
                  ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
1525
        do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1526
}
1527
#endif
1528

    
1529
/*****************************************************************************/
1530
/* PowerPC 601 specific instructions (POWER bridge) */
1531
void do_POWER_abso (void)
1532
{
1533
    if ((uint32_t)T0 == INT32_MIN) {
1534
        T0 = INT32_MAX;
1535
        xer_ov = 1;
1536
        xer_so = 1;
1537
    } else {
1538
        T0 = -T0;
1539
        xer_ov = 0;
1540
    }
1541
}
1542

    
1543
void do_POWER_clcs (void)
1544
{
1545
    switch (T0) {
1546
    case 0x0CUL:
1547
        /* Instruction cache line size */
1548
        T0 = env->icache_line_size;
1549
        break;
1550
    case 0x0DUL:
1551
        /* Data cache line size */
1552
        T0 = env->dcache_line_size;
1553
        break;
1554
    case 0x0EUL:
1555
        /* Minimum cache line size */
1556
        T0 = env->icache_line_size < env->dcache_line_size ?
1557
            env->icache_line_size : env->dcache_line_size;
1558
        break;
1559
    case 0x0FUL:
1560
        /* Maximum cache line size */
1561
        T0 = env->icache_line_size > env->dcache_line_size ?
1562
            env->icache_line_size : env->dcache_line_size;
1563
        break;
1564
    default:
1565
        /* Undefined */
1566
        break;
1567
    }
1568
}
1569

    
1570
void do_POWER_div (void)
1571
{
1572
    uint64_t tmp;
1573

    
1574
    if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1575
        T0 = (long)((-1) * (T0 >> 31));
1576
        env->spr[SPR_MQ] = 0;
1577
    } else {
1578
        tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1579
        env->spr[SPR_MQ] = tmp % T1;
1580
        T0 = tmp / (int32_t)T1;
1581
    }
1582
}
1583

    
1584
void do_POWER_divo (void)
1585
{
1586
    int64_t tmp;
1587

    
1588
    if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1589
        T0 = (long)((-1) * (T0 >> 31));
1590
        env->spr[SPR_MQ] = 0;
1591
        xer_ov = 1;
1592
        xer_so = 1;
1593
    } else {
1594
        tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1595
        env->spr[SPR_MQ] = tmp % T1;
1596
        tmp /= (int32_t)T1;
1597
        if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1598
            xer_ov = 1;
1599
            xer_so = 1;
1600
        } else {
1601
            xer_ov = 0;
1602
        }
1603
        T0 = tmp;
1604
    }
1605
}
1606

    
1607
void do_POWER_divs (void)
1608
{
1609
    if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1610
        T0 = (long)((-1) * (T0 >> 31));
1611
        env->spr[SPR_MQ] = 0;
1612
    } else {
1613
        env->spr[SPR_MQ] = T0 % T1;
1614
        T0 = (int32_t)T0 / (int32_t)T1;
1615
    }
1616
}
1617

    
1618
void do_POWER_divso (void)
1619
{
1620
    if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1621
        T0 = (long)((-1) * (T0 >> 31));
1622
        env->spr[SPR_MQ] = 0;
1623
        xer_ov = 1;
1624
        xer_so = 1;
1625
    } else {
1626
        T0 = (int32_t)T0 / (int32_t)T1;
1627
        env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1628
        xer_ov = 0;
1629
    }
1630
}
1631

    
1632
void do_POWER_dozo (void)
1633
{
1634
    if ((int32_t)T1 > (int32_t)T0) {
1635
        T2 = T0;
1636
        T0 = T1 - T0;
1637
        if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1638
            ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1639
            xer_ov = 1;
1640
            xer_so = 1;
1641
        } else {
1642
            xer_ov = 0;
1643
        }
1644
    } else {
1645
        T0 = 0;
1646
        xer_ov = 0;
1647
    }
1648
}
1649

    
1650
void do_POWER_maskg (void)
1651
{
1652
    uint32_t ret;
1653

    
1654
    if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1655
        ret = -1;
1656
    } else {
1657
        ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
1658
            (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
1659
        if ((uint32_t)T0 > (uint32_t)T1)
1660
            ret = ~ret;
1661
    }
1662
    T0 = ret;
1663
}
1664

    
1665
void do_POWER_mulo (void)
1666
{
1667
    uint64_t tmp;
1668

    
1669
    tmp = (uint64_t)T0 * (uint64_t)T1;
1670
    env->spr[SPR_MQ] = tmp >> 32;
1671
    T0 = tmp;
1672
    if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1673
        xer_ov = 1;
1674
        xer_so = 1;
1675
    } else {
1676
        xer_ov = 0;
1677
    }
1678
}
1679

    
1680
#if !defined (CONFIG_USER_ONLY)
1681
void do_POWER_rac (void)
1682
{
1683
#if 0
1684
    mmu_ctx_t ctx;
1685

1686
    /* We don't have to generate many instances of this instruction,
1687
     * as rac is supervisor only.
1688
     */
1689
    if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
1690
        T0 = ctx.raddr;
1691
#endif
1692
}
1693

    
1694
void do_POWER_rfsvc (void)
1695
{
1696
    __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1697
}
1698

    
1699
/* PowerPC 601 BAT management helper */
1700
void do_store_601_batu (int nr)
1701
{
1702
    do_store_ibatu(env, nr, (uint32_t)T0);
1703
    env->DBAT[0][nr] = env->IBAT[0][nr];
1704
    env->DBAT[1][nr] = env->IBAT[1][nr];
1705
}
1706
#endif
1707

    
1708
/*****************************************************************************/
1709
/* 602 specific instructions */
1710
/* mfrom is the most crazy instruction ever seen, imho ! */
1711
/* Real implementation uses a ROM table. Do the same */
1712
#define USE_MFROM_ROM_TABLE
1713
void do_op_602_mfrom (void)
1714
{
1715
    if (likely(T0 < 602)) {
1716
#if defined(USE_MFROM_ROM_TABLE)
1717
#include "mfrom_table.c"
1718
        T0 = mfrom_ROM_table[T0];
1719
#else
1720
        double d;
1721
        /* Extremly decomposed:
1722
         *                    -T0 / 256
1723
         * T0 = 256 * log10(10          + 1.0) + 0.5
1724
         */
1725
        d = T0;
1726
        d = float64_div(d, 256, &env->fp_status);
1727
        d = float64_chs(d);
1728
        d = exp10(d); // XXX: use float emulation function
1729
        d = float64_add(d, 1.0, &env->fp_status);
1730
        d = log10(d); // XXX: use float emulation function
1731
        d = float64_mul(d, 256, &env->fp_status);
1732
        d = float64_add(d, 0.5, &env->fp_status);
1733
        T0 = float64_round_to_int(d, &env->fp_status);
1734
#endif
1735
    } else {
1736
        T0 = 0;
1737
    }
1738
}
1739

    
1740
/*****************************************************************************/
1741
/* Embedded PowerPC specific helpers */
1742
void do_405_check_ov (void)
1743
{
1744
    if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1745
               !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1746
        xer_ov = 0;
1747
    } else {
1748
        xer_ov = 1;
1749
        xer_so = 1;
1750
    }
1751
}
1752

    
1753
void do_405_check_sat (void)
1754
{
1755
    if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1756
                !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1757
        /* Saturate result */
1758
        if (T2 >> 31) {
1759
            T0 = INT32_MIN;
1760
        } else {
1761
            T0 = INT32_MAX;
1762
        }
1763
    }
1764
}
1765

    
1766
/* XXX: to be improved to check access rights when in user-mode */
1767
void do_load_dcr (void)
1768
{
1769
    target_ulong val;
1770

    
1771
    if (unlikely(env->dcr_env == NULL)) {
1772
        if (loglevel != 0) {
1773
            fprintf(logfile, "No DCR environment\n");
1774
        }
1775
        do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1776
                               POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1777
    } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1778
        if (loglevel != 0) {
1779
            fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1780
        }
1781
        do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1782
                               POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1783
    } else {
1784
        T0 = val;
1785
    }
1786
}
1787

    
1788
void do_store_dcr (void)
1789
{
1790
    if (unlikely(env->dcr_env == NULL)) {
1791
        if (loglevel != 0) {
1792
            fprintf(logfile, "No DCR environment\n");
1793
        }
1794
        do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1795
                               POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1796
    } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1797
        if (loglevel != 0) {
1798
            fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1799
        }
1800
        do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1801
                               POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1802
    }
1803
}
1804

    
1805
#if !defined(CONFIG_USER_ONLY)
1806
void do_40x_rfci (void)
1807
{
1808
    __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1809
             ~((target_ulong)0xFFFF0000), 0);
1810
}
1811

    
1812
void do_rfci (void)
1813
{
1814
    __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1815
             ~((target_ulong)0x3FFF0000), 0);
1816
}
1817

    
1818
void do_rfdi (void)
1819
{
1820
    __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1821
             ~((target_ulong)0x3FFF0000), 0);
1822
}
1823

    
1824
void do_rfmci (void)
1825
{
1826
    __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1827
             ~((target_ulong)0x3FFF0000), 0);
1828
}
1829

    
1830
void do_load_403_pb (int num)
1831
{
1832
    T0 = env->pb[num];
1833
}
1834

    
1835
void do_store_403_pb (int num)
1836
{
1837
    if (likely(env->pb[num] != T0)) {
1838
        env->pb[num] = T0;
1839
        /* Should be optimized */
1840
        tlb_flush(env, 1);
1841
    }
1842
}
1843
#endif
1844

    
1845
/* 440 specific */
1846
void do_440_dlmzb (void)
1847
{
1848
    target_ulong mask;
1849
    int i;
1850

    
1851
    i = 1;
1852
    for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1853
        if ((T0 & mask) == 0)
1854
            goto done;
1855
        i++;
1856
    }
1857
    for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1858
        if ((T1 & mask) == 0)
1859
            break;
1860
        i++;
1861
    }
1862
 done:
1863
    T0 = i;
1864
}
1865

    
1866
#if defined(TARGET_PPCEMB)
1867
/* SPE extension helpers */
1868
/* Use a table to make this quicker */
1869
static uint8_t hbrev[16] = {
1870
    0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1871
    0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1872
};
1873

    
1874
static always_inline uint8_t byte_reverse (uint8_t val)
1875
{
1876
    return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1877
}
1878

    
1879
static always_inline uint32_t word_reverse (uint32_t val)
1880
{
1881
    return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1882
        (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1883
}
1884

    
1885
#define MASKBITS 16 // Random value - to be fixed
1886
void do_brinc (void)
1887
{
1888
    uint32_t a, b, d, mask;
1889

    
1890
    mask = (uint32_t)(-1UL) >> MASKBITS;
1891
    b = T1_64 & mask;
1892
    a = T0_64 & mask;
1893
    d = word_reverse(1 + word_reverse(a | ~mask));
1894
    T0_64 = (T0_64 & ~mask) | (d & mask);
1895
}
1896

    
1897
#define DO_SPE_OP2(name)                                                      \
1898
void do_ev##name (void)                                                       \
1899
{                                                                             \
1900
    T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) |         \
1901
        (uint64_t)_do_e##name(T0_64, T1_64);                                  \
1902
}
1903

    
1904
#define DO_SPE_OP1(name)                                                      \
1905
void do_ev##name (void)                                                       \
1906
{                                                                             \
1907
    T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) |                      \
1908
        (uint64_t)_do_e##name(T0_64);                                         \
1909
}
1910

    
1911
/* Fixed-point vector arithmetic */
1912
static always_inline uint32_t _do_eabs (uint32_t val)
1913
{
1914
    if (val != 0x80000000)
1915
        val &= ~0x80000000;
1916

    
1917
    return val;
1918
}
1919

    
1920
static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1921
{
1922
    return op1 + op2;
1923
}
1924

    
1925
static always_inline int _do_ecntlsw (uint32_t val)
1926
{
1927
    if (val & 0x80000000)
1928
        return _do_cntlzw(~val);
1929
    else
1930
        return _do_cntlzw(val);
1931
}
1932

    
1933
static always_inline int _do_ecntlzw (uint32_t val)
1934
{
1935
    return _do_cntlzw(val);
1936
}
1937

    
1938
static always_inline uint32_t _do_eneg (uint32_t val)
1939
{
1940
    if (val != 0x80000000)
1941
        val ^= 0x80000000;
1942

    
1943
    return val;
1944
}
1945

    
1946
static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1947
{
1948
    return rotl32(op1, op2);
1949
}
1950

    
1951
static always_inline uint32_t _do_erndw (uint32_t val)
1952
{
1953
    return (val + 0x000080000000) & 0xFFFF0000;
1954
}
1955

    
1956
static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1957
{
1958
    /* No error here: 6 bits are used */
1959
    return op1 << (op2 & 0x3F);
1960
}
1961

    
1962
static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1963
{
1964
    /* No error here: 6 bits are used */
1965
    return op1 >> (op2 & 0x3F);
1966
}
1967

    
1968
static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1969
{
1970
    /* No error here: 6 bits are used */
1971
    return op1 >> (op2 & 0x3F);
1972
}
1973

    
1974
static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1975
{
1976
    return op2 - op1;
1977
}
1978

    
1979
/* evabs */
1980
DO_SPE_OP1(abs);
1981
/* evaddw */
1982
DO_SPE_OP2(addw);
1983
/* evcntlsw */
1984
DO_SPE_OP1(cntlsw);
1985
/* evcntlzw */
1986
DO_SPE_OP1(cntlzw);
1987
/* evneg */
1988
DO_SPE_OP1(neg);
1989
/* evrlw */
1990
DO_SPE_OP2(rlw);
1991
/* evrnd */
1992
DO_SPE_OP1(rndw);
1993
/* evslw */
1994
DO_SPE_OP2(slw);
1995
/* evsrws */
1996
DO_SPE_OP2(srws);
1997
/* evsrwu */
1998
DO_SPE_OP2(srwu);
1999
/* evsubfw */
2000
DO_SPE_OP2(subfw);
2001

    
2002
/* evsel is a little bit more complicated... */
2003
static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
2004
{
2005
    if (n)
2006
        return op1;
2007
    else
2008
        return op2;
2009
}
2010

    
2011
void do_evsel (void)
2012
{
2013
    T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
2014
        (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
2015
}
2016

    
2017
/* Fixed-point vector comparisons */
2018
#define DO_SPE_CMP(name)                                                      \
2019
void do_ev##name (void)                                                       \
2020
{                                                                             \
2021
    T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32,                   \
2022
                                               T1_64 >> 32) << 32,            \
2023
                         _do_e##name(T0_64, T1_64));                          \
2024
}
2025

    
2026
static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
2027
{
2028
    return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2029
}
2030
static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
2031
{
2032
    return op1 == op2 ? 1 : 0;
2033
}
2034

    
2035
static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
2036
{
2037
    return op1 > op2 ? 1 : 0;
2038
}
2039

    
2040
static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
2041
{
2042
    return op1 > op2 ? 1 : 0;
2043
}
2044

    
2045
static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
2046
{
2047
    return op1 < op2 ? 1 : 0;
2048
}
2049

    
2050
static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
2051
{
2052
    return op1 < op2 ? 1 : 0;
2053
}
2054

    
2055
/* evcmpeq */
2056
DO_SPE_CMP(cmpeq);
2057
/* evcmpgts */
2058
DO_SPE_CMP(cmpgts);
2059
/* evcmpgtu */
2060
DO_SPE_CMP(cmpgtu);
2061
/* evcmplts */
2062
DO_SPE_CMP(cmplts);
2063
/* evcmpltu */
2064
DO_SPE_CMP(cmpltu);
2065

    
2066
/* Single precision floating-point conversions from/to integer */
2067
static always_inline uint32_t _do_efscfsi (int32_t val)
2068
{
2069
    union {
2070
        uint32_t u;
2071
        float32 f;
2072
    } u;
2073

    
2074
    u.f = int32_to_float32(val, &env->spe_status);
2075

    
2076
    return u.u;
2077
}
2078

    
2079
static always_inline uint32_t _do_efscfui (uint32_t val)
2080
{
2081
    union {
2082
        uint32_t u;
2083
        float32 f;
2084
    } u;
2085

    
2086
    u.f = uint32_to_float32(val, &env->spe_status);
2087

    
2088
    return u.u;
2089
}
2090

    
2091
static always_inline int32_t _do_efsctsi (uint32_t val)
2092
{
2093
    union {
2094
        int32_t u;
2095
        float32 f;
2096
    } u;
2097

    
2098
    u.u = val;
2099
    /* NaN are not treated the same way IEEE 754 does */
2100
    if (unlikely(isnan(u.f)))
2101
        return 0;
2102

    
2103
    return float32_to_int32(u.f, &env->spe_status);
2104
}
2105

    
2106
static always_inline uint32_t _do_efsctui (uint32_t val)
2107
{
2108
    union {
2109
        int32_t u;
2110
        float32 f;
2111
    } u;
2112

    
2113
    u.u = val;
2114
    /* NaN are not treated the same way IEEE 754 does */
2115
    if (unlikely(isnan(u.f)))
2116
        return 0;
2117

    
2118
    return float32_to_uint32(u.f, &env->spe_status);
2119
}
2120

    
2121
static always_inline int32_t _do_efsctsiz (uint32_t val)
2122
{
2123
    union {
2124
        int32_t u;
2125
        float32 f;
2126
    } u;
2127

    
2128
    u.u = val;
2129
    /* NaN are not treated the same way IEEE 754 does */
2130
    if (unlikely(isnan(u.f)))
2131
        return 0;
2132

    
2133
    return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2134
}
2135

    
2136
static always_inline uint32_t _do_efsctuiz (uint32_t val)
2137
{
2138
    union {
2139
        int32_t u;
2140
        float32 f;
2141
    } u;
2142

    
2143
    u.u = val;
2144
    /* NaN are not treated the same way IEEE 754 does */
2145
    if (unlikely(isnan(u.f)))
2146
        return 0;
2147

    
2148
    return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2149
}
2150

    
2151
void do_efscfsi (void)
2152
{
2153
    T0_64 = _do_efscfsi(T0_64);
2154
}
2155

    
2156
void do_efscfui (void)
2157
{
2158
    T0_64 = _do_efscfui(T0_64);
2159
}
2160

    
2161
void do_efsctsi (void)
2162
{
2163
    T0_64 = _do_efsctsi(T0_64);
2164
}
2165

    
2166
void do_efsctui (void)
2167
{
2168
    T0_64 = _do_efsctui(T0_64);
2169
}
2170

    
2171
void do_efsctsiz (void)
2172
{
2173
    T0_64 = _do_efsctsiz(T0_64);
2174
}
2175

    
2176
void do_efsctuiz (void)
2177
{
2178
    T0_64 = _do_efsctuiz(T0_64);
2179
}
2180

    
2181
/* Single precision floating-point conversion to/from fractional */
2182
static always_inline uint32_t _do_efscfsf (uint32_t val)
2183
{
2184
    union {
2185
        uint32_t u;
2186
        float32 f;
2187
    } u;
2188
    float32 tmp;
2189

    
2190
    u.f = int32_to_float32(val, &env->spe_status);
2191
    tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2192
    u.f = float32_div(u.f, tmp, &env->spe_status);
2193

    
2194
    return u.u;
2195
}
2196

    
2197
static always_inline uint32_t _do_efscfuf (uint32_t val)
2198
{
2199
    union {
2200
        uint32_t u;
2201
        float32 f;
2202
    } u;
2203
    float32 tmp;
2204

    
2205
    u.f = uint32_to_float32(val, &env->spe_status);
2206
    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2207
    u.f = float32_div(u.f, tmp, &env->spe_status);
2208

    
2209
    return u.u;
2210
}
2211

    
2212
static always_inline int32_t _do_efsctsf (uint32_t val)
2213
{
2214
    union {
2215
        int32_t u;
2216
        float32 f;
2217
    } u;
2218
    float32 tmp;
2219

    
2220
    u.u = val;
2221
    /* NaN are not treated the same way IEEE 754 does */
2222
    if (unlikely(isnan(u.f)))
2223
        return 0;
2224
    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2225
    u.f = float32_mul(u.f, tmp, &env->spe_status);
2226

    
2227
    return float32_to_int32(u.f, &env->spe_status);
2228
}
2229

    
2230
static always_inline uint32_t _do_efsctuf (uint32_t val)
2231
{
2232
    union {
2233
        int32_t u;
2234
        float32 f;
2235
    } u;
2236
    float32 tmp;
2237

    
2238
    u.u = val;
2239
    /* NaN are not treated the same way IEEE 754 does */
2240
    if (unlikely(isnan(u.f)))
2241
        return 0;
2242
    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2243
    u.f = float32_mul(u.f, tmp, &env->spe_status);
2244

    
2245
    return float32_to_uint32(u.f, &env->spe_status);
2246
}
2247

    
2248
static always_inline int32_t _do_efsctsfz (uint32_t val)
2249
{
2250
    union {
2251
        int32_t u;
2252
        float32 f;
2253
    } u;
2254
    float32 tmp;
2255

    
2256
    u.u = val;
2257
    /* NaN are not treated the same way IEEE 754 does */
2258
    if (unlikely(isnan(u.f)))
2259
        return 0;
2260
    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2261
    u.f = float32_mul(u.f, tmp, &env->spe_status);
2262

    
2263
    return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2264
}
2265

    
2266
static always_inline uint32_t _do_efsctufz (uint32_t val)
2267
{
2268
    union {
2269
        int32_t u;
2270
        float32 f;
2271
    } u;
2272
    float32 tmp;
2273

    
2274
    u.u = val;
2275
    /* NaN are not treated the same way IEEE 754 does */
2276
    if (unlikely(isnan(u.f)))
2277
        return 0;
2278
    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2279
    u.f = float32_mul(u.f, tmp, &env->spe_status);
2280

    
2281
    return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2282
}
2283

    
2284
void do_efscfsf (void)
2285
{
2286
    T0_64 = _do_efscfsf(T0_64);
2287
}
2288

    
2289
void do_efscfuf (void)
2290
{
2291
    T0_64 = _do_efscfuf(T0_64);
2292
}
2293

    
2294
void do_efsctsf (void)
2295
{
2296
    T0_64 = _do_efsctsf(T0_64);
2297
}
2298

    
2299
void do_efsctuf (void)
2300
{
2301
    T0_64 = _do_efsctuf(T0_64);
2302
}
2303

    
2304
void do_efsctsfz (void)
2305
{
2306
    T0_64 = _do_efsctsfz(T0_64);
2307
}
2308

    
2309
void do_efsctufz (void)
2310
{
2311
    T0_64 = _do_efsctufz(T0_64);
2312
}
2313

    
2314
/* Double precision floating point helpers */
2315
static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
2316
{
2317
    /* XXX: TODO: test special values (NaN, infinites, ...) */
2318
    return _do_efdtstlt(op1, op2);
2319
}
2320

    
2321
static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
2322
{
2323
    /* XXX: TODO: test special values (NaN, infinites, ...) */
2324
    return _do_efdtstgt(op1, op2);
2325
}
2326

    
2327
static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
2328
{
2329
    /* XXX: TODO: test special values (NaN, infinites, ...) */
2330
    return _do_efdtsteq(op1, op2);
2331
}
2332

    
2333
void do_efdcmplt (void)
2334
{
2335
    T0 = _do_efdcmplt(T0_64, T1_64);
2336
}
2337

    
2338
void do_efdcmpgt (void)
2339
{
2340
    T0 = _do_efdcmpgt(T0_64, T1_64);
2341
}
2342

    
2343
void do_efdcmpeq (void)
2344
{
2345
    T0 = _do_efdcmpeq(T0_64, T1_64);
2346
}
2347

    
2348
/* Double precision floating-point conversion to/from integer */
2349
static always_inline uint64_t _do_efdcfsi (int64_t val)
2350
{
2351
    union {
2352
        uint64_t u;
2353
        float64 f;
2354
    } u;
2355

    
2356
    u.f = int64_to_float64(val, &env->spe_status);
2357

    
2358
    return u.u;
2359
}
2360

    
2361
static always_inline uint64_t _do_efdcfui (uint64_t val)
2362
{
2363
    union {
2364
        uint64_t u;
2365
        float64 f;
2366
    } u;
2367

    
2368
    u.f = uint64_to_float64(val, &env->spe_status);
2369

    
2370
    return u.u;
2371
}
2372

    
2373
static always_inline int64_t _do_efdctsi (uint64_t val)
2374
{
2375
    union {
2376
        int64_t u;
2377
        float64 f;
2378
    } u;
2379

    
2380
    u.u = val;
2381
    /* NaN are not treated the same way IEEE 754 does */
2382
    if (unlikely(isnan(u.f)))
2383
        return 0;
2384

    
2385
    return float64_to_int64(u.f, &env->spe_status);
2386
}
2387

    
2388
static always_inline uint64_t _do_efdctui (uint64_t val)
2389
{
2390
    union {
2391
        int64_t u;
2392
        float64 f;
2393
    } u;
2394

    
2395
    u.u = val;
2396
    /* NaN are not treated the same way IEEE 754 does */
2397
    if (unlikely(isnan(u.f)))
2398
        return 0;
2399

    
2400
    return float64_to_uint64(u.f, &env->spe_status);
2401
}
2402

    
2403
static always_inline int64_t _do_efdctsiz (uint64_t val)
2404
{
2405
    union {
2406
        int64_t u;
2407
        float64 f;
2408
    } u;
2409

    
2410
    u.u = val;
2411
    /* NaN are not treated the same way IEEE 754 does */
2412
    if (unlikely(isnan(u.f)))
2413
        return 0;
2414

    
2415
    return float64_to_int64_round_to_zero(u.f, &env->spe_status);
2416
}
2417

    
2418
static always_inline uint64_t _do_efdctuiz (uint64_t val)
2419
{
2420
    union {
2421
        int64_t u;
2422
        float64 f;
2423
    } u;
2424

    
2425
    u.u = val;
2426
    /* NaN are not treated the same way IEEE 754 does */
2427
    if (unlikely(isnan(u.f)))
2428
        return 0;
2429

    
2430
    return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
2431
}
2432

    
2433
void do_efdcfsi (void)
2434
{
2435
    T0_64 = _do_efdcfsi(T0_64);
2436
}
2437

    
2438
void do_efdcfui (void)
2439
{
2440
    T0_64 = _do_efdcfui(T0_64);
2441
}
2442

    
2443
void do_efdctsi (void)
2444
{
2445
    T0_64 = _do_efdctsi(T0_64);
2446
}
2447

    
2448
void do_efdctui (void)
2449
{
2450
    T0_64 = _do_efdctui(T0_64);
2451
}
2452

    
2453
void do_efdctsiz (void)
2454
{
2455
    T0_64 = _do_efdctsiz(T0_64);
2456
}
2457

    
2458
void do_efdctuiz (void)
2459
{
2460
    T0_64 = _do_efdctuiz(T0_64);
2461
}
2462

    
2463
/* Double precision floating-point conversion to/from fractional */
2464
static always_inline uint64_t _do_efdcfsf (int64_t val)
2465
{
2466
    union {
2467
        uint64_t u;
2468
        float64 f;
2469
    } u;
2470
    float64 tmp;
2471

    
2472
    u.f = int32_to_float64(val, &env->spe_status);
2473
    tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2474
    u.f = float64_div(u.f, tmp, &env->spe_status);
2475

    
2476
    return u.u;
2477
}
2478

    
2479
static always_inline uint64_t _do_efdcfuf (uint64_t val)
2480
{
2481
    union {
2482
        uint64_t u;
2483
        float64 f;
2484
    } u;
2485
    float64 tmp;
2486

    
2487
    u.f = uint32_to_float64(val, &env->spe_status);
2488
    tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2489
    u.f = float64_div(u.f, tmp, &env->spe_status);
2490

    
2491
    return u.u;
2492
}
2493

    
2494
static always_inline int64_t _do_efdctsf (uint64_t val)
2495
{
2496
    union {
2497
        int64_t u;
2498
        float64 f;
2499
    } u;
2500
    float64 tmp;
2501

    
2502
    u.u = val;
2503
    /* NaN are not treated the same way IEEE 754 does */
2504
    if (unlikely(isnan(u.f)))
2505
        return 0;
2506
    tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2507
    u.f = float64_mul(u.f, tmp, &env->spe_status);
2508

    
2509
    return float64_to_int32(u.f, &env->spe_status);
2510
}
2511

    
2512
static always_inline uint64_t _do_efdctuf (uint64_t val)
2513
{
2514
    union {
2515
        int64_t u;
2516
        float64 f;
2517
    } u;
2518
    float64 tmp;
2519

    
2520
    u.u = val;
2521
    /* NaN are not treated the same way IEEE 754 does */
2522
    if (unlikely(isnan(u.f)))
2523
        return 0;
2524
    tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2525
    u.f = float64_mul(u.f, tmp, &env->spe_status);
2526

    
2527
    return float64_to_uint32(u.f, &env->spe_status);
2528
}
2529

    
2530
static always_inline int64_t _do_efdctsfz (uint64_t val)
2531
{
2532
    union {
2533
        int64_t u;
2534
        float64 f;
2535
    } u;
2536
    float64 tmp;
2537

    
2538
    u.u = val;
2539
    /* NaN are not treated the same way IEEE 754 does */
2540
    if (unlikely(isnan(u.f)))
2541
        return 0;
2542
    tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2543
    u.f = float64_mul(u.f, tmp, &env->spe_status);
2544

    
2545
    return float64_to_int32_round_to_zero(u.f, &env->spe_status);
2546
}
2547

    
2548
static always_inline uint64_t _do_efdctufz (uint64_t val)
2549
{
2550
    union {
2551
        int64_t u;
2552
        float64 f;
2553
    } u;
2554
    float64 tmp;
2555

    
2556
    u.u = val;
2557
    /* NaN are not treated the same way IEEE 754 does */
2558
    if (unlikely(isnan(u.f)))
2559
        return 0;
2560
    tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2561
    u.f = float64_mul(u.f, tmp, &env->spe_status);
2562

    
2563
    return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
2564
}
2565

    
2566
void do_efdcfsf (void)
2567
{
2568
    T0_64 = _do_efdcfsf(T0_64);
2569
}
2570

    
2571
void do_efdcfuf (void)
2572
{
2573
    T0_64 = _do_efdcfuf(T0_64);
2574
}
2575

    
2576
void do_efdctsf (void)
2577
{
2578
    T0_64 = _do_efdctsf(T0_64);
2579
}
2580

    
2581
void do_efdctuf (void)
2582
{
2583
    T0_64 = _do_efdctuf(T0_64);
2584
}
2585

    
2586
void do_efdctsfz (void)
2587
{
2588
    T0_64 = _do_efdctsfz(T0_64);
2589
}
2590

    
2591
void do_efdctufz (void)
2592
{
2593
    T0_64 = _do_efdctufz(T0_64);
2594
}
2595

    
2596
/* Floating point conversion between single and double precision */
2597
static always_inline uint32_t _do_efscfd (uint64_t val)
2598
{
2599
    union {
2600
        uint64_t u;
2601
        float64 f;
2602
    } u1;
2603
    union {
2604
        uint32_t u;
2605
        float32 f;
2606
    } u2;
2607

    
2608
    u1.u = val;
2609
    u2.f = float64_to_float32(u1.f, &env->spe_status);
2610

    
2611
    return u2.u;
2612
}
2613

    
2614
static always_inline uint64_t _do_efdcfs (uint32_t val)
2615
{
2616
    union {
2617
        uint64_t u;
2618
        float64 f;
2619
    } u2;
2620
    union {
2621
        uint32_t u;
2622
        float32 f;
2623
    } u1;
2624

    
2625
    u1.u = val;
2626
    u2.f = float32_to_float64(u1.f, &env->spe_status);
2627

    
2628
    return u2.u;
2629
}
2630

    
2631
void do_efscfd (void)
2632
{
2633
    T0_64 = _do_efscfd(T0_64);
2634
}
2635

    
2636
void do_efdcfs (void)
2637
{
2638
    T0_64 = _do_efdcfs(T0_64);
2639
}
2640

    
2641
/* Single precision fixed-point vector arithmetic */
2642
/* evfsabs */
2643
DO_SPE_OP1(fsabs);
2644
/* evfsnabs */
2645
DO_SPE_OP1(fsnabs);
2646
/* evfsneg */
2647
DO_SPE_OP1(fsneg);
2648
/* evfsadd */
2649
DO_SPE_OP2(fsadd);
2650
/* evfssub */
2651
DO_SPE_OP2(fssub);
2652
/* evfsmul */
2653
DO_SPE_OP2(fsmul);
2654
/* evfsdiv */
2655
DO_SPE_OP2(fsdiv);
2656

    
2657
/* Single-precision floating-point comparisons */
2658
static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2659
{
2660
    /* XXX: TODO: test special values (NaN, infinites, ...) */
2661
    return _do_efststlt(op1, op2);
2662
}
2663

    
2664
static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2665
{
2666
    /* XXX: TODO: test special values (NaN, infinites, ...) */
2667
    return _do_efststgt(op1, op2);
2668
}
2669

    
2670
static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2671
{
2672
    /* XXX: TODO: test special values (NaN, infinites, ...) */
2673
    return _do_efststeq(op1, op2);
2674
}
2675

    
2676
void do_efscmplt (void)
2677
{
2678
    T0 = _do_efscmplt(T0_64, T1_64);
2679
}
2680

    
2681
void do_efscmpgt (void)
2682
{
2683
    T0 = _do_efscmpgt(T0_64, T1_64);
2684
}
2685

    
2686
void do_efscmpeq (void)
2687
{
2688
    T0 = _do_efscmpeq(T0_64, T1_64);
2689
}
2690

    
2691
/* Single-precision floating-point vector comparisons */
2692
/* evfscmplt */
2693
DO_SPE_CMP(fscmplt);
2694
/* evfscmpgt */
2695
DO_SPE_CMP(fscmpgt);
2696
/* evfscmpeq */
2697
DO_SPE_CMP(fscmpeq);
2698
/* evfststlt */
2699
DO_SPE_CMP(fststlt);
2700
/* evfststgt */
2701
DO_SPE_CMP(fststgt);
2702
/* evfststeq */
2703
DO_SPE_CMP(fststeq);
2704

    
2705
/* Single-precision floating-point vector conversions */
2706
/* evfscfsi */
2707
DO_SPE_OP1(fscfsi);
2708
/* evfscfui */
2709
DO_SPE_OP1(fscfui);
2710
/* evfscfuf */
2711
DO_SPE_OP1(fscfuf);
2712
/* evfscfsf */
2713
DO_SPE_OP1(fscfsf);
2714
/* evfsctsi */
2715
DO_SPE_OP1(fsctsi);
2716
/* evfsctui */
2717
DO_SPE_OP1(fsctui);
2718
/* evfsctsiz */
2719
DO_SPE_OP1(fsctsiz);
2720
/* evfsctuiz */
2721
DO_SPE_OP1(fsctuiz);
2722
/* evfsctsf */
2723
DO_SPE_OP1(fsctsf);
2724
/* evfsctuf */
2725
DO_SPE_OP1(fsctuf);
2726
#endif /* defined(TARGET_PPCEMB) */
2727

    
2728
/*****************************************************************************/
2729
/* Softmmu support */
2730
#if !defined (CONFIG_USER_ONLY)
2731

    
2732
#define MMUSUFFIX _mmu
2733
#define GETPC() (__builtin_return_address(0))
2734

    
2735
#define SHIFT 0
2736
#include "softmmu_template.h"
2737

    
2738
#define SHIFT 1
2739
#include "softmmu_template.h"
2740

    
2741
#define SHIFT 2
2742
#include "softmmu_template.h"
2743

    
2744
#define SHIFT 3
2745
#include "softmmu_template.h"
2746

    
2747
/* try to fill the TLB and return an exception if error. If retaddr is
2748
   NULL, it means that the function was called in C code (i.e. not
2749
   from generated code or from helper.c) */
2750
/* XXX: fix it to restore all registers */
2751
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2752
{
2753
    TranslationBlock *tb;
2754
    CPUState *saved_env;
2755
    target_phys_addr_t pc;
2756
    int ret;
2757

    
2758
    /* XXX: hack to restore env in all cases, even if not called from
2759
       generated code */
2760
    saved_env = env;
2761
    env = cpu_single_env;
2762
    ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2763
    if (unlikely(ret != 0)) {
2764
        if (likely(retaddr)) {
2765
            /* now we have a real cpu fault */
2766
            pc = (target_phys_addr_t)(unsigned long)retaddr;
2767
            tb = tb_find_pc(pc);
2768
            if (likely(tb)) {
2769
                /* the PC is inside the translated code. It means that we have
2770
                   a virtual CPU fault */
2771
                cpu_restore_state(tb, env, pc, NULL);
2772
            }
2773
        }
2774
        do_raise_exception_err(env->exception_index, env->error_code);
2775
    }
2776
    env = saved_env;
2777
}
2778

    
2779
/* Software driven TLBs management */
2780
/* PowerPC 602/603 software TLB load instructions helpers */
2781
void do_load_6xx_tlb (int is_code)
2782
{
2783
    target_ulong RPN, CMP, EPN;
2784
    int way;
2785

    
2786
    RPN = env->spr[SPR_RPA];
2787
    if (is_code) {
2788
        CMP = env->spr[SPR_ICMP];
2789
        EPN = env->spr[SPR_IMISS];
2790
    } else {
2791
        CMP = env->spr[SPR_DCMP];
2792
        EPN = env->spr[SPR_DMISS];
2793
    }
2794
    way = (env->spr[SPR_SRR1] >> 17) & 1;
2795
#if defined (DEBUG_SOFTWARE_TLB)
2796
    if (loglevel != 0) {
2797
        fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2798
                __func__, (unsigned long)T0, (unsigned long)EPN,
2799
                (unsigned long)CMP, (unsigned long)RPN, way);
2800
    }
2801
#endif
2802
    /* Store this TLB */
2803
    ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2804
                     way, is_code, CMP, RPN);
2805
}
2806

    
2807
void do_load_74xx_tlb (int is_code)
2808
{
2809
    target_ulong RPN, CMP, EPN;
2810
    int way;
2811

    
2812
    RPN = env->spr[SPR_PTELO];
2813
    CMP = env->spr[SPR_PTEHI];
2814
    EPN = env->spr[SPR_TLBMISS] & ~0x3;
2815
    way = env->spr[SPR_TLBMISS] & 0x3;
2816
#if defined (DEBUG_SOFTWARE_TLB)
2817
    if (loglevel != 0) {
2818
        fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2819
                __func__, (unsigned long)T0, (unsigned long)EPN,
2820
                (unsigned long)CMP, (unsigned long)RPN, way);
2821
    }
2822
#endif
2823
    /* Store this TLB */
2824
    ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2825
                     way, is_code, CMP, RPN);
2826
}
2827

    
2828
static target_ulong booke_tlb_to_page_size (int size)
2829
{
2830
    return 1024 << (2 * size);
2831
}
2832

    
2833
static int booke_page_size_to_tlb (target_ulong page_size)
2834
{
2835
    int size;
2836

    
2837
    switch (page_size) {
2838
    case 0x00000400UL:
2839
        size = 0x0;
2840
        break;
2841
    case 0x00001000UL:
2842
        size = 0x1;
2843
        break;
2844
    case 0x00004000UL:
2845
        size = 0x2;
2846
        break;
2847
    case 0x00010000UL:
2848
        size = 0x3;
2849
        break;
2850
    case 0x00040000UL:
2851
        size = 0x4;
2852
        break;
2853
    case 0x00100000UL:
2854
        size = 0x5;
2855
        break;
2856
    case 0x00400000UL:
2857
        size = 0x6;
2858
        break;
2859
    case 0x01000000UL:
2860
        size = 0x7;
2861
        break;
2862
    case 0x04000000UL:
2863
        size = 0x8;
2864
        break;
2865
    case 0x10000000UL:
2866
        size = 0x9;
2867
        break;
2868
    case 0x40000000UL:
2869
        size = 0xA;
2870
        break;
2871
#if defined (TARGET_PPC64)
2872
    case 0x000100000000ULL:
2873
        size = 0xB;
2874
        break;
2875
    case 0x000400000000ULL:
2876
        size = 0xC;
2877
        break;
2878
    case 0x001000000000ULL:
2879
        size = 0xD;
2880
        break;
2881
    case 0x004000000000ULL:
2882
        size = 0xE;
2883
        break;
2884
    case 0x010000000000ULL:
2885
        size = 0xF;
2886
        break;
2887
#endif
2888
    default:
2889
        size = -1;
2890
        break;
2891
    }
2892

    
2893
    return size;
2894
}
2895

    
2896
/* Helpers for 4xx TLB management */
2897
void do_4xx_tlbre_lo (void)
2898
{
2899
    ppcemb_tlb_t *tlb;
2900
    int size;
2901

    
2902
    T0 &= 0x3F;
2903
    tlb = &env->tlb[T0].tlbe;
2904
    T0 = tlb->EPN;
2905
    if (tlb->prot & PAGE_VALID)
2906
        T0 |= 0x400;
2907
    size = booke_page_size_to_tlb(tlb->size);
2908
    if (size < 0 || size > 0x7)
2909
        size = 1;
2910
    T0 |= size << 7;
2911
    env->spr[SPR_40x_PID] = tlb->PID;
2912
}
2913

    
2914
void do_4xx_tlbre_hi (void)
2915
{
2916
    ppcemb_tlb_t *tlb;
2917

    
2918
    T0 &= 0x3F;
2919
    tlb = &env->tlb[T0].tlbe;
2920
    T0 = tlb->RPN;
2921
    if (tlb->prot & PAGE_EXEC)
2922
        T0 |= 0x200;
2923
    if (tlb->prot & PAGE_WRITE)
2924
        T0 |= 0x100;
2925
}
2926

    
2927
void do_4xx_tlbwe_hi (void)
2928
{
2929
    ppcemb_tlb_t *tlb;
2930
    target_ulong page, end;
2931

    
2932
#if defined (DEBUG_SOFTWARE_TLB)
2933
    if (loglevel != 0) {
2934
        fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
2935
    }
2936
#endif
2937
    T0 &= 0x3F;
2938
    tlb = &env->tlb[T0].tlbe;
2939
    /* Invalidate previous TLB (if it's valid) */
2940
    if (tlb->prot & PAGE_VALID) {
2941
        end = tlb->EPN + tlb->size;
2942
#if defined (DEBUG_SOFTWARE_TLB)
2943
        if (loglevel != 0) {
2944
            fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2945
                    " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2946
        }
2947
#endif
2948
        for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2949
            tlb_flush_page(env, page);
2950
    }
2951
    tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2952
    /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2953
     * If this ever occurs, one should use the ppcemb target instead
2954
     * of the ppc or ppc64 one
2955
     */
2956
    if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2957
        cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2958
                  "are not supported (%d)\n",
2959
                  tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2960
    }
2961
    tlb->EPN = T1 & ~(tlb->size - 1);
2962
    if (T1 & 0x40)
2963
        tlb->prot |= PAGE_VALID;
2964
    else
2965
        tlb->prot &= ~PAGE_VALID;
2966
    if (T1 & 0x20) {
2967
        /* XXX: TO BE FIXED */
2968
        cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2969
    }
2970
    tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2971
    tlb->attr = T1 & 0xFF;
2972
#if defined (DEBUG_SOFTWARE_TLB)
2973
    if (loglevel != 0) {
2974
        fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2975
                " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2976
                (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2977
                tlb->prot & PAGE_READ ? 'r' : '-',
2978
                tlb->prot & PAGE_WRITE ? 'w' : '-',
2979
                tlb->prot & PAGE_EXEC ? 'x' : '-',
2980
                tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2981
    }
2982
#endif
2983
    /* Invalidate new TLB (if valid) */
2984
    if (tlb->prot & PAGE_VALID) {
2985
        end = tlb->EPN + tlb->size;
2986
#if defined (DEBUG_SOFTWARE_TLB)
2987
        if (loglevel != 0) {
2988
            fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2989
                    " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2990
        }
2991
#endif
2992
        for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2993
            tlb_flush_page(env, page);
2994
    }
2995
}
2996

    
2997
void do_4xx_tlbwe_lo (void)
2998
{
2999
    ppcemb_tlb_t *tlb;
3000

    
3001
#if defined (DEBUG_SOFTWARE_TLB)
3002
    if (loglevel != 0) {
3003
        fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
3004
    }
3005
#endif
3006
    T0 &= 0x3F;
3007
    tlb = &env->tlb[T0].tlbe;
3008
    tlb->RPN = T1 & 0xFFFFFC00;
3009
    tlb->prot = PAGE_READ;
3010
    if (T1 & 0x200)
3011
        tlb->prot |= PAGE_EXEC;
3012
    if (T1 & 0x100)
3013
        tlb->prot |= PAGE_WRITE;
3014
#if defined (DEBUG_SOFTWARE_TLB)
3015
    if (loglevel != 0) {
3016
        fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3017
                " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3018
                (int)T0, tlb->RPN, tlb->EPN, tlb->size,
3019
                tlb->prot & PAGE_READ ? 'r' : '-',
3020
                tlb->prot & PAGE_WRITE ? 'w' : '-',
3021
                tlb->prot & PAGE_EXEC ? 'x' : '-',
3022
                tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3023
    }
3024
#endif
3025
}
3026

    
3027
/* PowerPC 440 TLB management */
3028
void do_440_tlbwe (int word)
3029
{
3030
    ppcemb_tlb_t *tlb;
3031
    target_ulong EPN, RPN, size;
3032
    int do_flush_tlbs;
3033

    
3034
#if defined (DEBUG_SOFTWARE_TLB)
3035
    if (loglevel != 0) {
3036
        fprintf(logfile, "%s word %d T0 " REGX " T1 " REGX "\n",
3037
                __func__, word, T0, T1);
3038
    }
3039
#endif
3040
    do_flush_tlbs = 0;
3041
    T0 &= 0x3F;
3042
    tlb = &env->tlb[T0].tlbe;
3043
    switch (word) {
3044
    default:
3045
        /* Just here to please gcc */
3046
    case 0:
3047
        EPN = T1 & 0xFFFFFC00;
3048
        if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3049
            do_flush_tlbs = 1;
3050
        tlb->EPN = EPN;
3051
        size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
3052
        if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3053
            do_flush_tlbs = 1;
3054
        tlb->size = size;
3055
        tlb->attr &= ~0x1;
3056
        tlb->attr |= (T1 >> 8) & 1;
3057
        if (T1 & 0x200) {
3058
            tlb->prot |= PAGE_VALID;
3059
        } else {
3060
            if (tlb->prot & PAGE_VALID) {
3061
                tlb->prot &= ~PAGE_VALID;
3062
                do_flush_tlbs = 1;
3063
            }
3064
        }
3065
        tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3066
        if (do_flush_tlbs)
3067
            tlb_flush(env, 1);
3068
        break;
3069
    case 1:
3070
        RPN = T1 & 0xFFFFFC0F;
3071
        if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3072
            tlb_flush(env, 1);
3073
        tlb->RPN = RPN;
3074
        break;
3075
    case 2:
3076
        tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
3077
        tlb->prot = tlb->prot & PAGE_VALID;
3078
        if (T1 & 0x1)
3079
            tlb->prot |= PAGE_READ << 4;
3080
        if (T1 & 0x2)
3081
            tlb->prot |= PAGE_WRITE << 4;
3082
        if (T1 & 0x4)
3083
            tlb->prot |= PAGE_EXEC << 4;
3084
        if (T1 & 0x8)
3085
            tlb->prot |= PAGE_READ;
3086
        if (T1 & 0x10)
3087
            tlb->prot |= PAGE_WRITE;
3088
        if (T1 & 0x20)
3089
            tlb->prot |= PAGE_EXEC;
3090
        break;
3091
    }
3092
}
3093

    
3094
void do_440_tlbre (int word)
3095
{
3096
    ppcemb_tlb_t *tlb;
3097
    int size;
3098

    
3099
    T0 &= 0x3F;
3100
    tlb = &env->tlb[T0].tlbe;
3101
    switch (word) {
3102
    default:
3103
        /* Just here to please gcc */
3104
    case 0:
3105
        T0 = tlb->EPN;
3106
        size = booke_page_size_to_tlb(tlb->size);
3107
        if (size < 0 || size > 0xF)
3108
            size = 1;
3109
        T0 |= size << 4;
3110
        if (tlb->attr & 0x1)
3111
            T0 |= 0x100;
3112
        if (tlb->prot & PAGE_VALID)
3113
            T0 |= 0x200;
3114
        env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3115
        env->spr[SPR_440_MMUCR] |= tlb->PID;
3116
        break;
3117
    case 1:
3118
        T0 = tlb->RPN;
3119
        break;
3120
    case 2:
3121
        T0 = tlb->attr & ~0x1;
3122
        if (tlb->prot & (PAGE_READ << 4))
3123
            T0 |= 0x1;
3124
        if (tlb->prot & (PAGE_WRITE << 4))
3125
            T0 |= 0x2;
3126
        if (tlb->prot & (PAGE_EXEC << 4))
3127
            T0 |= 0x4;
3128
        if (tlb->prot & PAGE_READ)
3129
            T0 |= 0x8;
3130
        if (tlb->prot & PAGE_WRITE)
3131
            T0 |= 0x10;
3132
        if (tlb->prot & PAGE_EXEC)
3133
            T0 |= 0x20;
3134
        break;
3135
    }
3136
}
3137
#endif /* !CONFIG_USER_ONLY */