Revision 4fcc562b
b/cpu-all.h | ||
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820 | 820 |
void cpu_single_step(CPUState *env, int enabled); |
821 | 821 |
void cpu_reset(CPUState *s); |
822 | 822 |
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823 |
/* Return the physical page corresponding to a virtual one. Use it |
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824 |
only for debugging because no protection checks are done. Return -1 |
|
825 |
if no page found. */ |
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826 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
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827 |
|
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828 | 823 |
#define CPU_LOG_TB_OUT_ASM (1 << 0) |
829 | 824 |
#define CPU_LOG_TB_IN_ASM (1 << 1) |
830 | 825 |
#define CPU_LOG_TB_OP (1 << 2) |
... | ... | |
851 | 846 |
|
852 | 847 |
#if !defined(CONFIG_USER_ONLY) |
853 | 848 |
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849 |
/* Return the physical page corresponding to a virtual one. Use it |
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850 |
only for debugging because no protection checks are done. Return -1 |
|
851 |
if no page found. */ |
|
852 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
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853 |
|
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854 | 854 |
/* memory API */ |
855 | 855 |
|
856 | 856 |
extern int phys_ram_fd; |
b/target-alpha/helper.c | ||
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173 | 173 |
return 1; |
174 | 174 |
} |
175 | 175 |
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176 |
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
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177 |
{ |
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178 |
return addr; |
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179 |
} |
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180 |
|
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181 | 176 |
void do_interrupt (CPUState *env) |
182 | 177 |
{ |
183 | 178 |
env->exception_index = -1; |
b/target-arm/helper.c | ||
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483 | 483 |
return 1; |
484 | 484 |
} |
485 | 485 |
|
486 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
|
487 |
{ |
|
488 |
return addr; |
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489 |
} |
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490 |
|
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491 | 486 |
/* These should probably raise undefined insn exceptions. */ |
492 | 487 |
void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val) |
493 | 488 |
{ |
b/target-cris/helper.c | ||
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56 | 56 |
return 1; |
57 | 57 |
} |
58 | 58 |
|
59 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
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60 |
{ |
|
61 |
return addr; |
|
62 |
} |
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63 |
|
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64 | 59 |
#else /* !CONFIG_USER_ONLY */ |
65 | 60 |
|
66 | 61 |
|
b/target-i386/helper.c | ||
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1386 | 1386 |
return 1; |
1387 | 1387 |
} |
1388 | 1388 |
|
1389 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
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1390 |
{ |
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1391 |
return addr; |
|
1392 |
} |
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1393 |
|
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1394 | 1389 |
#else |
1395 | 1390 |
|
1396 | 1391 |
/* XXX: This value should match the one returned by CPUID |
b/target-m68k/helper.c | ||
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342 | 342 |
env->current_sp = new_sp; |
343 | 343 |
} |
344 | 344 |
|
345 |
/* MMU */ |
|
346 |
|
|
347 |
/* TODO: This will need fixing once the MMU is implemented. */ |
|
348 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
|
349 |
{ |
|
350 |
return addr; |
|
351 |
} |
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352 |
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353 | 345 |
#if defined(CONFIG_USER_ONLY) |
354 | 346 |
|
355 | 347 |
int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
... | ... | |
362 | 354 |
|
363 | 355 |
#else |
364 | 356 |
|
357 |
/* MMU */ |
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358 |
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|
359 |
/* TODO: This will need fixing once the MMU is implemented. */ |
|
360 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
|
361 |
{ |
|
362 |
return addr; |
|
363 |
} |
|
364 |
|
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365 | 365 |
int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
366 | 366 |
int mmu_idx, int is_softmmu) |
367 | 367 |
{ |
b/target-microblaze/helper.c | ||
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45 | 45 |
return 1; |
46 | 46 |
} |
47 | 47 |
|
48 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
|
49 |
{ |
|
50 |
return addr; |
|
51 |
} |
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52 |
|
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53 | 48 |
#else /* !CONFIG_USER_ONLY */ |
54 | 49 |
|
55 | 50 |
int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
b/target-mips/helper.c | ||
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253 | 253 |
env->error_code = error_code; |
254 | 254 |
} |
255 | 255 |
|
256 |
#if !defined(CONFIG_USER_ONLY) |
|
256 | 257 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
257 | 258 |
{ |
258 |
#if defined(CONFIG_USER_ONLY) |
|
259 |
return addr; |
|
260 |
#else |
|
261 | 259 |
target_phys_addr_t phys_addr; |
262 | 260 |
int prot; |
263 | 261 |
|
264 | 262 |
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
265 | 263 |
return -1; |
266 | 264 |
return phys_addr; |
267 |
#endif |
|
268 | 265 |
} |
266 |
#endif |
|
269 | 267 |
|
270 | 268 |
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
271 | 269 |
int mmu_idx, int is_softmmu) |
b/target-ppc/helper.c | ||
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97 | 97 |
return 1; |
98 | 98 |
} |
99 | 99 |
|
100 |
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
|
101 |
{ |
|
102 |
return addr; |
|
103 |
} |
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104 |
|
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105 | 100 |
#else |
106 | 101 |
/* Common routines used by software and hardware TLBs emulation */ |
107 | 102 |
static inline int pte_is_valid(target_ulong pte0) |
b/target-s390x/helper.c | ||
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46 | 46 |
return env; |
47 | 47 |
} |
48 | 48 |
|
49 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
|
50 |
{ |
|
51 |
return addr; |
|
52 |
} |
|
53 |
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54 | 49 |
void cpu_reset(CPUS390XState *env) |
55 | 50 |
{ |
56 | 51 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
b/target-sh4/helper.c | ||
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53 | 53 |
return 1; |
54 | 54 |
} |
55 | 55 |
|
56 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
|
57 |
{ |
|
58 |
return addr; |
|
59 |
} |
|
60 |
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61 | 56 |
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) |
62 | 57 |
{ |
63 | 58 |
/* For user mode, only U0 area is cachable. */ |
b/target-sparc/helper.c | ||
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652 | 652 |
#endif /* !CONFIG_USER_ONLY */ |
653 | 653 |
|
654 | 654 |
|
655 |
#if defined(CONFIG_USER_ONLY) |
|
656 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
|
657 |
{ |
|
658 |
return addr; |
|
659 |
} |
|
660 |
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|
661 |
#else |
|
655 |
#if !defined(CONFIG_USER_ONLY) |
|
662 | 656 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
663 | 657 |
{ |
664 | 658 |
target_phys_addr_t phys_addr; |
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