Revision 502a5395 hw/versatilepb.c
| b/hw/versatilepb.c | ||
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#include "vl.h" |
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#include "arm_pic.h" |
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#define LOCK_VALUE 0xa05f |
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/* Primary interrupt controller. */ |
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typedef struct vpb_sic_state |
| ... | ... | |
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return s; |
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} |
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/* System controller. */ |
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typedef struct {
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uint32_t base; |
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uint32_t leds; |
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uint16_t lockval; |
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uint32_t cfgdata1; |
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uint32_t cfgdata2; |
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uint32_t flags; |
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uint32_t nvflags; |
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uint32_t resetlevel; |
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} vpb_sys_state; |
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static uint32_t vpb_sys_read(void *opaque, target_phys_addr_t offset) |
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{
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vpb_sys_state *s = (vpb_sys_state *)opaque; |
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offset -= s->base; |
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switch (offset) {
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case 0x00: /* ID */ |
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return 0x41007004; |
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case 0x04: /* SW */ |
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/* General purpose hardware switches. |
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We don't have a useful way of exposing these to the user. */ |
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return 0; |
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case 0x08: /* LED */ |
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return s->leds; |
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case 0x20: /* LOCK */ |
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return s->lockval; |
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case 0x0c: /* OSC0 */ |
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case 0x10: /* OSC1 */ |
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case 0x14: /* OSC2 */ |
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case 0x18: /* OSC3 */ |
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case 0x1c: /* OSC4 */ |
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case 0x24: /* 100HZ */ |
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/* ??? Implement these. */ |
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return 0; |
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case 0x28: /* CFGDATA1 */ |
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return s->cfgdata1; |
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case 0x2c: /* CFGDATA2 */ |
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return s->cfgdata2; |
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case 0x30: /* FLAGS */ |
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return s->flags; |
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case 0x38: /* NVFLAGS */ |
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return s->nvflags; |
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case 0x40: /* RESETCTL */ |
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return s->resetlevel; |
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case 0x44: /* PCICTL */ |
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return 1; |
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case 0x48: /* MCI */ |
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return 0; |
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case 0x4c: /* FLASH */ |
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return 0; |
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case 0x50: /* CLCD */ |
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return 0x1000; |
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case 0x54: /* CLCDSER */ |
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return 0; |
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case 0x58: /* BOOTCS */ |
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return 0; |
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case 0x5c: /* 24MHz */ |
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/* ??? not implemented. */ |
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return 0; |
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case 0x60: /* MISC */ |
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return 0; |
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case 0x64: /* DMAPSR0 */ |
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case 0x68: /* DMAPSR1 */ |
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case 0x6c: /* DMAPSR2 */ |
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case 0x8c: /* OSCRESET0 */ |
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case 0x90: /* OSCRESET1 */ |
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case 0x94: /* OSCRESET2 */ |
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case 0x98: /* OSCRESET3 */ |
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case 0x9c: /* OSCRESET4 */ |
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case 0xc0: /* SYS_TEST_OSC0 */ |
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case 0xc4: /* SYS_TEST_OSC1 */ |
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case 0xc8: /* SYS_TEST_OSC2 */ |
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case 0xcc: /* SYS_TEST_OSC3 */ |
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case 0xd0: /* SYS_TEST_OSC4 */ |
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return 0; |
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default: |
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printf ("vpb_sys_read: Bad register offset 0x%x\n", offset);
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return 0; |
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} |
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} |
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static void vpb_sys_write(void *opaque, target_phys_addr_t offset, |
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uint32_t val) |
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{
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vpb_sys_state *s = (vpb_sys_state *)opaque; |
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offset -= s->base; |
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switch (offset) {
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case 0x08: /* LED */ |
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s->leds = val; |
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case 0x0c: /* OSC0 */ |
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case 0x10: /* OSC1 */ |
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case 0x14: /* OSC2 */ |
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case 0x18: /* OSC3 */ |
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case 0x1c: /* OSC4 */ |
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/* ??? */ |
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break; |
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case 0x20: /* LOCK */ |
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if (val == LOCK_VALUE) |
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s->lockval = val; |
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else |
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s->lockval = val & 0x7fff; |
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break; |
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case 0x28: /* CFGDATA1 */ |
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/* ??? Need to implement this. */ |
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s->cfgdata1 = val; |
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break; |
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case 0x2c: /* CFGDATA2 */ |
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/* ??? Need to implement this. */ |
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s->cfgdata2 = val; |
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break; |
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case 0x30: /* FLAGSSET */ |
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s->flags |= val; |
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break; |
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case 0x34: /* FLAGSCLR */ |
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s->flags &= ~val; |
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break; |
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case 0x38: /* NVFLAGSSET */ |
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s->nvflags |= val; |
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break; |
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case 0x3c: /* NVFLAGSCLR */ |
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s->nvflags &= ~val; |
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break; |
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case 0x40: /* RESETCTL */ |
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if (s->lockval == LOCK_VALUE) {
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s->resetlevel = val; |
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if (val & 0x100) |
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cpu_abort(cpu_single_env, "Board reset\n"); |
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} |
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break; |
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case 0x44: /* PCICTL */ |
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/* nothing to do. */ |
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break; |
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case 0x4c: /* FLASH */ |
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case 0x50: /* CLCD */ |
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case 0x54: /* CLCDSER */ |
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case 0x64: /* DMAPSR0 */ |
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case 0x68: /* DMAPSR1 */ |
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case 0x6c: /* DMAPSR2 */ |
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case 0x8c: /* OSCRESET0 */ |
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case 0x90: /* OSCRESET1 */ |
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case 0x94: /* OSCRESET2 */ |
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case 0x98: /* OSCRESET3 */ |
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case 0x9c: /* OSCRESET4 */ |
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break; |
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default: |
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printf ("vpb_sys_write: Bad register offset 0x%x\n", offset);
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return; |
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} |
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} |
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static CPUReadMemoryFunc *vpb_sys_readfn[] = {
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vpb_sys_read, |
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vpb_sys_read, |
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vpb_sys_read |
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}; |
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static CPUWriteMemoryFunc *vpb_sys_writefn[] = {
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vpb_sys_write, |
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vpb_sys_write, |
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vpb_sys_write |
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}; |
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static vpb_sys_state *vpb_sys_init(uint32_t base) |
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{
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vpb_sys_state *s; |
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int iomemtype; |
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s = (vpb_sys_state *)qemu_mallocz(sizeof(vpb_sys_state)); |
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if (!s) |
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return NULL; |
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s->base = base; |
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iomemtype = cpu_register_io_memory(0, vpb_sys_readfn, |
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vpb_sys_writefn, s); |
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cpu_register_physical_memory(base, 0x00000fff, iomemtype); |
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/* ??? Save/restore. */ |
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return s; |
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} |
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/* Board init. */ |
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/* The AB and PB boards both use the same core, just with different |
| ... | ... | |
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CPUState *env; |
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void *pic; |
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void *sic; |
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PCIBus *pci_bus; |
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NICInfo *nd; |
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int n; |
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int done_smc = 0; |
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env = cpu_init(); |
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cpu_arm_set_model(env, ARM_CPUID_ARM926); |
| ... | ... | |
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/* SDRAM at address zero. */ |
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
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vpb_sys_init(0x10000000); |
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pic = arm_pic_init_cpu(env); |
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pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ); |
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sic = vpb_sic_init(0x10003000, pic, 31); |
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pl050_init(0x10006000, sic, 3, 0); |
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pl050_init(0x10007000, sic, 4, 1); |
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/* TODO: Init PCI NICs. */ |
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL |
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|| strcmp(nd_table[0].model, "smc91c111") == 0) {
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smc91c111_init(&nd_table[0], 0x10010000, sic, 25); |
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pci_bus = pci_vpb_init(sic); |
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/* The Versatile PCI bridge does not provide access to PCI IO space, |
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so many of the qemu PCI devices are not useable. */ |
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for(n = 0; n < nb_nics; n++) {
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nd = &nd_table[n]; |
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if (!nd->model) |
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nd->model = done_smc ? "rtl8139" : "smc91c111"; |
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if (strcmp(nd->model, "smc91c111") == 0) {
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smc91c111_init(nd, 0x10010000, sic, 25); |
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
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exit (1); |
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pci_nic_init(pci_bus, nd); |
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} |
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} |
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