Revision 50443c98
b/cpu-exec.c | ||
---|---|---|
265 | 265 |
} |
266 | 266 |
} |
267 | 267 |
#elif defined(TARGET_PPC) |
268 |
if (env1->msr[MSR_POW]) {
|
|
268 |
if (env1->halted) {
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|
269 | 269 |
if (env1->msr[MSR_EE] && |
270 | 270 |
(env1->interrupt_request & |
271 | 271 |
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) { |
272 |
env1->msr[MSR_POW] = 0;
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|
272 |
env1->halted = 0;
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|
273 | 273 |
} else { |
274 | 274 |
return EXCP_HALTED; |
275 | 275 |
} |
b/monitor.c | ||
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257 | 257 |
term_printf(" (halted)"); |
258 | 258 |
#elif defined(TARGET_PPC) |
259 | 259 |
term_printf(" nip=0x" TARGET_FMT_lx, env->nip); |
260 |
if (msr_pow)
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|
260 |
if (env->halted)
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|
261 | 261 |
term_printf(" (halted)"); |
262 | 262 |
#endif |
263 | 263 |
term_printf("\n"); |
b/target-ppc/cpu.h | ||
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495 | 495 |
|
496 | 496 |
CPU_COMMON |
497 | 497 |
|
498 |
int halted; /* TRUE if the CPU is in suspend state */ |
|
499 |
|
|
498 | 500 |
int access_type; /* when a memory exception occurs, the access |
499 | 501 |
type is stored here */ |
500 | 502 |
|
b/target-ppc/helper.c | ||
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807 | 807 |
|
808 | 808 |
void do_store_msr (CPUPPCState *env, target_ulong value) |
809 | 809 |
{ |
810 |
int enter_pm; |
|
811 |
|
|
810 | 812 |
value &= env->msr_mask; |
811 | 813 |
if (((value >> MSR_IR) & 1) != msr_ir || |
812 | 814 |
((value >> MSR_DR) & 1) != msr_dr) { |
... | ... | |
846 | 848 |
msr_ri = (value >> MSR_RI) & 1; |
847 | 849 |
msr_le = (value >> MSR_LE) & 1; |
848 | 850 |
do_compute_hflags(env); |
849 |
if (msr_pow) { |
|
851 |
|
|
852 |
enter_pm = 0; |
|
853 |
switch (PPC_EXCP(env)) { |
|
854 |
case PPC_FLAGS_EXCP_7x0: |
|
855 |
if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0) |
|
856 |
enter_pm = 1; |
|
857 |
break; |
|
858 |
default: |
|
859 |
break; |
|
860 |
} |
|
861 |
if (enter_pm) { |
|
850 | 862 |
/* power save: exit cpu loop */ |
863 |
env->halted = 1; |
|
851 | 864 |
env->exception_index = EXCP_HLT; |
852 | 865 |
cpu_loop_exit(); |
853 | 866 |
} |
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