Revision 508b43ea

b/target-alpha/helper.h
100 100
DEF_HELPER_1(ieee_input_s, i64, i64)
101 101

  
102 102
#if !defined (CONFIG_USER_ONLY)
103
DEF_HELPER_0(hw_rei, void)
104 103
DEF_HELPER_1(hw_ret, void, i64)
105 104
DEF_HELPER_2(mfpr, i64, int, i64)
106 105
DEF_HELPER_2(mtpr, void, int, i64)
b/target-alpha/op_helper.c
1156 1156

  
1157 1157
/* PALcode support special instructions */
1158 1158
#if !defined (CONFIG_USER_ONLY)
1159
void helper_hw_rei (void)
1160
{
1161
    env->pc = env->ipr[IPR_EXC_ADDR] & ~3;
1162
    env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
1163
    env->intr_flag = 0;
1164
    env->lock_addr = -1;
1165
    /* XXX: re-enable interrupts and memory mapping */
1166
}
1167

  
1168 1159
void helper_hw_ret (uint64_t a)
1169 1160
{
1170 1161
    env->pc = a & ~3;
1171 1162
    env->ipr[IPR_EXC_ADDR] = a & 1;
1172 1163
    env->intr_flag = 0;
1173 1164
    env->lock_addr = -1;
1174
    /* XXX: re-enable interrupts and memory mapping */
1175 1165
}
1176 1166

  
1177 1167
uint64_t helper_mfpr (int iprn, uint64_t val)
b/target-alpha/translate.c
2876 2876
        break;
2877 2877
#endif
2878 2878
    case 0x1E:
2879
        /* HW_REI (PALcode) */
2879
        /* HW_RET (PALcode) */
2880 2880
#if defined (CONFIG_USER_ONLY)
2881 2881
        goto invalid_opc;
2882 2882
#else
2883 2883
        if (!ctx->pal_mode)
2884 2884
            goto invalid_opc;
2885 2885
        if (rb == 31) {
2886
            /* "Old" alpha */
2887
            gen_helper_hw_rei();
2888
        } else {
2889
            TCGv tmp;
2890

  
2891
            if (ra != 31) {
2892
                tmp = tcg_temp_new();
2893
                tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51));
2894
            } else
2895
                tmp = tcg_const_i64(((int64_t)insn << 51) >> 51);
2886
            /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return
2887
               address from EXC_ADDR.  This turns out to be useful for our
2888
               emulation PALcode, so continue to accept it.  */
2889
            TCGv tmp = tcg_temp_new();
2890
            tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, ipr[IPR_EXC_ADDR]));
2896 2891
            gen_helper_hw_ret(tmp);
2897 2892
            tcg_temp_free(tmp);
2893
        } else {
2894
            gen_helper_hw_ret(cpu_ir[rb]);
2898 2895
        }
2899 2896
        ret = EXIT_PC_UPDATED;
2900 2897
        break;

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