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1
/*
2
 *  PPC emulation helpers for qemu.
3
 * 
4
 *  Copyright (c) 2003 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include "exec.h"
21
#if defined (USE_OPEN_FIRMWARE)
22
#include <time.h>
23
#include "of.h"
24
#endif
25

    
26
//#define DEBUG_MMU
27
//#define DEBUG_BATS
28
//#define DEBUG_EXCEPTIONS
29

    
30
extern FILE *stdout, *stderr;
31

    
32
/*****************************************************************************/
33
/* PPC MMU emulation */
34
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
35
                              int is_user, int is_softmmu);
36

    
37
/* Perform BAT hit & translation */
38
static int get_bat (CPUState *env, uint32_t *real, int *prot,
39
                    uint32_t virtual, int rw, int type)
40
{
41
    uint32_t *BATlt, *BATut, *BATu, *BATl;
42
    uint32_t base, BEPIl, BEPIu, bl;
43
    int i;
44
    int ret = -1;
45

    
46
#if defined (DEBUG_BATS)
47
    if (loglevel > 0) {
48
        fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
49
               type == ACCESS_CODE ? 'I' : 'D', virtual);
50
    }
51
#endif
52
    switch (type) {
53
    case ACCESS_CODE:
54
        BATlt = env->IBAT[1];
55
        BATut = env->IBAT[0];
56
        break;
57
    default:
58
        BATlt = env->DBAT[1];
59
        BATut = env->DBAT[0];
60
        break;
61
    }
62
#if defined (DEBUG_BATS)
63
    if (loglevel > 0) {
64
        fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
65
               type == ACCESS_CODE ? 'I' : 'D', virtual);
66
    }
67
#endif
68
    base = virtual & 0xFFFC0000;
69
    for (i = 0; i < 4; i++) {
70
        BATu = &BATut[i];
71
        BATl = &BATlt[i];
72
        BEPIu = *BATu & 0xF0000000;
73
        BEPIl = *BATu & 0x0FFE0000;
74
        bl = (*BATu & 0x00001FFC) << 15;
75
#if defined (DEBUG_BATS)
76
        if (loglevel > 0) {
77
            fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
78
                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
79
                    *BATu, *BATl);
80
        }
81
#endif
82
        if ((virtual & 0xF0000000) == BEPIu &&
83
            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
84
            /* BAT matches */
85
            if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
86
                (msr_pr == 1 && (*BATu & 0x00000001))) {
87
                /* Get physical address */
88
                *real = (*BATl & 0xF0000000) |
89
                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
90
                    (virtual & 0x0001F000);
91
                if (*BATl & 0x00000001)
92
                    *prot = PAGE_READ;
93
                if (*BATl & 0x00000002)
94
                    *prot = PAGE_WRITE | PAGE_READ;
95
#if defined (DEBUG_BATS)
96
                if (loglevel > 0) {
97
                    fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
98
                            i, *real, *prot & PAGE_READ ? 'R' : '-',
99
                            *prot & PAGE_WRITE ? 'W' : '-');
100
                }
101
#endif
102
                ret = 0;
103
                break;
104
            }
105
        }
106
    }
107
    if (ret < 0) {
108
#if defined (DEBUG_BATS)
109
        printf("no BAT match for 0x%08x:\n", virtual);
110
        for (i = 0; i < 4; i++) {
111
            BATu = &BATut[i];
112
            BATl = &BATlt[i];
113
            BEPIu = *BATu & 0xF0000000;
114
            BEPIl = *BATu & 0x0FFE0000;
115
            bl = (*BATu & 0x00001FFC) << 15;
116
            printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
117
                   "0x%08x 0x%08x 0x%08x\n",
118
                   __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
119
                   *BATu, *BATl, BEPIu, BEPIl, bl);
120
        }
121
#endif
122
    }
123
    /* No hit */
124
    return ret;
125
}
126

    
127
/* PTE table lookup */
128
static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
129
                     int h, int key, int rw)
130
{
131
    uint32_t pte0, pte1, keep = 0, access = 0;
132
    int i, good = -1, store = 0;
133
    int ret = -1; /* No entry found */
134

    
135
    for (i = 0; i < 8; i++) {
136
        pte0 = ldl_raw(phys_ram_base + base + (i * 8));
137
        pte1 =  ldl_raw(phys_ram_base + base + (i * 8) + 4);
138
#if defined (DEBUG_MMU)
139
        if (loglevel > 0) {
140
            fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
141
                    "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
142
                    pte0 >> 31, h, (pte0 >> 6) & 1, va);
143
        }
144
#endif
145
        /* Check validity and table match */
146
        if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
147
            /* Check vsid & api */
148
            if ((pte0 & 0x7FFFFFBF) == va) {
149
                if (good == -1) {
150
                    good = i;
151
                    keep = pte1;
152
                } else {
153
                    /* All matches should have equal RPN, WIMG & PP */
154
                    if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
155
                        if (loglevel > 0)
156
                            fprintf(logfile, "Bad RPN/WIMG/PP\n");
157
                        return -1;
158
                    }
159
                }
160
                /* Check access rights */
161
                if (key == 0) {
162
                    access = PAGE_READ;
163
                    if ((pte1 & 0x00000003) != 0x3)
164
                        access |= PAGE_WRITE;
165
                } else {
166
                    switch (pte1 & 0x00000003) {
167
                    case 0x0:
168
                        access = 0;
169
                        break;
170
                    case 0x1:
171
                    case 0x3:
172
                        access = PAGE_READ;
173
                        break;
174
                    case 0x2:
175
                        access = PAGE_READ | PAGE_WRITE;
176
                        break;
177
                    }
178
                }
179
                if (ret < 0) {
180
                    if ((rw == 0 && (access & PAGE_READ)) ||
181
                        (rw == 1 && (access & PAGE_WRITE))) {
182
#if defined (DEBUG_MMU)
183
                        if (loglevel > 0)
184
                            fprintf(logfile, "PTE access granted !\n");
185
#endif
186
                    good = i;
187
                    keep = pte1;
188
                    ret = 0;
189
                    } else {
190
                        /* Access right violation */
191
                        ret = -2;
192
#if defined (DEBUG_MMU)
193
                        if (loglevel > 0)
194
                            fprintf(logfile, "PTE access rejected\n");
195
#endif
196
                }
197
                    *prot = access;
198
                }
199
            }
200
        }
201
    }
202
    if (good != -1) {
203
        *RPN = keep & 0xFFFFF000;
204
#if defined (DEBUG_MMU)
205
        if (loglevel > 0) {
206
            fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
207
               *RPN, *prot, ret);
208
        }
209
#endif
210
        /* Update page flags */
211
        if (!(keep & 0x00000100)) {
212
            /* Access flag */
213
            keep |= 0x00000100;
214
            store = 1;
215
        }
216
            if (!(keep & 0x00000080)) {
217
            if (rw && ret == 0) {
218
                /* Change flag */
219
                keep |= 0x00000080;
220
                store = 1;
221
            } else {
222
                /* Force page fault for first write access */
223
                *prot &= ~PAGE_WRITE;
224
            }
225
        }
226
        if (store) {
227
            stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
228
        }
229
    }
230

    
231
    return ret;
232
}
233

    
234
static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
235
{
236
    return (sdr1 & 0xFFFF0000) | (hash & mask);
237
}
238

    
239
/* Perform segment based translation */
240
static int get_segment (CPUState *env, uint32_t *real, int *prot,
241
                        uint32_t virtual, int rw, int type)
242
{
243
    uint32_t pg_addr, sdr, ptem, vsid, pgidx;
244
    uint32_t hash, mask;
245
    uint32_t sr;
246
    int key;
247
    int ret = -1, ret2;
248

    
249
    sr = env->sr[virtual >> 28];
250
#if defined (DEBUG_MMU)
251
    if (loglevel > 0) {
252
        fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
253
                "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
254
                virtual, virtual >> 28, sr, env->nip,
255
                env->lr, msr_ir, msr_dr, msr_pr, rw, type);
256
    }
257
#endif
258
    key = (((sr & 0x20000000) && msr_pr == 1) ||
259
        ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
260
    if ((sr & 0x80000000) == 0) {
261
#if defined (DEBUG_MMU)
262
        if (loglevel > 0)
263
            fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
264
                    key, sr & 0x10000000);
265
#endif
266
        /* Check if instruction fetch is allowed, if needed */
267
        if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
268
            /* Page address translation */
269
            vsid = sr & 0x00FFFFFF;
270
            pgidx = (virtual >> 12) & 0xFFFF;
271
            sdr = env->sdr1;
272
            hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
273
            mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
274
            pg_addr = get_pgaddr(sdr, hash, mask);
275
            ptem = (vsid << 7) | (pgidx >> 10);
276
#if defined (DEBUG_MMU)
277
            if (loglevel > 0) {
278
                fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
279
                        "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
280
                        pg_addr);
281
            }
282
#endif
283
            /* Primary table lookup */
284
            ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
285
            if (ret < 0) {
286
                /* Secondary table lookup */
287
                hash = (~hash) & 0x01FFFFC0;
288
                pg_addr = get_pgaddr(sdr, hash, mask);
289
#if defined (DEBUG_MMU)
290
                if (virtual != 0xEFFFFFFF && loglevel > 0) {
291
                    fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
292
                            "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
293
                            hash, pg_addr);
294
                }
295
#endif
296
                ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
297
                if (ret2 != -1)
298
                    ret = ret2;
299
            }
300
        } else {
301
#if defined (DEBUG_MMU)
302
            if (loglevel > 0)
303
                fprintf(logfile, "No access allowed\n");
304
#endif
305
            ret = -3;
306
        }
307
    } else {
308
#if defined (DEBUG_MMU)
309
        if (loglevel > 0)
310
            fprintf(logfile, "direct store...\n");
311
#endif
312
        /* Direct-store segment : absolutely *BUGGY* for now */
313
        switch (type) {
314
        case ACCESS_INT:
315
            /* Integer load/store : only access allowed */
316
            break;
317
        case ACCESS_CODE:
318
            /* No code fetch is allowed in direct-store areas */
319
            return -4;
320
        case ACCESS_FLOAT:
321
            /* Floating point load/store */
322
            return -4;
323
        case ACCESS_RES:
324
            /* lwarx, ldarx or srwcx. */
325
            return -4;
326
        case ACCESS_CACHE:
327
            /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
328
            /* Should make the instruction do no-op.
329
             * As it already do no-op, it's quite easy :-)
330
             */
331
            *real = virtual;
332
            return 0;
333
        case ACCESS_EXT:
334
            /* eciwx or ecowx */
335
            return -4;
336
        default:
337
            if (logfile) {
338
                fprintf(logfile, "ERROR: instruction should not need "
339
                        "address translation\n");
340
            }
341
            printf("ERROR: instruction should not need "
342
                   "address translation\n");
343
            return -4;
344
        }
345
        if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
346
            *real = virtual;
347
            ret = 2;
348
        } else {
349
            ret = -2;
350
        }
351
    }
352

    
353
    return ret;
354
}
355

    
356
int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
357
                          uint32_t address, int rw, int access_type)
358
{
359
    int ret;
360
#if 0
361
    if (loglevel > 0) {
362
        fprintf(logfile, "%s\n", __func__);
363
    }
364
#endif    
365
    if ((access_type == ACCESS_CODE && msr_ir == 0) ||
366
        (access_type != ACCESS_CODE && msr_dr == 0)) {
367
        /* No address translation */
368
        *physical = address & ~0xFFF;
369
        *prot = PAGE_READ | PAGE_WRITE;
370
        ret = 0;
371
    } else {
372
        /* Try to find a BAT */
373
        ret = get_bat(env, physical, prot, address, rw, access_type);
374
        if (ret < 0) {
375
            /* We didn't match any BAT entry */
376
            ret = get_segment(env, physical, prot, address, rw, access_type);
377
        }
378
    }
379
#if 0
380
    if (loglevel > 0) {
381
        fprintf(logfile, "%s address %08x => %08x\n",
382
                __func__, address, *physical);
383
    }
384
#endif    
385
    return ret;
386
}
387

    
388
#if defined(CONFIG_USER_ONLY) 
389
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
390
{
391
    return addr;
392
}
393
#else
394
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
395
{
396
    uint32_t phys_addr;
397
    int prot;
398

    
399
    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
400
        return -1;
401
    return phys_addr;
402
}
403
#endif
404

    
405
#if !defined(CONFIG_USER_ONLY) 
406

    
407
#define MMUSUFFIX _mmu
408
#define GETPC() (__builtin_return_address(0))
409

    
410
#define SHIFT 0
411
#include "softmmu_template.h"
412

    
413
#define SHIFT 1
414
#include "softmmu_template.h"
415

    
416
#define SHIFT 2
417
#include "softmmu_template.h"
418

    
419
#define SHIFT 3
420
#include "softmmu_template.h"
421

    
422
/* try to fill the TLB and return an exception if error. If retaddr is
423
   NULL, it means that the function was called in C code (i.e. not
424
   from generated code or from helper.c) */
425
/* XXX: fix it to restore all registers */
426
void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
427
{
428
    TranslationBlock *tb;
429
    CPUState *saved_env;
430
    unsigned long pc;
431
    int ret;
432

    
433
    /* XXX: hack to restore env in all cases, even if not called from
434
       generated code */
435
    saved_env = env;
436
    env = cpu_single_env;
437
    {
438
        unsigned long tlb_addrr, tlb_addrw;
439
        int index;
440
        index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
441
        tlb_addrr = env->tlb_read[is_user][index].address;
442
        tlb_addrw = env->tlb_write[is_user][index].address;
443
#if 0
444
        if (loglevel) {
445
            fprintf(logfile,
446
                    "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
447
               "(0x%08lx 0x%08lx)\n", __func__, env,
448
               &env->tlb_read[is_user][index], index, addr,
449
               tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
450
               tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
451
        }
452
#endif
453
    }
454
    ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
455
    if (ret) {
456
        if (retaddr) {
457
            /* now we have a real cpu fault */
458
            pc = (unsigned long)retaddr;
459
            tb = tb_find_pc(pc);
460
            if (tb) {
461
                /* the PC is inside the translated code. It means that we have
462
                   a virtual CPU fault */
463
                cpu_restore_state(tb, env, pc, NULL);
464
            }
465
        }
466
        do_raise_exception_err(env->exception_index, env->error_code);
467
    }
468
    {
469
        unsigned long tlb_addrr, tlb_addrw;
470
        int index;
471
        index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
472
        tlb_addrr = env->tlb_read[is_user][index].address;
473
        tlb_addrw = env->tlb_write[is_user][index].address;
474
#if 0
475
        printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
476
               "(0x%08lx 0x%08lx)\n", __func__, env,
477
               &env->tlb_read[is_user][index], index, addr,
478
               tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
479
               tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
480
#endif
481
    }
482
    env = saved_env;
483
}
484

    
485
void cpu_ppc_init_mmu(CPUState *env)
486
{
487
    /* Nothing to do: all translation are disabled */
488
}
489
#endif
490

    
491
/* Perform address translation */
492
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
493
                              int is_user, int is_softmmu)
494
{
495
    uint32_t physical;
496
    int prot;
497
    int exception = 0, error_code = 0;
498
    int access_type;
499
    int ret = 0;
500

    
501
//    printf("%s 0\n", __func__);
502
    access_type = env->access_type;
503
    if (env->user_mode_only) {
504
        /* user mode only emulation */
505
        ret = -2;
506
        goto do_fault;
507
    }
508
    /* NASTY BUG workaround */
509
    if (access_type == ACCESS_CODE && rw) {
510
        printf("%s: ERROR WRITE CODE ACCESS\n", __func__);
511
        access_type = ACCESS_INT;
512
    }
513
    ret = get_physical_address(env, &physical, &prot,
514
                               address, rw, access_type);
515
    if (ret == 0) {
516
        ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
517
                           is_user, is_softmmu);
518
    } else if (ret < 0) {
519
    do_fault:
520
#if defined (DEBUG_MMU)
521
        if (loglevel > 0)
522
            cpu_ppc_dump_state(env, logfile, 0);
523
#endif
524
        if (access_type == ACCESS_CODE) {
525
            exception = EXCP_ISI;
526
            switch (ret) {
527
            case -1:
528
                /* No matches in page tables */
529
                error_code = EXCP_ISI_TRANSLATE;
530
                break;
531
            case -2:
532
                /* Access rights violation */
533
                error_code = EXCP_ISI_PROT;
534
                break;
535
            case -3:
536
                /* No execute protection violation */
537
                error_code = EXCP_ISI_NOEXEC;
538
                break;
539
            case -4:
540
                /* Direct store exception */
541
                /* No code fetch is allowed in direct-store areas */
542
                error_code = EXCP_ISI_DIRECT;
543
                break;
544
            }
545
        } else {
546
            exception = EXCP_DSI;
547
            switch (ret) {
548
            case -1:
549
                /* No matches in page tables */
550
                error_code = EXCP_DSI_TRANSLATE;
551
                break;
552
            case -2:
553
                /* Access rights violation */
554
                error_code = EXCP_DSI_PROT;
555
                break;
556
            case -4:
557
                /* Direct store exception */
558
                switch (access_type) {
559
                case ACCESS_FLOAT:
560
                    /* Floating point load/store */
561
                    exception = EXCP_ALIGN;
562
                    error_code = EXCP_ALIGN_FP;
563
                    break;
564
                case ACCESS_RES:
565
                    /* lwarx, ldarx or srwcx. */
566
                    exception = EXCP_DSI;
567
                    error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
568
                    break;
569
                case ACCESS_EXT:
570
                    /* eciwx or ecowx */
571
                    exception = EXCP_DSI;
572
                    error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
573
                        EXCP_DSI_ECXW;
574
                    break;
575
                default:
576
                    printf("DSI: invalid exception (%d)\n", ret);
577
                    exception = EXCP_PROGRAM;
578
                    error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
579
                    break;
580
                }
581
            }
582
            if (rw)
583
                error_code |= EXCP_DSI_STORE;
584
            /* Store fault address */
585
            env->spr[DAR] = address;
586
        }
587
#if 0
588
        printf("%s: set exception to %d %02x\n",
589
               __func__, exception, error_code);
590
#endif
591
        env->exception_index = exception;
592
        env->error_code = error_code;
593
        ret = 1;
594
    }
595

    
596
    return ret;
597
}
598

    
599
uint32_t _load_xer (CPUState *env)
600
{
601
    return (xer_so << XER_SO) |
602
        (xer_ov << XER_OV) |
603
        (xer_ca << XER_CA) |
604
        (xer_bc << XER_BC);
605
}
606

    
607
void _store_xer (CPUState *env, uint32_t value)
608
{
609
    xer_so = (value >> XER_SO) & 0x01;
610
    xer_ov = (value >> XER_OV) & 0x01;
611
    xer_ca = (value >> XER_CA) & 0x01;
612
    xer_bc = (value >> XER_BC) & 0x1f;
613
}
614

    
615
uint32_t _load_msr (CPUState *env)
616
{
617
    return (msr_pow << MSR_POW) |
618
        (msr_ile << MSR_ILE) |
619
        (msr_ee << MSR_EE) |
620
        (msr_pr << MSR_PR) |
621
        (msr_fp << MSR_FP) |
622
        (msr_me << MSR_ME) |
623
        (msr_fe0 << MSR_FE0) |
624
        (msr_se << MSR_SE) |
625
        (msr_be << MSR_BE) |
626
        (msr_fe1 << MSR_FE1) |
627
        (msr_ip << MSR_IP) |
628
        (msr_ir << MSR_IR) |
629
        (msr_dr << MSR_DR) |
630
        (msr_ri << MSR_RI) |
631
        (msr_le << MSR_LE);
632
}
633

    
634
void _store_msr (CPUState *env, uint32_t value)
635
{
636
#if 0 // TRY
637
    if (((value >> MSR_IR) & 0x01) != msr_ir ||
638
        ((value >> MSR_DR) & 0x01) != msr_dr)
639
    {
640
        /* Flush all tlb when changing translation mode or privilege level */
641
        tlb_flush(env, 1);
642
    }
643
#endif
644
    msr_pow = (value >> MSR_POW) & 0x03;
645
    msr_ile = (value >> MSR_ILE) & 0x01;
646
    msr_ee = (value >> MSR_EE) & 0x01;
647
    msr_pr = (value >> MSR_PR) & 0x01;
648
    msr_fp = (value >> MSR_FP) & 0x01;
649
    msr_me = (value >> MSR_ME) & 0x01;
650
    msr_fe0 = (value >> MSR_FE0) & 0x01;
651
    msr_se = (value >> MSR_SE) & 0x01;
652
    msr_be = (value >> MSR_BE) & 0x01;
653
    msr_fe1 = (value >> MSR_FE1) & 0x01;
654
    msr_ip = (value >> MSR_IP) & 0x01;
655
    msr_ir = (value >> MSR_IR) & 0x01;
656
    msr_dr = (value >> MSR_DR) & 0x01;
657
    msr_ri = (value >> MSR_RI) & 0x01;
658
    msr_le = (value >> MSR_LE) & 0x01;
659
}
660

    
661
void do_interrupt (CPUState *env)
662
{
663
#if defined (CONFIG_USER_ONLY)
664
    env->exception_index |= 0x100;
665
#else
666
    uint32_t msr;
667
    int excp = env->exception_index;
668

    
669
    msr = _load_msr(env);
670
#if defined (DEBUG_EXCEPTIONS)
671
    if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) 
672
    {
673
        if (loglevel > 0) {
674
            fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
675
                    env->nip, excp << 8, env->error_code);
676
    }
677
        if (loglevel > 0)
678
            cpu_ppc_dump_state(env, logfile, 0);
679
    }
680
#endif
681
    /* Generate informations in save/restore registers */
682
    switch (excp) {
683
    case EXCP_OFCALL:
684
#if defined (USE_OPEN_FIRMWARE)
685
        env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
686
#endif
687
        return;
688
    case EXCP_RTASCALL:
689
#if defined (USE_OPEN_FIRMWARE)
690
        printf("RTAS call !\n");
691
        env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
692
        printf("RTAS call done\n");
693
#endif
694
        return;
695
    case EXCP_NONE:
696
        /* Do nothing */
697
#if defined (DEBUG_EXCEPTIONS)
698
        printf("%s: escape EXCP_NONE\n", __func__);
699
#endif
700
        return;
701
    case EXCP_RESET:
702
        if (msr_ip)
703
            excp += 0xFFC00;
704
        goto store_next;
705
    case EXCP_MACHINE_CHECK:
706
        if (msr_me == 0) {
707
            cpu_abort(env, "Machine check exception while not allowed\n");
708
        }
709
        msr_me = 0;
710
        break;
711
    case EXCP_DSI:
712
        /* Store exception cause */
713
        /* data location address has been stored
714
         * when the fault has been detected
715
     */
716
        msr &= ~0xFFFF0000;
717
        env->spr[DSISR] = 0;
718
        if (env->error_code &  EXCP_DSI_TRANSLATE)
719
            env->spr[DSISR] |= 0x40000000;
720
        else if (env->error_code & EXCP_DSI_PROT)
721
            env->spr[DSISR] |= 0x08000000;
722
        else if (env->error_code & EXCP_DSI_NOTSUP) {
723
            env->spr[DSISR] |= 0x80000000;
724
            if (env->error_code & EXCP_DSI_DIRECT)
725
                env->spr[DSISR] |= 0x04000000;
726
        }
727
        if (env->error_code & EXCP_DSI_STORE)
728
            env->spr[DSISR] |= 0x02000000;
729
        if ((env->error_code & 0xF) == EXCP_DSI_DABR)
730
            env->spr[DSISR] |= 0x00400000;
731
        if (env->error_code & EXCP_DSI_ECXW)
732
            env->spr[DSISR] |= 0x00100000;
733
#if defined (DEBUG_EXCEPTIONS)
734
        if (loglevel) {
735
            fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
736
                    env->spr[DSISR], env->spr[DAR]);
737
        } else {
738
            printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
739
                   env->spr[DSISR], env->spr[DAR], env->nip);
740
        }
741
#endif
742
        goto store_next;
743
    case EXCP_ISI:
744
        /* Store exception cause */
745
        msr &= ~0xFFFF0000;
746
        if (env->error_code == EXCP_ISI_TRANSLATE)
747
            msr |= 0x40000000;
748
        else if (env->error_code == EXCP_ISI_NOEXEC ||
749
                 env->error_code == EXCP_ISI_GUARD ||
750
                 env->error_code == EXCP_ISI_DIRECT)
751
            msr |= 0x10000000;
752
        else
753
            msr |= 0x08000000;
754
#if defined (DEBUG_EXCEPTIONS)
755
        if (loglevel) {
756
            fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
757
                    msr, env->nip);
758
        } else {
759
            printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
760
                   msr, env->nip, env->spr[V_TBL]);
761
        }
762
#endif
763
        goto store_next;
764
    case EXCP_EXTERNAL:
765
        if (msr_ee == 0) {
766
#if defined (DEBUG_EXCEPTIONS)
767
            if (loglevel > 0) {
768
                fprintf(logfile, "Skipping hardware interrupt\n");
769
    }
770
#endif
771
            /* Requeue it */
772
            do_raise_exception(EXCP_EXTERNAL);
773
            return;
774
            }
775
        goto store_next;
776
    case EXCP_ALIGN:
777
        /* Store exception cause */
778
        /* Get rS/rD and rA from faulting opcode */
779
        env->spr[DSISR] |=
780
            (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
781
        /* data location address has been stored
782
         * when the fault has been detected
783
         */
784
        goto store_current;
785
    case EXCP_PROGRAM:
786
        msr &= ~0xFFFF0000;
787
        switch (env->error_code & ~0xF) {
788
        case EXCP_FP:
789
            if (msr_fe0 == 0 && msr_fe1 == 0) {
790
#if defined (DEBUG_EXCEPTIONS)
791
                printf("Ignore floating point exception\n");
792
#endif
793
                return;
794
        }
795
            msr |= 0x00100000;
796
            /* Set FX */
797
            env->fpscr[7] |= 0x8;
798
            /* Finally, update FEX */
799
            if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
800
                ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
801
                env->fpscr[7] |= 0x4;
802
        break;
803
        case EXCP_INVAL:
804
            //            printf("Invalid instruction at 0x%08x\n", env->nip);
805
            msr |= 0x00080000;
806
        break;
807
        case EXCP_PRIV:
808
            msr |= 0x00040000;
809
        break;
810
        case EXCP_TRAP:
811
            msr |= 0x00020000;
812
            break;
813
        default:
814
            /* Should never occur */
815
        break;
816
    }
817
        msr |= 0x00010000;
818
        goto store_current;
819
    case EXCP_NO_FP:
820
        goto store_current;
821
    case EXCP_DECR:
822
        if (msr_ee == 0) {
823
            /* Requeue it */
824
            do_raise_exception(EXCP_DECR);
825
            return;
826
        }
827
        goto store_next;
828
    case EXCP_SYSCALL:
829
#if defined (DEBUG_EXCEPTIONS)
830
        if (msr_pr) {
831
            if (loglevel) {
832
                fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
833
                        env->gpr[0], env->gpr[3], env->gpr[4],
834
                        env->gpr[5], env->gpr[6]);
835
            } else {
836
                printf("syscall %d from 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
837
                       env->gpr[0], env->nip, env->gpr[3], env->gpr[4],
838
                       env->gpr[5], env->gpr[6]);
839
            }
840
        }
841
#endif
842
        goto store_next;
843
    case EXCP_TRACE:
844
        goto store_next;
845
    case EXCP_FP_ASSIST:
846
        goto store_next;
847
    case EXCP_MTMSR:
848
        /* Nothing to do */
849
        return;
850
    case EXCP_BRANCH:
851
        /* Nothing to do */
852
        return;
853
    case EXCP_RFI:
854
        /* Restore user-mode state */
855
        tb_flush(env);
856
#if defined (DEBUG_EXCEPTIONS)
857
        if (msr_pr == 1)
858
            printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
859
#endif
860
        return;
861
    store_current:
862
        /* SRR0 is set to current instruction */
863
        env->spr[SRR0] = (uint32_t)env->nip - 4;
864
        break;
865
    store_next:
866
        /* SRR0 is set to next instruction */
867
        env->spr[SRR0] = (uint32_t)env->nip;
868
        break;
869
    }
870
    env->spr[SRR1] = msr;
871
    /* reload MSR with correct bits */
872
    msr_pow = 0;
873
    msr_ee = 0;
874
    msr_pr = 0;
875
    msr_fp = 0;
876
    msr_fe0 = 0;
877
    msr_se = 0;
878
    msr_be = 0;
879
    msr_fe1 = 0;
880
    msr_ir = 0;
881
    msr_dr = 0;
882
    msr_ri = 0;
883
    msr_le = msr_ile;
884
    /* Jump to handler */
885
    env->nip = excp << 8;
886
    env->exception_index = EXCP_NONE;
887
    /* Invalidate all TLB as we may have changed translation mode */
888
    tlb_flush(env, 1);
889
    /* ensure that no TB jump will be modified as
890
       the program flow was changed */
891
#ifdef __sparc__
892
    tmp_T0 = 0;
893
#else
894
    T0 = 0;
895
#endif
896
#endif
897
    env->exception_index = -1;
898
}