root / hw / pci_bridge.c @ 51a92333
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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to dea
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* split out from pci.c
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*/
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#include "pci_bridge.h" |
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#include "pci_internals.h" |
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PCIDevice *pci_bridge_get_device(PCIBus *bus) |
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{ |
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return bus->parent_dev;
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} |
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static uint32_t pci_config_get_io_base(PCIDevice *d,
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uint32_t base, uint32_t base_upper16) |
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{ |
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uint32_t val; |
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val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
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if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
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val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
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} |
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return val;
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} |
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static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
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{ |
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return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
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<< 16;
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} |
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static pcibus_t pci_config_get_pref_base(PCIDevice *d,
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uint32_t base, uint32_t upper) |
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{ |
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pcibus_t tmp; |
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pcibus_t val; |
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tmp = (pcibus_t)pci_get_word(d->config + base); |
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val = (tmp & PCI_PREF_RANGE_MASK) << 16;
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if (tmp & PCI_PREF_RANGE_TYPE_64) {
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val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
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} |
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return val;
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} |
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pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type) |
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{ |
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pcibus_t base; |
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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base = pci_config_get_io_base(bridge, |
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PCI_IO_BASE, PCI_IO_BASE_UPPER16); |
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} else {
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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base = pci_config_get_pref_base( |
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bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); |
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} else {
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base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); |
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} |
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} |
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return base;
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} |
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pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type) |
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{ |
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pcibus_t limit; |
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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limit = pci_config_get_io_base(bridge, |
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PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); |
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limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ |
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} else {
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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limit = pci_config_get_pref_base( |
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bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); |
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} else {
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limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); |
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} |
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limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ |
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} |
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return limit;
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} |
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static void pci_bridge_write_config(PCIDevice *d, |
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uint32_t address, uint32_t val, int len)
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{ |
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pci_default_write_config(d, address, val, len); |
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if (/* io base/limit */ |
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ranges_overlap(address, len, PCI_IO_BASE, 2) ||
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/* memory base/limit, prefetchable base/limit and
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io base/limit upper 16 */
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ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
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PCIBridge *s = container_of(d, PCIBridge, dev); |
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pci_bridge_update_mappings(&s->sec_bus); |
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} |
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} |
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static int pci_bridge_initfn(PCIDevice *dev) |
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{ |
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PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
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pci_config_set_vendor_id(s->dev.config, s->vid); |
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pci_config_set_device_id(s->dev.config, s->did); |
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pci_set_word(dev->config + PCI_STATUS, |
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PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
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pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); |
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dev->config[PCI_HEADER_TYPE] = |
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(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | |
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PCI_HEADER_TYPE_BRIDGE; |
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pci_set_word(dev->config + PCI_SEC_STATUS, |
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PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
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return 0; |
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} |
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static int pci_bridge_exitfn(PCIDevice *pci_dev) |
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{ |
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PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); |
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assert(QLIST_EMPTY(&s->sec_bus.child)); |
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QLIST_REMOVE(&s->sec_bus, sibling); |
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return 0; |
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} |
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PCIBus *pci_bridge_init(PCIBus *bus, int devfn, bool multifunction, |
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uint16_t vid, uint16_t did, |
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pci_map_irq_fn map_irq, const char *name) |
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{ |
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PCIDevice *dev; |
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PCIBridge *s; |
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PCIBus *sec_bus; |
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dev = pci_create_multifunction(bus, devfn, multifunction, "pci-bridge");
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qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
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qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
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qdev_init_nofail(&dev->qdev); |
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s = DO_UPCAST(PCIBridge, dev, dev); |
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sec_bus = &s->sec_bus; |
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qbus_create_inplace(&sec_bus->qbus, &pci_bus_info, &dev->qdev, name); |
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sec_bus->parent_dev = dev; |
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sec_bus->map_irq = map_irq; |
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QLIST_INIT(&sec_bus->child); |
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QLIST_INSERT_HEAD(&bus->child, sec_bus, sibling); |
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return &s->sec_bus;
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} |
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static PCIDeviceInfo bridge_info = {
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.qdev.name = "pci-bridge",
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.qdev.size = sizeof(PCIBridge),
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.init = pci_bridge_initfn, |
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.exit = pci_bridge_exitfn, |
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.config_write = pci_bridge_write_config, |
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.is_bridge = 1,
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.qdev.props = (Property[]) { |
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DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), |
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DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), |
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DEFINE_PROP_END_OF_LIST(), |
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} |
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}; |
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static void pci_register_devices(void) |
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{ |
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pci_qdev_register(&bridge_info); |
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} |
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device_init(pci_register_devices) |