Revision 51b2772f
| b/hw/mips_malta.c | ||
|---|---|---|
| 748 | 748 |
{
|
| 749 | 749 |
CPUState *env = opaque; |
| 750 | 750 |
cpu_reset(env); |
| 751 |
cpu_mips_register(env, NULL); |
|
| 751 | 752 |
|
| 752 | 753 |
/* The bootload does not need to be rewritten as it is located in a |
| 753 | 754 |
read only location. The kernel location and the arguments table |
| b/hw/mips_pica61.c | ||
|---|---|---|
| 51 | 51 |
{
|
| 52 | 52 |
CPUState *env = opaque; |
| 53 | 53 |
cpu_reset(env); |
| 54 |
cpu_mips_register(env, NULL); |
|
| 54 | 55 |
} |
| 55 | 56 |
|
| 56 | 57 |
static |
| b/hw/mips_r4k.c | ||
|---|---|---|
| 128 | 128 |
{
|
| 129 | 129 |
CPUState *env = opaque; |
| 130 | 130 |
cpu_reset(env); |
| 131 |
cpu_mips_register(env, NULL); |
|
| 131 | 132 |
|
| 132 | 133 |
if (env->kernel_filename) |
| 133 | 134 |
load_kernel (env, env->ram_size, env->kernel_filename, |
| b/target-mips/cpu.h | ||
|---|---|---|
| 48 | 48 |
target_ulong PFN[2]; |
| 49 | 49 |
}; |
| 50 | 50 |
|
| 51 |
typedef struct mips_def_t mips_def_t; |
|
| 52 |
|
|
| 51 | 53 |
typedef struct CPUMIPSState CPUMIPSState; |
| 52 | 54 |
struct CPUMIPSState {
|
| 53 | 55 |
/* General integer registers */ |
| ... | ... | |
| 295 | 297 |
const char *kernel_cmdline; |
| 296 | 298 |
const char *initrd_filename; |
| 297 | 299 |
|
| 300 |
mips_def_t *cpu_model; |
|
| 301 |
|
|
| 298 | 302 |
struct QEMUTimer *timer; /* Internal timer */ |
| 299 | 303 |
}; |
| 300 | 304 |
|
| ... | ... | |
| 308 | 312 |
void r4k_do_tlbwr (void); |
| 309 | 313 |
void r4k_do_tlbp (void); |
| 310 | 314 |
void r4k_do_tlbr (void); |
| 311 |
typedef struct mips_def_t mips_def_t; |
|
| 312 | 315 |
int mips_find_by_name (const unsigned char *name, mips_def_t **def); |
| 313 | 316 |
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 314 | 317 |
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def); |
| b/target-mips/translate_init.c | ||
|---|---|---|
| 207 | 207 |
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) |
| 208 | 208 |
{
|
| 209 | 209 |
if (!def) |
| 210 |
def = env->cpu_model; |
|
| 211 |
if (!def) |
|
| 210 | 212 |
cpu_abort(env, "Unable to find MIPS CPU definition\n"); |
| 213 |
env->cpu_model = def; |
|
| 211 | 214 |
env->CP0_PRid = def->CP0_PRid; |
| 212 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 213 |
env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE); |
|
| 214 |
#else |
|
| 215 | 215 |
env->CP0_Config0 = def->CP0_Config0; |
| 216 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 217 |
env->CP0_Config0 |= (1 << CP0C0_BE); |
|
| 216 | 218 |
#endif |
| 217 | 219 |
env->CP0_Config1 = def->CP0_Config1; |
| 218 | 220 |
env->CP0_Config2 = def->CP0_Config2; |
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