Revision 51cc2e78 target-mips/translate.c

b/target-mips/translate.c
8598 8598
        return NULL;
8599 8599
    env = qemu_mallocz(sizeof(CPUMIPSState));
8600 8600
    env->cpu_model = def;
8601
    env->cpu_model_str = cpu_model;
8601 8602

  
8602 8603
    cpu_exec_init(env);
8603
    env->cpu_model_str = cpu_model;
8604
#ifndef CONFIG_USER_ONLY
8605
    mmu_init(env, def);
8606
#endif
8607
    fpu_init(env, def);
8608
    mvp_init(env, def);
8604 8609
    mips_tcg_init();
8605 8610
    cpu_reset(env);
8606 8611
    qemu_init_vcpu(env);
......
8615 8620
    }
8616 8621

  
8617 8622
    memset(env, 0, offsetof(CPUMIPSState, breakpoints));
8618

  
8619 8623
    tlb_flush(env, 1);
8620 8624

  
8621
    /* Minimal init */
8625
    /* Reset registers to their default values */
8626
    env->CP0_PRid = env->cpu_model->CP0_PRid;
8627
    env->CP0_Config0 = env->cpu_model->CP0_Config0;
8628
#ifdef TARGET_WORDS_BIGENDIAN
8629
    env->CP0_Config0 |= (1 << CP0C0_BE);
8630
#endif
8631
    env->CP0_Config1 = env->cpu_model->CP0_Config1;
8632
    env->CP0_Config2 = env->cpu_model->CP0_Config2;
8633
    env->CP0_Config3 = env->cpu_model->CP0_Config3;
8634
    env->CP0_Config6 = env->cpu_model->CP0_Config6;
8635
    env->CP0_Config7 = env->cpu_model->CP0_Config7;
8636
    env->SYNCI_Step = env->cpu_model->SYNCI_Step;
8637
    env->CCRes = env->cpu_model->CCRes;
8638
    env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
8639
    env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
8640
    env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
8641
    env->current_tc = 0;
8642
    env->SEGBITS = env->cpu_model->SEGBITS;
8643
    env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
8644
#if defined(TARGET_MIPS64)
8645
    if (env->cpu_model->insn_flags & ISA_MIPS3) {
8646
        env->SEGMask |= 3ULL << 62;
8647
    }
8648
#endif
8649
    env->PABITS = env->cpu_model->PABITS;
8650
    env->PAMask = (target_ulong)((1ULL << env->cpu_model->PABITS) - 1);
8651
    env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
8652
    env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
8653
    env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
8654
    env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
8655
    env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
8656
    env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
8657
    env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
8658
    env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
8659
    env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
8660
    env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
8661
    env->insn_flags = env->cpu_model->insn_flags;
8662

  
8622 8663
#if defined(CONFIG_USER_ONLY)
8623 8664
    env->hflags = MIPS_HFLAG_UM;
8624 8665
    /* Enable access to the SYNCI_Step register.  */
......
8632 8673
        env->CP0_ErrorEPC = env->active_tc.PC;
8633 8674
    }
8634 8675
    env->active_tc.PC = (int32_t)0xBFC00000;
8676
    env->CP0_Random = env->tlb->nb_tlb - 1;
8677
    env->tlb->tlb_in_use = env->tlb->nb_tlb;
8635 8678
    env->CP0_Wired = 0;
8636 8679
    /* SMP not implemented */
8637 8680
    env->CP0_EBase = 0x80000000;
......
8653 8696
    env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
8654 8697
    env->hflags = MIPS_HFLAG_CP0;
8655 8698
#endif
8699
#if defined(TARGET_MIPS64)
8700
    if (env->cpu_model->insn_flags & ISA_MIPS3) {
8701
        env->hflags |= MIPS_HFLAG_64;
8702
    }
8703
#endif
8656 8704
    env->exception_index = EXCP_NONE;
8657
    cpu_mips_register(env, env->cpu_model);
8658 8705
}
8659 8706

  
8660 8707
void gen_pc_load(CPUState *env, TranslationBlock *tb,

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