Revision 51cc2e78 target-mips/translate_init.c

b/target-mips/translate_init.c
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        default:
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            cpu_abort(env, "MMU type not supported\n");
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    }
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    env->CP0_Random = env->tlb->nb_tlb - 1;
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    env->tlb->tlb_in_use = env->tlb->nb_tlb;
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}
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#endif /* CONFIG_USER_ONLY */
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......
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                             (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
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                             (0x1 << CP0MVPC1_PCP1);
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}
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static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
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{
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    env->CP0_PRid = def->CP0_PRid;
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    env->CP0_Config0 = def->CP0_Config0;
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#ifdef TARGET_WORDS_BIGENDIAN
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    env->CP0_Config0 |= (1 << CP0C0_BE);
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#endif
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    env->CP0_Config1 = def->CP0_Config1;
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    env->CP0_Config2 = def->CP0_Config2;
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    env->CP0_Config3 = def->CP0_Config3;
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    env->CP0_Config6 = def->CP0_Config6;
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    env->CP0_Config7 = def->CP0_Config7;
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    env->SYNCI_Step = def->SYNCI_Step;
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    env->CCRes = def->CCRes;
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    env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
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    env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
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    env->CP0_SRSCtl = def->CP0_SRSCtl;
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    env->current_tc = 0;
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    env->SEGBITS = def->SEGBITS;
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    env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1);
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#if defined(TARGET_MIPS64)
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    if (def->insn_flags & ISA_MIPS3) {
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        env->hflags |= MIPS_HFLAG_64;
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        env->SEGMask |= 3ULL << 62;
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    }
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#endif
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    env->PABITS = def->PABITS;
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    env->PAMask = (target_ulong)((1ULL << def->PABITS) - 1);
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    env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask;
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    env->CP0_SRSConf0 = def->CP0_SRSConf0;
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    env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask;
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    env->CP0_SRSConf1 = def->CP0_SRSConf1;
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    env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask;
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    env->CP0_SRSConf2 = def->CP0_SRSConf2;
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    env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask;
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    env->CP0_SRSConf3 = def->CP0_SRSConf3;
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    env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask;
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    env->CP0_SRSConf4 = def->CP0_SRSConf4;
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    env->insn_flags = def->insn_flags;
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#ifndef CONFIG_USER_ONLY
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    mmu_init(env, def);
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#endif
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    fpu_init(env, def);
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    mvp_init(env, def);
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    return 0;
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}

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