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/*
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* Sparc CPU init helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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//#define DEBUG_FEATURES
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static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
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/* CPUClass::reset() */
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static void sparc_cpu_reset(CPUState *s) |
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{
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SPARCCPU *cpu = SPARC_CPU(s); |
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); |
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CPUSPARCState *env = &cpu->env; |
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scc->parent_reset(s); |
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memset(env, 0, offsetof(CPUSPARCState, breakpoints));
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tlb_flush(env, 1);
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env->cwp = 0;
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#ifndef TARGET_SPARC64
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env->wim = 1;
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#endif
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env->regwptr = env->regbase + (env->cwp * 16);
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CC_OP = CC_OP_FLAGS; |
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#if defined(CONFIG_USER_ONLY)
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#ifdef TARGET_SPARC64
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env->cleanwin = env->nwindows - 2;
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env->cansave = env->nwindows - 2;
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env->pstate = PS_RMO | PS_PEF | PS_IE; |
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env->asi = 0x82; /* Primary no-fault */ |
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#endif
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#else
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#if !defined(TARGET_SPARC64)
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env->psret = 0;
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env->psrs = 1;
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env->psrps = 1;
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#endif
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#ifdef TARGET_SPARC64
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env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG; |
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env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
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env->tl = env->maxtl; |
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cpu_tsptr(env)->tt = TT_POWER_ON_RESET; |
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env->lsu = 0;
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#else
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env->mmuregs[0] &= ~(MMU_E | MMU_NF);
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env->mmuregs[0] |= env->def->mmu_bm;
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#endif
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env->pc = 0;
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env->npc = env->pc + 4;
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#endif
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env->cache_control = 0;
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} |
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static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
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{
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sparc_def_t def1, *def = &def1; |
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if (cpu_sparc_find_by_name(def, cpu_model) < 0) { |
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return -1; |
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} |
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env->def = g_new0(sparc_def_t, 1);
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memcpy(env->def, def, sizeof(*def));
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#if defined(CONFIG_USER_ONLY)
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if ((env->def->features & CPU_FEATURE_FLOAT)) {
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env->def->features |= CPU_FEATURE_FLOAT128; |
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} |
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#endif
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env->version = def->iu_version; |
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env->fsr = def->fpu_version; |
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env->nwindows = def->nwindows; |
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#if !defined(TARGET_SPARC64)
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env->mmuregs[0] |= def->mmu_version;
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cpu_sparc_set_id(env, 0);
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env->mxccregs[7] |= def->mxcc_version;
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#else
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env->mmu_version = def->mmu_version; |
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env->maxtl = def->maxtl; |
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env->version |= def->maxtl << 8;
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env->version |= def->nwindows - 1;
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#endif
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return 0; |
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} |
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SPARCCPU *cpu_sparc_init(const char *cpu_model) |
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{
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SPARCCPU *cpu; |
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CPUSPARCState *env; |
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cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU)); |
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env = &cpu->env; |
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if (cpu_sparc_register(env, cpu_model) < 0) { |
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object_unref(OBJECT(cpu)); |
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return NULL; |
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} |
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
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return cpu;
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} |
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void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
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{
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#if !defined(TARGET_SPARC64)
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env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
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#endif
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} |
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static const sparc_def_t sparc_defs[] = { |
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#ifdef TARGET_SPARC64
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{
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.name = "Fujitsu Sparc64",
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.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 4,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Fujitsu Sparc64 III",
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.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 5,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Fujitsu Sparc64 IV",
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.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Fujitsu Sparc64 V",
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.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "TI UltraSparc I",
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.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "TI UltraSparc II",
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.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "TI UltraSparc IIi",
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.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "TI UltraSparc IIe",
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.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Sun UltraSparc III",
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.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Sun UltraSparc III Cu",
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.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Sun UltraSparc IIIi",
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.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Sun UltraSparc IV",
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.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_4, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Sun UltraSparc IV+",
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.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
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}, |
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{
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.name = "Sun UltraSparc IIIi+",
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.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Sun UltraSparc T1",
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/* defined in sparc_ifu_fdp.v and ctu.h */
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.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v, |
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
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| CPU_FEATURE_GL, |
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}, |
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{
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.name = "Sun UltraSparc T2",
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/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
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.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v, |
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
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| CPU_FEATURE_GL, |
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}, |
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{
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.name = "NEC UltraSparc I",
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.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12, |
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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#else
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{
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.name = "Fujitsu MB86904",
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.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
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.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "Fujitsu MB86907",
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.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
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.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
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.name = "TI MicroSparc I",
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.iu_version = 0x41000000,
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.fpu_version = 4 << 17, |
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.mmu_version = 0x41000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_cxr_mask = 0x0000003f,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x0000003f,
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.nwindows = 7,
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.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | |
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CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | |
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CPU_FEATURE_FMUL, |
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}, |
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{
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.name = "TI MicroSparc II",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17, |
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.mmu_version = 0x02000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
|
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.name = "TI MicroSparc IIep",
|
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.iu_version = 0x42000000,
|
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.fpu_version = 4 << 17, |
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.mmu_version = 0x04000000,
|
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.mmu_bm = 0x00004000,
|
| 348 |
.mmu_ctpr_mask = 0x00ffffc0,
|
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.mmu_cxr_mask = 0x000000ff,
|
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.mmu_sfsr_mask = 0x00016bff,
|
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.mmu_trcr_mask = 0x00ffffff,
|
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.nwindows = 8,
|
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.features = CPU_DEFAULT_FEATURES, |
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}, |
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{
|
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.name = "TI SuperSparc 40", /* STP1020NPGA */ |
| 357 |
.iu_version = 0x41000000, /* SuperSPARC 2.x */ |
| 358 |
.fpu_version = 0 << 17, |
| 359 |
.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ |
| 360 |
.mmu_bm = 0x00002000,
|
| 361 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 362 |
.mmu_cxr_mask = 0x0000ffff,
|
| 363 |
.mmu_sfsr_mask = 0xffffffff,
|
| 364 |
.mmu_trcr_mask = 0xffffffff,
|
| 365 |
.nwindows = 8,
|
| 366 |
.features = CPU_DEFAULT_FEATURES, |
| 367 |
}, |
| 368 |
{
|
| 369 |
.name = "TI SuperSparc 50", /* STP1020PGA */ |
| 370 |
.iu_version = 0x40000000, /* SuperSPARC 3.x */ |
| 371 |
.fpu_version = 0 << 17, |
| 372 |
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ |
| 373 |
.mmu_bm = 0x00002000,
|
| 374 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 375 |
.mmu_cxr_mask = 0x0000ffff,
|
| 376 |
.mmu_sfsr_mask = 0xffffffff,
|
| 377 |
.mmu_trcr_mask = 0xffffffff,
|
| 378 |
.nwindows = 8,
|
| 379 |
.features = CPU_DEFAULT_FEATURES, |
| 380 |
}, |
| 381 |
{
|
| 382 |
.name = "TI SuperSparc 51",
|
| 383 |
.iu_version = 0x40000000, /* SuperSPARC 3.x */ |
| 384 |
.fpu_version = 0 << 17, |
| 385 |
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ |
| 386 |
.mmu_bm = 0x00002000,
|
| 387 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 388 |
.mmu_cxr_mask = 0x0000ffff,
|
| 389 |
.mmu_sfsr_mask = 0xffffffff,
|
| 390 |
.mmu_trcr_mask = 0xffffffff,
|
| 391 |
.mxcc_version = 0x00000104,
|
| 392 |
.nwindows = 8,
|
| 393 |
.features = CPU_DEFAULT_FEATURES, |
| 394 |
}, |
| 395 |
{
|
| 396 |
.name = "TI SuperSparc 60", /* STP1020APGA */ |
| 397 |
.iu_version = 0x40000000, /* SuperSPARC 3.x */ |
| 398 |
.fpu_version = 0 << 17, |
| 399 |
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ |
| 400 |
.mmu_bm = 0x00002000,
|
| 401 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 402 |
.mmu_cxr_mask = 0x0000ffff,
|
| 403 |
.mmu_sfsr_mask = 0xffffffff,
|
| 404 |
.mmu_trcr_mask = 0xffffffff,
|
| 405 |
.nwindows = 8,
|
| 406 |
.features = CPU_DEFAULT_FEATURES, |
| 407 |
}, |
| 408 |
{
|
| 409 |
.name = "TI SuperSparc 61",
|
| 410 |
.iu_version = 0x44000000, /* SuperSPARC 3.x */ |
| 411 |
.fpu_version = 0 << 17, |
| 412 |
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ |
| 413 |
.mmu_bm = 0x00002000,
|
| 414 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 415 |
.mmu_cxr_mask = 0x0000ffff,
|
| 416 |
.mmu_sfsr_mask = 0xffffffff,
|
| 417 |
.mmu_trcr_mask = 0xffffffff,
|
| 418 |
.mxcc_version = 0x00000104,
|
| 419 |
.nwindows = 8,
|
| 420 |
.features = CPU_DEFAULT_FEATURES, |
| 421 |
}, |
| 422 |
{
|
| 423 |
.name = "TI SuperSparc II",
|
| 424 |
.iu_version = 0x40000000, /* SuperSPARC II 1.x */ |
| 425 |
.fpu_version = 0 << 17, |
| 426 |
.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ |
| 427 |
.mmu_bm = 0x00002000,
|
| 428 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 429 |
.mmu_cxr_mask = 0x0000ffff,
|
| 430 |
.mmu_sfsr_mask = 0xffffffff,
|
| 431 |
.mmu_trcr_mask = 0xffffffff,
|
| 432 |
.mxcc_version = 0x00000104,
|
| 433 |
.nwindows = 8,
|
| 434 |
.features = CPU_DEFAULT_FEATURES, |
| 435 |
}, |
| 436 |
{
|
| 437 |
.name = "LEON2",
|
| 438 |
.iu_version = 0xf2000000,
|
| 439 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
| 440 |
.mmu_version = 0xf2000000,
|
| 441 |
.mmu_bm = 0x00004000,
|
| 442 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 443 |
.mmu_cxr_mask = 0x0000003f,
|
| 444 |
.mmu_sfsr_mask = 0xffffffff,
|
| 445 |
.mmu_trcr_mask = 0xffffffff,
|
| 446 |
.nwindows = 8,
|
| 447 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, |
| 448 |
}, |
| 449 |
{
|
| 450 |
.name = "LEON3",
|
| 451 |
.iu_version = 0xf3000000,
|
| 452 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
| 453 |
.mmu_version = 0xf3000000,
|
| 454 |
.mmu_bm = 0x00000000,
|
| 455 |
.mmu_ctpr_mask = 0xfffffffc,
|
| 456 |
.mmu_cxr_mask = 0x000000ff,
|
| 457 |
.mmu_sfsr_mask = 0xffffffff,
|
| 458 |
.mmu_trcr_mask = 0xffffffff,
|
| 459 |
.nwindows = 8,
|
| 460 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | |
| 461 |
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN, |
| 462 |
}, |
| 463 |
#endif
|
| 464 |
}; |
| 465 |
|
| 466 |
static const char * const feature_name[] = { |
| 467 |
"float",
|
| 468 |
"float128",
|
| 469 |
"swap",
|
| 470 |
"mul",
|
| 471 |
"div",
|
| 472 |
"flush",
|
| 473 |
"fsqrt",
|
| 474 |
"fmul",
|
| 475 |
"vis1",
|
| 476 |
"vis2",
|
| 477 |
"fsmuld",
|
| 478 |
"hypv",
|
| 479 |
"cmt",
|
| 480 |
"gl",
|
| 481 |
}; |
| 482 |
|
| 483 |
static void print_features(FILE *f, fprintf_function cpu_fprintf, |
| 484 |
uint32_t features, const char *prefix) |
| 485 |
{
|
| 486 |
unsigned int i; |
| 487 |
|
| 488 |
for (i = 0; i < ARRAY_SIZE(feature_name); i++) { |
| 489 |
if (feature_name[i] && (features & (1 << i))) { |
| 490 |
if (prefix) {
|
| 491 |
(*cpu_fprintf)(f, "%s", prefix);
|
| 492 |
} |
| 493 |
(*cpu_fprintf)(f, "%s ", feature_name[i]);
|
| 494 |
} |
| 495 |
} |
| 496 |
} |
| 497 |
|
| 498 |
static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) |
| 499 |
{
|
| 500 |
unsigned int i; |
| 501 |
|
| 502 |
for (i = 0; i < ARRAY_SIZE(feature_name); i++) { |
| 503 |
if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
|
| 504 |
*features |= 1 << i;
|
| 505 |
return;
|
| 506 |
} |
| 507 |
} |
| 508 |
fprintf(stderr, "CPU feature %s not found\n", flagname);
|
| 509 |
} |
| 510 |
|
| 511 |
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
| 512 |
{
|
| 513 |
unsigned int i; |
| 514 |
const sparc_def_t *def = NULL; |
| 515 |
char *s = g_strdup(cpu_model);
|
| 516 |
char *featurestr, *name = strtok(s, ","); |
| 517 |
uint32_t plus_features = 0;
|
| 518 |
uint32_t minus_features = 0;
|
| 519 |
uint64_t iu_version; |
| 520 |
uint32_t fpu_version, mmu_version, nwindows; |
| 521 |
|
| 522 |
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
| 523 |
if (strcasecmp(name, sparc_defs[i].name) == 0) { |
| 524 |
def = &sparc_defs[i]; |
| 525 |
} |
| 526 |
} |
| 527 |
if (!def) {
|
| 528 |
goto error;
|
| 529 |
} |
| 530 |
memcpy(cpu_def, def, sizeof(*def));
|
| 531 |
|
| 532 |
featurestr = strtok(NULL, ","); |
| 533 |
while (featurestr) {
|
| 534 |
char *val;
|
| 535 |
|
| 536 |
if (featurestr[0] == '+') { |
| 537 |
add_flagname_to_bitmaps(featurestr + 1, &plus_features);
|
| 538 |
} else if (featurestr[0] == '-') { |
| 539 |
add_flagname_to_bitmaps(featurestr + 1, &minus_features);
|
| 540 |
} else if ((val = strchr(featurestr, '='))) { |
| 541 |
*val = 0; val++;
|
| 542 |
if (!strcmp(featurestr, "iu_version")) { |
| 543 |
char *err;
|
| 544 |
|
| 545 |
iu_version = strtoll(val, &err, 0);
|
| 546 |
if (!*val || *err) {
|
| 547 |
fprintf(stderr, "bad numerical value %s\n", val);
|
| 548 |
goto error;
|
| 549 |
} |
| 550 |
cpu_def->iu_version = iu_version; |
| 551 |
#ifdef DEBUG_FEATURES
|
| 552 |
fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version); |
| 553 |
#endif
|
| 554 |
} else if (!strcmp(featurestr, "fpu_version")) { |
| 555 |
char *err;
|
| 556 |
|
| 557 |
fpu_version = strtol(val, &err, 0);
|
| 558 |
if (!*val || *err) {
|
| 559 |
fprintf(stderr, "bad numerical value %s\n", val);
|
| 560 |
goto error;
|
| 561 |
} |
| 562 |
cpu_def->fpu_version = fpu_version; |
| 563 |
#ifdef DEBUG_FEATURES
|
| 564 |
fprintf(stderr, "fpu_version %x\n", fpu_version);
|
| 565 |
#endif
|
| 566 |
} else if (!strcmp(featurestr, "mmu_version")) { |
| 567 |
char *err;
|
| 568 |
|
| 569 |
mmu_version = strtol(val, &err, 0);
|
| 570 |
if (!*val || *err) {
|
| 571 |
fprintf(stderr, "bad numerical value %s\n", val);
|
| 572 |
goto error;
|
| 573 |
} |
| 574 |
cpu_def->mmu_version = mmu_version; |
| 575 |
#ifdef DEBUG_FEATURES
|
| 576 |
fprintf(stderr, "mmu_version %x\n", mmu_version);
|
| 577 |
#endif
|
| 578 |
} else if (!strcmp(featurestr, "nwindows")) { |
| 579 |
char *err;
|
| 580 |
|
| 581 |
nwindows = strtol(val, &err, 0);
|
| 582 |
if (!*val || *err || nwindows > MAX_NWINDOWS ||
|
| 583 |
nwindows < MIN_NWINDOWS) {
|
| 584 |
fprintf(stderr, "bad numerical value %s\n", val);
|
| 585 |
goto error;
|
| 586 |
} |
| 587 |
cpu_def->nwindows = nwindows; |
| 588 |
#ifdef DEBUG_FEATURES
|
| 589 |
fprintf(stderr, "nwindows %d\n", nwindows);
|
| 590 |
#endif
|
| 591 |
} else {
|
| 592 |
fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
| 593 |
goto error;
|
| 594 |
} |
| 595 |
} else {
|
| 596 |
fprintf(stderr, "feature string `%s' not in format "
|
| 597 |
"(+feature|-feature|feature=xyz)\n", featurestr);
|
| 598 |
goto error;
|
| 599 |
} |
| 600 |
featurestr = strtok(NULL, ","); |
| 601 |
} |
| 602 |
cpu_def->features |= plus_features; |
| 603 |
cpu_def->features &= ~minus_features; |
| 604 |
#ifdef DEBUG_FEATURES
|
| 605 |
print_features(stderr, fprintf, cpu_def->features, NULL);
|
| 606 |
#endif
|
| 607 |
g_free(s); |
| 608 |
return 0; |
| 609 |
|
| 610 |
error:
|
| 611 |
g_free(s); |
| 612 |
return -1; |
| 613 |
} |
| 614 |
|
| 615 |
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
| 616 |
{
|
| 617 |
unsigned int i; |
| 618 |
|
| 619 |
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
| 620 |
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx
|
| 621 |
" FPU %08x MMU %08x NWINS %d ",
|
| 622 |
sparc_defs[i].name, |
| 623 |
sparc_defs[i].iu_version, |
| 624 |
sparc_defs[i].fpu_version, |
| 625 |
sparc_defs[i].mmu_version, |
| 626 |
sparc_defs[i].nwindows); |
| 627 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
| 628 |
~sparc_defs[i].features, "-");
|
| 629 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & |
| 630 |
sparc_defs[i].features, "+");
|
| 631 |
(*cpu_fprintf)(f, "\n");
|
| 632 |
} |
| 633 |
(*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
|
| 634 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
|
| 635 |
(*cpu_fprintf)(f, "\n");
|
| 636 |
(*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
|
| 637 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
|
| 638 |
(*cpu_fprintf)(f, "\n");
|
| 639 |
(*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
|
| 640 |
"fpu_version mmu_version nwindows\n");
|
| 641 |
} |
| 642 |
|
| 643 |
static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf, |
| 644 |
uint32_t cc) |
| 645 |
{
|
| 646 |
cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', |
| 647 |
cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', |
| 648 |
cc & PSR_CARRY ? 'C' : '-'); |
| 649 |
} |
| 650 |
|
| 651 |
#ifdef TARGET_SPARC64
|
| 652 |
#define REGS_PER_LINE 4 |
| 653 |
#else
|
| 654 |
#define REGS_PER_LINE 8 |
| 655 |
#endif
|
| 656 |
|
| 657 |
void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
|
| 658 |
int flags)
|
| 659 |
{
|
| 660 |
SPARCCPU *cpu = SPARC_CPU(cs); |
| 661 |
CPUSPARCState *env = &cpu->env; |
| 662 |
int i, x;
|
| 663 |
|
| 664 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
| 665 |
env->npc); |
| 666 |
|
| 667 |
for (i = 0; i < 8; i++) { |
| 668 |
if (i % REGS_PER_LINE == 0) { |
| 669 |
cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); |
| 670 |
} |
| 671 |
cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
|
| 672 |
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { |
| 673 |
cpu_fprintf(f, "\n");
|
| 674 |
} |
| 675 |
} |
| 676 |
for (x = 0; x < 3; x++) { |
| 677 |
for (i = 0; i < 8; i++) { |
| 678 |
if (i % REGS_PER_LINE == 0) { |
| 679 |
cpu_fprintf(f, "%%%c%d-%d: ",
|
| 680 |
x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), |
| 681 |
i, i + REGS_PER_LINE - 1);
|
| 682 |
} |
| 683 |
cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); |
| 684 |
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { |
| 685 |
cpu_fprintf(f, "\n");
|
| 686 |
} |
| 687 |
} |
| 688 |
} |
| 689 |
|
| 690 |
for (i = 0; i < TARGET_DPREGS; i++) { |
| 691 |
if ((i & 3) == 0) { |
| 692 |
cpu_fprintf(f, "%%f%02d: ", i * 2); |
| 693 |
} |
| 694 |
cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
|
| 695 |
if ((i & 3) == 3) { |
| 696 |
cpu_fprintf(f, "\n");
|
| 697 |
} |
| 698 |
} |
| 699 |
#ifdef TARGET_SPARC64
|
| 700 |
cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
|
| 701 |
(unsigned)cpu_get_ccr(env));
|
| 702 |
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT); |
| 703 |
cpu_fprintf(f, " xcc: ");
|
| 704 |
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
|
| 705 |
cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
|
| 706 |
env->psrpil); |
| 707 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
|
| 708 |
"cleanwin: %d cwp: %d\n",
|
| 709 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
| 710 |
env->cleanwin, env->nwindows - 1 - env->cwp);
|
| 711 |
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " |
| 712 |
TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
|
| 713 |
#else
|
| 714 |
cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
|
| 715 |
cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env)); |
| 716 |
cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', |
| 717 |
env->psrps ? 'P' : '-', env->psret ? 'E' : '-', |
| 718 |
env->wim); |
| 719 |
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", |
| 720 |
env->fsr, env->y); |
| 721 |
#endif
|
| 722 |
cpu_fprintf(f, "\n");
|
| 723 |
} |
| 724 |
|
| 725 |
static void sparc_cpu_set_pc(CPUState *cs, vaddr value) |
| 726 |
{
|
| 727 |
SPARCCPU *cpu = SPARC_CPU(cs); |
| 728 |
|
| 729 |
cpu->env.pc = value; |
| 730 |
cpu->env.npc = value + 4;
|
| 731 |
} |
| 732 |
|
| 733 |
static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
| 734 |
{
|
| 735 |
SPARCCPU *cpu = SPARC_CPU(cs); |
| 736 |
|
| 737 |
cpu->env.pc = tb->pc; |
| 738 |
cpu->env.npc = tb->cs_base; |
| 739 |
} |
| 740 |
|
| 741 |
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) |
| 742 |
{
|
| 743 |
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); |
| 744 |
|
| 745 |
qemu_init_vcpu(CPU(dev)); |
| 746 |
|
| 747 |
scc->parent_realize(dev, errp); |
| 748 |
} |
| 749 |
|
| 750 |
static void sparc_cpu_initfn(Object *obj) |
| 751 |
{
|
| 752 |
CPUState *cs = CPU(obj); |
| 753 |
SPARCCPU *cpu = SPARC_CPU(obj); |
| 754 |
CPUSPARCState *env = &cpu->env; |
| 755 |
|
| 756 |
cs->env_ptr = env; |
| 757 |
cpu_exec_init(env); |
| 758 |
|
| 759 |
if (tcg_enabled()) {
|
| 760 |
gen_intermediate_code_init(env); |
| 761 |
} |
| 762 |
} |
| 763 |
|
| 764 |
static void sparc_cpu_uninitfn(Object *obj) |
| 765 |
{
|
| 766 |
SPARCCPU *cpu = SPARC_CPU(obj); |
| 767 |
CPUSPARCState *env = &cpu->env; |
| 768 |
|
| 769 |
g_free(env->def); |
| 770 |
} |
| 771 |
|
| 772 |
static void sparc_cpu_class_init(ObjectClass *oc, void *data) |
| 773 |
{
|
| 774 |
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); |
| 775 |
CPUClass *cc = CPU_CLASS(oc); |
| 776 |
DeviceClass *dc = DEVICE_CLASS(oc); |
| 777 |
|
| 778 |
scc->parent_realize = dc->realize; |
| 779 |
dc->realize = sparc_cpu_realizefn; |
| 780 |
|
| 781 |
scc->parent_reset = cc->reset; |
| 782 |
cc->reset = sparc_cpu_reset; |
| 783 |
|
| 784 |
cc->do_interrupt = sparc_cpu_do_interrupt; |
| 785 |
cc->dump_state = sparc_cpu_dump_state; |
| 786 |
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
| 787 |
cc->memory_rw_debug = sparc_cpu_memory_rw_debug; |
| 788 |
#endif
|
| 789 |
cc->set_pc = sparc_cpu_set_pc; |
| 790 |
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; |
| 791 |
cc->gdb_read_register = sparc_cpu_gdb_read_register; |
| 792 |
cc->gdb_write_register = sparc_cpu_gdb_write_register; |
| 793 |
#ifndef CONFIG_USER_ONLY
|
| 794 |
cc->do_unassigned_access = sparc_cpu_unassigned_access; |
| 795 |
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; |
| 796 |
#endif
|
| 797 |
|
| 798 |
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
|
| 799 |
cc->gdb_num_core_regs = 86;
|
| 800 |
#else
|
| 801 |
cc->gdb_num_core_regs = 72;
|
| 802 |
#endif
|
| 803 |
} |
| 804 |
|
| 805 |
static const TypeInfo sparc_cpu_type_info = { |
| 806 |
.name = TYPE_SPARC_CPU, |
| 807 |
.parent = TYPE_CPU, |
| 808 |
.instance_size = sizeof(SPARCCPU),
|
| 809 |
.instance_init = sparc_cpu_initfn, |
| 810 |
.instance_finalize = sparc_cpu_uninitfn, |
| 811 |
.abstract = false,
|
| 812 |
.class_size = sizeof(SPARCCPUClass),
|
| 813 |
.class_init = sparc_cpu_class_init, |
| 814 |
}; |
| 815 |
|
| 816 |
static void sparc_cpu_register_types(void) |
| 817 |
{
|
| 818 |
type_register_static(&sparc_cpu_type_info); |
| 819 |
} |
| 820 |
|
| 821 |
type_init(sparc_cpu_register_types) |