Revision 534ce69f
| b/target-mips/op.c | ||
|---|---|---|
| 1293 | 1293 |
|
| 1294 | 1294 |
void op_mtc0_context (void) |
| 1295 | 1295 |
{
|
| 1296 |
env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & ~0x007FFFFF);
|
|
| 1296 |
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
|
| 1297 | 1297 |
RETURN(); |
| 1298 | 1298 |
} |
| 1299 | 1299 |
|
| ... | ... | |
| 1458 | 1458 |
RETURN(); |
| 1459 | 1459 |
} |
| 1460 | 1460 |
|
| 1461 |
void op_mtc0_xcontext (void) |
|
| 1462 |
{
|
|
| 1463 |
env->CP0_XContext = (int32_t)T0; /* XXX */ |
|
| 1464 |
RETURN(); |
|
| 1465 |
} |
|
| 1466 |
|
|
| 1467 | 1461 |
void op_mtc0_framemask (void) |
| 1468 | 1462 |
{
|
| 1469 | 1463 |
env->CP0_Framemask = T0; /* XXX */ |
| ... | ... | |
| 1528 | 1522 |
RETURN(); |
| 1529 | 1523 |
} |
| 1530 | 1524 |
|
| 1525 |
#ifdef TARGET_MIPS64 |
|
| 1531 | 1526 |
void op_dmfc0_entrylo0 (void) |
| 1532 | 1527 |
{
|
| 1533 | 1528 |
T0 = env->CP0_EntryLo0; |
| ... | ... | |
| 1612 | 1607 |
|
| 1613 | 1608 |
void op_dmtc0_context (void) |
| 1614 | 1609 |
{
|
| 1615 |
env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
|
|
| 1610 |
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
|
|
| 1616 | 1611 |
RETURN(); |
| 1617 | 1612 |
} |
| 1618 | 1613 |
|
| ... | ... | |
| 1632 | 1627 |
|
| 1633 | 1628 |
void op_dmtc0_xcontext (void) |
| 1634 | 1629 |
{
|
| 1635 |
env->CP0_XContext = T0; /* XXX */
|
|
| 1630 |
env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff);
|
|
| 1636 | 1631 |
RETURN(); |
| 1637 | 1632 |
} |
| 1638 | 1633 |
|
| ... | ... | |
| 1647 | 1642 |
env->CP0_ErrorEPC = T0; |
| 1648 | 1643 |
RETURN(); |
| 1649 | 1644 |
} |
| 1645 |
#endif /* TARGET_MIPS64 */ |
|
| 1650 | 1646 |
|
| 1651 | 1647 |
#if 0 |
| 1652 | 1648 |
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env) |
| b/target-mips/translate.c | ||
|---|---|---|
| 2750 | 2750 |
switch (sel) {
|
| 2751 | 2751 |
case 0: |
| 2752 | 2752 |
/* 64 bit MMU only */ |
| 2753 |
gen_op_mtc0_xcontext();
|
|
| 2753 |
/* Nothing writable in lower 32 bits */
|
|
| 2754 | 2754 |
rn = "XContext"; |
| 2755 | 2755 |
break; |
| 2756 | 2756 |
default: |
| ... | ... | |
| 2946 | 2946 |
generate_exception(ctx, EXCP_RI); |
| 2947 | 2947 |
} |
| 2948 | 2948 |
|
| 2949 |
#ifdef TARGET_MIPS64 |
|
| 2949 | 2950 |
static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) |
| 2950 | 2951 |
{
|
| 2951 | 2952 |
const char *rn = "invalid"; |
| ... | ... | |
| 4120 | 4121 |
#endif |
| 4121 | 4122 |
generate_exception(ctx, EXCP_RI); |
| 4122 | 4123 |
} |
| 4124 |
#endif /* TARGET_MIPS64 */ |
|
| 4123 | 4125 |
|
| 4124 | 4126 |
static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd) |
| 4125 | 4127 |
{
|
| ... | ... | |
| 4140 | 4142 |
gen_mtc0(ctx, rd, ctx->opcode & 0x7); |
| 4141 | 4143 |
opn = "mtc0"; |
| 4142 | 4144 |
break; |
| 4145 |
#ifdef TARGET_MIPS64 |
|
| 4143 | 4146 |
case OPC_DMFC0: |
| 4144 | 4147 |
if (rt == 0) {
|
| 4145 | 4148 |
/* Treat as NOP */ |
| ... | ... | |
| 4154 | 4157 |
gen_dmtc0(ctx, rd, ctx->opcode & 0x7); |
| 4155 | 4158 |
opn = "dmtc0"; |
| 4156 | 4159 |
break; |
| 4160 |
#endif |
|
| 4157 | 4161 |
#if defined(MIPS_USES_R4K_TLB) |
| 4158 | 4162 |
case OPC_TLBWI: |
| 4159 | 4163 |
gen_op_tlbwi(); |
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