Revision 534ce69f target-mips/translate.c
b/target-mips/translate.c | ||
---|---|---|
2750 | 2750 |
switch (sel) { |
2751 | 2751 |
case 0: |
2752 | 2752 |
/* 64 bit MMU only */ |
2753 |
gen_op_mtc0_xcontext();
|
|
2753 |
/* Nothing writable in lower 32 bits */
|
|
2754 | 2754 |
rn = "XContext"; |
2755 | 2755 |
break; |
2756 | 2756 |
default: |
... | ... | |
2946 | 2946 |
generate_exception(ctx, EXCP_RI); |
2947 | 2947 |
} |
2948 | 2948 |
|
2949 |
#ifdef TARGET_MIPS64 |
|
2949 | 2950 |
static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) |
2950 | 2951 |
{ |
2951 | 2952 |
const char *rn = "invalid"; |
... | ... | |
4120 | 4121 |
#endif |
4121 | 4122 |
generate_exception(ctx, EXCP_RI); |
4122 | 4123 |
} |
4124 |
#endif /* TARGET_MIPS64 */ |
|
4123 | 4125 |
|
4124 | 4126 |
static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd) |
4125 | 4127 |
{ |
... | ... | |
4140 | 4142 |
gen_mtc0(ctx, rd, ctx->opcode & 0x7); |
4141 | 4143 |
opn = "mtc0"; |
4142 | 4144 |
break; |
4145 |
#ifdef TARGET_MIPS64 |
|
4143 | 4146 |
case OPC_DMFC0: |
4144 | 4147 |
if (rt == 0) { |
4145 | 4148 |
/* Treat as NOP */ |
... | ... | |
4154 | 4157 |
gen_dmtc0(ctx, rd, ctx->opcode & 0x7); |
4155 | 4158 |
opn = "dmtc0"; |
4156 | 4159 |
break; |
4160 |
#endif |
|
4157 | 4161 |
#if defined(MIPS_USES_R4K_TLB) |
4158 | 4162 |
case OPC_TLBWI: |
4159 | 4163 |
gen_op_tlbwi(); |
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