/ - Diff - qemu - Greek Research and Technology Network's projects

b/Makefile.objs
146	146	hw-obj-$(CONFIG_USB_UHCI) += usb-uhci.o
147	147	hw-obj-$(CONFIG_USB_OHCI) += usb-ohci.o
148	148	hw-obj-$(CONFIG_FDC) += fdc.o
	149	hw-obj-$(CONFIG_ACPI) += acpi.o
149	150
150	151	# PCI watchdog devices
151	152	hw-obj-y += wdt_i6300esb.o

     obj-i386-y = pckbd.o dma.o
     obj-i386-y += vga.o
     obj-i386-y += mc146818rtc.o i8259.o pc.o
     obj-i386-y += cirrus_vga.o apic.o ioapic.o acpi.o piix_pci.o
     obj-i386-y += cirrus_vga.o apic.o ioapic.o piix_pci.o
     obj-i386-y += vmmouse.o vmport.o hpet.o
     obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
     obj-i386-y += debugcon.o multiboot.o
-...
     obj-mips-y += mips_addr.o mips_timer.o mips_int.o
     obj-mips-y += dma.o vga.o i8259.o
     obj-mips-y += g364fb.o jazz_led.o
     obj-mips-y += gt64xxx.o pckbd.o mc146818rtc.o acpi.o
     obj-mips-y += gt64xxx.o pckbd.o mc146818rtc.o
     obj-mips-y += piix4.o cirrus_vga.o
     obj-mips-y += pflash_cfi01.o

b/default-configs/i386-softmmu.mak
10	10	CONFIG_PCSPK=y
11	11	CONFIG_USB_UHCI=y
12	12	CONFIG_FDC=y
	13	CONFIG_ACPI=y
13	14	CONFIG_IDE_CORE=y
14	15	CONFIG_IDE_QDEV=y
15	16	CONFIG_IDE_PCI=y

b/default-configs/mips-softmmu.mak
12	12	CONFIG_PCSPK=y
13	13	CONFIG_USB_UHCI=y
14	14	CONFIG_FDC=y
	15	CONFIG_ACPI=y
15	16	CONFIG_IDE_CORE=y
16	17	CONFIG_IDE_QDEV=y
17	18	CONFIG_IDE_PCI=y

b/default-configs/mips64-softmmu.mak
12	12	CONFIG_PCSPK=y
13	13	CONFIG_USB_UHCI=y
14	14	CONFIG_FDC=y
	15	CONFIG_ACPI=y
15	16	CONFIG_IDE_CORE=y
16	17	CONFIG_IDE_QDEV=y
17	18	CONFIG_IDE_PCI=y

b/default-configs/mips64el-softmmu.mak
12	12	CONFIG_PCSPK=y
13	13	CONFIG_USB_UHCI=y
14	14	CONFIG_FDC=y
	15	CONFIG_ACPI=y
15	16	CONFIG_IDE_CORE=y
16	17	CONFIG_IDE_QDEV=y
17	18	CONFIG_IDE_PCI=y

b/default-configs/mipsel-softmmu.mak
12	12	CONFIG_PCSPK=y
13	13	CONFIG_USB_UHCI=y
14	14	CONFIG_FDC=y
	15	CONFIG_ACPI=y
15	16	CONFIG_IDE_CORE=y
16	17	CONFIG_IDE_QDEV=y
17	18	CONFIG_IDE_PCI=y

b/default-configs/x86_64-softmmu.mak
10	10	CONFIG_PCSPK=y
11	11	CONFIG_USB_UHCI=y
12	12	CONFIG_FDC=y
	13	CONFIG_ACPI=y
13	14	CONFIG_IDE_CORE=y
14	15	CONFIG_IDE_QDEV=y
15	16	CONFIG_IDE_PCI=y

     #include "sysemu.h"
     #include "i2c.h"
     #include "smbus.h"
     #include "kvm.h"
     //#define DEBUG
-...
         uint8_t smb_data[32];
         uint8_t smb_index;
         qemu_irq irq;
         qemu_irq cmos_s3;
         qemu_irq smi_irq;
         int kvm_enabled;
     } PIIX4PMState;
     #define RSM_STS (1 << 15)
-...
                            was caused by power button */
                         s->pmsts |= (RSM_STS | PWRBTN_STS);
                         qemu_system_reset_request();
     #if defined(TARGET_I386)
                         cmos_set_s3_resume();
     #endif
                         if (s->cmos_s3) {
                             qemu_irq_raise(s->cmos_s3);
+                        }
                     default:
                         break;
+                    }
-...
+            }
             if (s->dev.config[0x5b] & (1 << 1)) {
                 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
                 if (s->smi_irq) {
                     qemu_irq_raise(s->smi_irq);
+                }
+            }
         } else {
             s->apms = val;
-...
         pci_conf[0x5a] = 0;
         pci_conf[0x5b] = 0;
         if (kvm_enabled()) {
         if (s->kvm_enabled) {
             /* Mark SMM as already inited (until KVM supports SMM). */
             pci_conf[0x5B] = 0x02;
+        }
-...
     static void piix4_powerdown(void *opaque, int irq, int power_failing)
+    {
     #if defined(TARGET_I386)
         PIIX4PMState *s = opaque;
         if (!s) {
-...
             s->pmsts |= PWRBTN_EN;
             pm_update_sci(s);
+        }
     #endif
+    }
     i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                            qemu_irq sci_irq)
                            qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
                            int kvm_enabled)
+    {
         PIIX4PMState *s;
         uint8_t *pci_conf;
-...
         register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
         if (kvm_enabled()) {
         if (kvm_enabled) {
             /* Mark SMM as already inited to prevent SMM from running.  KVM does not
              * support SMM mode. */
             pci_conf[0x5B] = 0x02;
-...
         s->smbus = i2c_init_bus(NULL, "i2c");
         s->irq = sci_irq;
         s->cmos_s3 = cmos_s3;
         s->smi_irq = smi_irq;
         qemu_register_reset(piix4_reset, s);
         return s->smbus;

         isa_bus_irqs(i8259);
         pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
         usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
         smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_reserve_irq(9));
         smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_reserve_irq(9),
                               NULL, NULL, 0);
         eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
         for (i = 0; i < 8; i++) {
             /* TODO: Populate SPD eeprom data.  */

     #include "loader.h"
     #include "elf.h"
     #include "multiboot.h"
     #include "kvm.h"
     /* output Bochs bios info messages */
     //#define DEBUG_BIOS
-...
         return env->cpu_index == 0;
+    }
     /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
        BIOS will read it and start S3 resume at POST Entry */
     static void cmos_set_s3_resume(void *opaque, int irq, int level)
+    {
         RTCState *s = opaque;
         if (level) {
             rtc_set_memory(s, 0xF, 0xFE);
+        }
+    }
     static void acpi_smi_interrupt(void *opaque, int irq, int level)
+    {
         CPUState *s = opaque;
         if (level) {
             cpu_interrupt(s, CPU_INTERRUPT_SMI);
+        }
+    }
     static CPUState *pc_new_cpu(const char *cpu_model)
+    {
         CPUState *env;
-...
         qemu_irq *cpu_irq;
         qemu_irq *isa_irq;
         qemu_irq *i8259;
         qemu_irq *cmos_s3;
         qemu_irq *smi_irq;
         IsaIrqState *isa_irq_state;
         DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
         DriveInfo *fd[MAX_FD];
-...
             uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
             i2c_bus *smbus;
             cmos_s3 = qemu_allocate_irqs(cmos_set_s3_resume, rtc_state, 1);
             smi_irq = qemu_allocate_irqs(acpi_smi_interrupt, first_cpu, 1);
             /* TODO: Populate SPD eeprom data.  */
             smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
                                   isa_reserve_irq(9));
                                   isa_reserve_irq(9), *cmos_s3, *smi_irq,
                                   kvm_enabled());
             for (i = 0; i < 8; i++) {
                 DeviceState *eeprom;
                 eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
-...
                  initrd_filename, cpu_model, 0);
+    }
     /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
        BIOS will read it and start S3 resume at POST Entry */
     void cmos_set_s3_resume(void)
+    {
         if (rtc_state)
             rtc_set_memory(rtc_state, 0xF, 0xFE);
+    }
     static QEMUMachine pc_machine = {
         .name = "pc-0.13",
         .alias = "pc",

     RTCState *rtc_init(int base_year);
     void rtc_set_memory(RTCState *s, int addr, int val);
     void rtc_set_date(RTCState *s, const struct tm *tm);
     void cmos_set_s3_resume(void);
     /* pc.c */
     extern int fd_bootchk;
-...
     int acpi_table_add(const char *table_desc);
     /* acpi_piix.c */
     i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                            qemu_irq sci_irq);
                            qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
                            int kvm_enabled);
     void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
     void piix4_acpi_system_hot_add_init(PCIBus *bus);

Archipelago » qemu

Revision 53b67b30