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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%g0",
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    "%g1",
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    "%g2",
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    "%g3",
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    "%g4",
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    "%g5",
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    "%g6",
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    "%g7",
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    "%o0",
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    "%o1",
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    "%o2",
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    "%o3",
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    "%o4",
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    "%o5",
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    "%o6",
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    "%o7",
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    "%l0",
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    "%l1",
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    "%l2",
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    "%l3",
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    "%l4",
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    "%l5",
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    "%l6",
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    "%l7",
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    "%i0",
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    "%i1",
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    "%i2",
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    "%i3",
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    "%i4",
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    "%i5",
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    "%i6",
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    "%i7",
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};
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static const int tcg_target_reg_alloc_order[] = {
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    TCG_REG_L0,
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    TCG_REG_L1,
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    TCG_REG_L2,
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    TCG_REG_L3,
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    TCG_REG_L4,
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    TCG_REG_L5,
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    TCG_REG_L6,
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    TCG_REG_L7,
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    TCG_REG_I0,
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    TCG_REG_I1,
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    TCG_REG_I2,
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    TCG_REG_I3,
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    TCG_REG_I4,
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};
75

    
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static const int tcg_target_call_iarg_regs[6] = {
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    TCG_REG_O0,
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    TCG_REG_O1,
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    TCG_REG_O2,
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    TCG_REG_O3,
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    TCG_REG_O4,
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    TCG_REG_O5,
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};
84

    
85
static const int tcg_target_call_oarg_regs[2] = {
86
    TCG_REG_O0,
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    TCG_REG_O1,
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};
89

    
90
static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
91
{
92
    return (val << ((sizeof(tcg_target_long) * 8 - bits))
93
            >> (sizeof(tcg_target_long) * 8 - bits)) == val;
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}
95

    
96
static inline int check_fit_i32(uint32_t val, unsigned int bits)
97
{
98
    return ((val << (32 - bits)) >> (32 - bits)) == val;
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}
100

    
101
static void patch_reloc(uint8_t *code_ptr, int type,
102
                        tcg_target_long value, tcg_target_long addend)
103
{
104
    value += addend;
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    switch (type) {
106
    case R_SPARC_32:
107
        if (value != (uint32_t)value)
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            tcg_abort();
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        *(uint32_t *)code_ptr = value;
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        break;
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    case R_SPARC_WDISP22:
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        value -= (long)code_ptr;
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        value >>= 2;
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        if (!check_fit_tl(value, 22))
115
            tcg_abort();
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        *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
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        break;
118
    default:
119
        tcg_abort();
120
    }
121
}
122

    
123
/* maximum number of register used for input function arguments */
124
static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
126
    return 6;
127
}
128

    
129
/* parse target specific constraints */
130
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
131
{
132
    const char *ct_str;
133

    
134
    ct_str = *pct_str;
135
    switch (ct_str[0]) {
136
    case 'r':
137
    case 'L': /* qemu_ld/st constraint */
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
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        // Helper args
141
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
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        // Internal use
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
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        break;
148
    case 'I':
149
        ct->ct |= TCG_CT_CONST_S11;
150
        break;
151
    case 'J':
152
        ct->ct |= TCG_CT_CONST_S13;
153
        break;
154
    default:
155
        return -1;
156
    }
157
    ct_str++;
158
    *pct_str = ct_str;
159
    return 0;
160
}
161

    
162
/* test if a constant matches the constraint */
163
static inline int tcg_target_const_match(tcg_target_long val,
164
                                         const TCGArgConstraint *arg_ct)
165
{
166
    int ct;
167

    
168
    ct = arg_ct->ct;
169
    if (ct & TCG_CT_CONST)
170
        return 1;
171
    else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
172
        return 1;
173
    else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
174
        return 1;
175
    else
176
        return 0;
177
}
178

    
179
#define INSN_OP(x)  ((x) << 30)
180
#define INSN_OP2(x) ((x) << 22)
181
#define INSN_OP3(x) ((x) << 19)
182
#define INSN_OPF(x) ((x) << 5)
183
#define INSN_RD(x)  ((x) << 25)
184
#define INSN_RS1(x) ((x) << 14)
185
#define INSN_RS2(x) (x)
186
#define INSN_ASI(x) ((x) << 5)
187

    
188
#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
189
#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
190

    
191
#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
192
#define COND_N     0x0
193
#define COND_E     0x1
194
#define COND_LE    0x2
195
#define COND_L     0x3
196
#define COND_LEU   0x4
197
#define COND_CS    0x5
198
#define COND_NEG   0x6
199
#define COND_VS    0x7
200
#define COND_A     0x8
201
#define COND_NE    0x9
202
#define COND_G     0xa
203
#define COND_GE    0xb
204
#define COND_GU    0xc
205
#define COND_CC    0xd
206
#define COND_POS   0xe
207
#define COND_VC    0xf
208
#define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
209

    
210
#define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
211
#define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
212
#define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
213
#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
214
#define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
215
#define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
216
#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
217
#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
218
#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
219
#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
220
#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
221
#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
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#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
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#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
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#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
225

    
226
#define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
227
#define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
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#define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
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230
#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
231
#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
232
#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
233

    
234
#define WRY        (INSN_OP(2) | INSN_OP3(0x30))
235
#define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
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#define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
237
#define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
238
#define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
239
#define CALL       INSN_OP(1)
240
#define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
241
#define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
242
#define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
243
#define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
244
#define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
245
#define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
246
#define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
247
#define STB        (INSN_OP(3) | INSN_OP3(0x05))
248
#define STH        (INSN_OP(3) | INSN_OP3(0x06))
249
#define STW        (INSN_OP(3) | INSN_OP3(0x04))
250
#define STX        (INSN_OP(3) | INSN_OP3(0x0e))
251
#define LDUBA      (INSN_OP(3) | INSN_OP3(0x11))
252
#define LDSBA      (INSN_OP(3) | INSN_OP3(0x19))
253
#define LDUHA      (INSN_OP(3) | INSN_OP3(0x12))
254
#define LDSHA      (INSN_OP(3) | INSN_OP3(0x1a))
255
#define LDUWA      (INSN_OP(3) | INSN_OP3(0x10))
256
#define LDSWA      (INSN_OP(3) | INSN_OP3(0x18))
257
#define LDXA       (INSN_OP(3) | INSN_OP3(0x1b))
258
#define STBA       (INSN_OP(3) | INSN_OP3(0x15))
259
#define STHA       (INSN_OP(3) | INSN_OP3(0x16))
260
#define STWA       (INSN_OP(3) | INSN_OP3(0x14))
261
#define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
262

    
263
#ifndef ASI_PRIMARY_LITTLE
264
#define ASI_PRIMARY_LITTLE 0x88
265
#endif
266

    
267
static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
268
                                 int op)
269
{
270
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
271
              INSN_RS2(rs2));
272
}
273

    
274
static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset,
275
                                  int op)
276
{
277
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
278
              INSN_IMM13(offset));
279
}
280

    
281
static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
282
{
283
    tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
284
}
285

    
286
static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
287
{
288
    tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
289
}
290

    
291
static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
292
{
293
    tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
294
}
295

    
296
static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
297
{
298
    if (check_fit_i32(arg, 12))
299
        tcg_out_movi_imm13(s, ret, arg);
300
    else {
301
        tcg_out_sethi(s, ret, arg);
302
        if (arg & 0x3ff)
303
            tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
304
    }
305
}
306

    
307
static inline void tcg_out_movi(TCGContext *s, TCGType type,
308
                                int ret, tcg_target_long arg)
309
{
310
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
311
    if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) {
312
        tcg_out_movi_imm32(s, TCG_REG_I4, arg >> 32);
313
        tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
314
        tcg_out_movi_imm32(s, ret, arg);
315
        tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
316
    } else
317
#endif
318
        tcg_out_movi_imm32(s, ret, arg);
319
}
320

    
321
static inline void tcg_out_ld_raw(TCGContext *s, int ret,
322
                                  tcg_target_long arg)
323
{
324
    tcg_out_sethi(s, ret, arg);
325
    tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
326
              INSN_IMM13(arg & 0x3ff));
327
}
328

    
329
static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
330
                                  tcg_target_long arg)
331
{
332
    if (!check_fit_tl(arg, 10))
333
        tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
334
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
335
    tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
336
              INSN_IMM13(arg & 0x3ff));
337
#else
338
    tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
339
              INSN_IMM13(arg & 0x3ff));
340
#endif
341
}
342

    
343
static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
344
{
345
    if (check_fit_tl(offset, 13))
346
        tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
347
                  INSN_IMM13(offset));
348
    else {
349
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
350
        tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
351
                  INSN_RS2(addr));
352
    }
353
}
354

    
355
static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
356
                                    int offset, int op, int asi)
357
{
358
    tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
359
    tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
360
              INSN_ASI(asi) | INSN_RS2(addr));
361
}
362

    
363
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
364
                              int arg1, tcg_target_long arg2)
365
{
366
    if (type == TCG_TYPE_I32)
367
        tcg_out_ldst(s, ret, arg1, arg2, LDUW);
368
    else
369
        tcg_out_ldst(s, ret, arg1, arg2, LDX);
370
}
371

    
372
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
373
                              int arg1, tcg_target_long arg2)
374
{
375
    if (type == TCG_TYPE_I32)
376
        tcg_out_ldst(s, arg, arg1, arg2, STW);
377
    else
378
        tcg_out_ldst(s, arg, arg1, arg2, STX);
379
}
380

    
381
static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
382
{
383
    if (val == 0 || val == -1)
384
        tcg_out32(s, WRY | INSN_IMM13(val));
385
    else
386
        fprintf(stderr, "unimplemented sety %ld\n", (long)val);
387
}
388

    
389
static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
390
{
391
    if (val != 0) {
392
        if (check_fit_tl(val, 13))
393
            tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
394
        else {
395
            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
396
            tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
397
        }
398
    }
399
}
400

    
401
static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
402
{
403
    if (val != 0) {
404
        if (check_fit_tl(val, 13))
405
            tcg_out_arithi(s, reg, reg, val, ARITH_AND);
406
        else {
407
            tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
408
            tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
409
        }
410
    }
411
}
412

    
413
static inline void tcg_out_nop(TCGContext *s)
414
{
415
    tcg_out_sethi(s, TCG_REG_G0, 0);
416
}
417

    
418
static void tcg_out_branch(TCGContext *s, int opc, int label_index)
419
{
420
    int32_t val;
421
    TCGLabel *l = &s->labels[label_index];
422

    
423
    if (l->has_value) {
424
        val = l->u.value - (tcg_target_long)s->code_ptr;
425
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
426
                      | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
427
    } else {
428
        tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
429
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
430
    }
431
}
432

    
433
static const uint8_t tcg_cond_to_bcond[10] = {
434
    [TCG_COND_EQ] = COND_E,
435
    [TCG_COND_NE] = COND_NE,
436
    [TCG_COND_LT] = COND_L,
437
    [TCG_COND_GE] = COND_GE,
438
    [TCG_COND_LE] = COND_LE,
439
    [TCG_COND_GT] = COND_G,
440
    [TCG_COND_LTU] = COND_CS,
441
    [TCG_COND_GEU] = COND_CC,
442
    [TCG_COND_LEU] = COND_LEU,
443
    [TCG_COND_GTU] = COND_GU,
444
};
445

    
446
static void tcg_out_brcond(TCGContext *s, int cond,
447
                           TCGArg arg1, TCGArg arg2, int const_arg2,
448
                           int label_index)
449
{
450
    if (const_arg2 && arg2 == 0)
451
        /* orcc %g0, r, %g0 */
452
        tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC);
453
    else
454
        /* subcc r1, r2, %g0 */
455
        tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC);
456
    tcg_out_branch(s, tcg_cond_to_bcond[cond], label_index);
457
    tcg_out_nop(s);
458
}
459

    
460
/* Generate global QEMU prologue and epilogue code */
461
void tcg_target_qemu_prologue(TCGContext *s)
462
{
463
    tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
464
              INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
465
    tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
466
              INSN_RS2(TCG_REG_G0));
467
    tcg_out_nop(s);
468
}
469

    
470
#if defined(CONFIG_SOFTMMU)
471
extern void __ldb_mmu(void);
472
extern void __ldw_mmu(void);
473
extern void __ldl_mmu(void);
474
extern void __ldq_mmu(void);
475

    
476
extern void __stb_mmu(void);
477
extern void __stw_mmu(void);
478
extern void __stl_mmu(void);
479
extern void __stq_mmu(void);
480

    
481

    
482
static const void * const qemu_ld_helpers[4] = {
483
    __ldb_mmu,
484
    __ldw_mmu,
485
    __ldl_mmu,
486
    __ldq_mmu,
487
};
488

    
489
static const void * const qemu_st_helpers[4] = {
490
    __stb_mmu,
491
    __stw_mmu,
492
    __stl_mmu,
493
    __stq_mmu,
494
};
495
#endif
496

    
497
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
498
                            int opc)
499
{
500
    int addr_reg, data_reg, r0, r1, arg0, arg1, mem_index, s_bits;
501
    int target_ld_op, host_ld_op;
502
#if defined(CONFIG_SOFTMMU)
503
    uint32_t *label1_ptr, *label2_ptr;
504
#endif
505

    
506
    data_reg = *args++;
507
    addr_reg = *args++;
508
    mem_index = *args;
509
    s_bits = opc & 3;
510

    
511
    r0 = TCG_REG_L0;
512
    r1 = TCG_REG_L1;
513
    arg0 = TCG_REG_O0;
514
    arg1 = TCG_REG_O1;
515

    
516
#if TARGET_LONG_BITS == 32
517
    target_ld_op = LDUW;
518
#else
519
    target_ld_op = LDX;
520
#endif
521

    
522
#ifdef __arch64__
523
    host_ld_op = LDX;
524
#else
525
    host_ld_op = LDUW;
526
#endif
527

    
528

    
529
#if defined(CONFIG_SOFTMMU)
530
    /* srl addr_reg, x, r1 */
531
    tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
532
                   SHIFT_SRL);
533
    /* and addr_reg, x, r0 */
534
    tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
535
                   ARITH_AND);
536

    
537
    /* and r1, x, r1 */
538
    tcg_out_andi(s, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
539

    
540
    /* add r1, x, r1 */
541
    tcg_out_addi(s, r1, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
542

    
543
    /* add env, r1, r1 */
544
    tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD);
545

    
546
    /* ld [r1], arg1 */
547
    tcg_out32(s, target_ld_op | INSN_RD(arg1) | INSN_RS1(r1) | INSN_RS2(TCG_REG_G0));
548

    
549
    /* subcc r0, arg1, %g0 */
550
    tcg_out_arith(s, TCG_REG_G0, r0, arg1, ARITH_SUBCC);
551

    
552
    /* will become:
553
       be label1 */
554
    label1_ptr = (uint32_t *)s->code_ptr;
555
    tcg_out32(s, 0);
556

    
557
    /* mov (delay slot) */
558
    tcg_out_mov(s, arg0, addr_reg);
559

    
560
    /* XXX: move that code at the end of the TB */
561
    /* qemu_ld_helper[s_bits](arg0, arg1) */
562
    tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
563
                           - (tcg_target_ulong)s->code_ptr) >> 2)
564
                         & 0x3fffffff));
565
    /* mov (delay slot) */
566
    tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
567

    
568
    /* data_reg = sign_extend(arg0) */
569
    switch(opc) {
570
    case 0 | 4:
571
        /* sll arg0, 24/56, data_reg */
572
        tcg_out_arithi(s, data_reg, arg0, sizeof(tcg_target_long) * 8 - 8,
573
                       SHIFT_SLL);
574
        /* sra data_reg, 24/56, data_reg */
575
        tcg_out_arithi(s, data_reg, data_reg, sizeof(tcg_target_long) * 8 - 8,
576
                       SHIFT_SRA);
577
        break;
578
    case 1 | 4:
579
        /* sll arg0, 16/48, data_reg */
580
        tcg_out_arithi(s, data_reg, arg0, sizeof(tcg_target_long) * 8 - 16,
581
                       SHIFT_SLL);
582
        /* sra data_reg, 16/48, data_reg */
583
        tcg_out_arithi(s, data_reg, data_reg, sizeof(tcg_target_long) * 8 - 16,
584
                       SHIFT_SRA);
585
        break;
586
    case 2 | 4:
587
        /* sll arg0, 32, data_reg */
588
        tcg_out_arithi(s, data_reg, arg0, 32, SHIFT_SLL);
589
        /* sra data_reg, 32, data_reg */
590
        tcg_out_arithi(s, data_reg, data_reg, 32, SHIFT_SRA);
591
        break;
592
    case 0:
593
    case 1:
594
    case 2:
595
    case 3:
596
    default:
597
        /* mov */
598
        tcg_out_mov(s, data_reg, arg0);
599
        break;
600
    }
601

    
602
    /* will become:
603
       ba label2 */
604
    label2_ptr = (uint32_t *)s->code_ptr;
605
    tcg_out32(s, 0);
606

    
607
    /* nop (delay slot */
608
    tcg_out_nop(s);
609

    
610
    /* label1: */
611
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
612
                   INSN_OFF22((unsigned long)s->code_ptr -
613
                              (unsigned long)label1_ptr));
614

    
615
    /* ld [r1 + x], r1 */
616
    tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) -
617
                 offsetof(CPUTLBEntry, addr_read), host_ld_op);
618
    /* add r0, r1, r0 */
619
    tcg_out_arith(s, r0, r1, r0, ARITH_ADD);
620
#else
621
    r0 = addr_reg;
622
#endif
623

    
624
    switch(opc) {
625
    case 0:
626
        /* ldub [r0], data_reg */
627
        tcg_out_ldst(s, data_reg, r0, 0, LDUB);
628
        break;
629
    case 0 | 4:
630
        /* ldsb [r0], data_reg */
631
        tcg_out_ldst(s, data_reg, r0, 0, LDSB);
632
        break;
633
    case 1:
634
#ifdef TARGET_WORDS_BIGENDIAN
635
        /* lduh [r0], data_reg */
636
        tcg_out_ldst(s, data_reg, r0, 0, LDUH);
637
#else
638
        /* lduha [r0] ASI_PRIMARY_LITTLE, data_reg */
639
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDUHA, ASI_PRIMARY_LITTLE);
640
#endif
641
        break;
642
    case 1 | 4:
643
#ifdef TARGET_WORDS_BIGENDIAN
644
        /* ldsh [r0], data_reg */
645
        tcg_out_ldst(s, data_reg, r0, 0, LDSH);
646
#else
647
        /* ldsha [r0] ASI_PRIMARY_LITTLE, data_reg */
648
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDSHA, ASI_PRIMARY_LITTLE);
649
#endif
650
        break;
651
    case 2:
652
#ifdef TARGET_WORDS_BIGENDIAN
653
        /* lduw [r0], data_reg */
654
        tcg_out_ldst(s, data_reg, r0, 0, LDUW);
655
#else
656
        /* lduwa [r0] ASI_PRIMARY_LITTLE, data_reg */
657
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDUWA, ASI_PRIMARY_LITTLE);
658
#endif
659
        break;
660
    case 2 | 4:
661
#ifdef TARGET_WORDS_BIGENDIAN
662
        /* ldsw [r0], data_reg */
663
        tcg_out_ldst(s, data_reg, r0, 0, LDSW);
664
#else
665
        /* ldswa [r0] ASI_PRIMARY_LITTLE, data_reg */
666
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDSWA, ASI_PRIMARY_LITTLE);
667
#endif
668
        break;
669
    case 3:
670
#ifdef TARGET_WORDS_BIGENDIAN
671
        /* ldx [r0], data_reg */
672
        tcg_out_ldst(s, data_reg, r0, 0, LDX);
673
#else
674
        /* ldxa [r0] ASI_PRIMARY_LITTLE, data_reg */
675
        tcg_out_ldst_asi(s, data_reg, r0, 0, LDXA, ASI_PRIMARY_LITTLE);
676
#endif
677
        break;
678
    default:
679
        tcg_abort();
680
    }
681

    
682
#if defined(CONFIG_SOFTMMU)
683
    /* label2: */
684
    *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
685
                   INSN_OFF22((unsigned long)s->code_ptr -
686
                              (unsigned long)label2_ptr));
687
#endif
688
}
689

    
690
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
691
                            int opc)
692
{
693
    int addr_reg, data_reg, r0, r1, arg0, arg1, arg2, mem_index, s_bits;
694
    int target_ld_op, host_ld_op;
695
#if defined(CONFIG_SOFTMMU)
696
    uint32_t *label1_ptr, *label2_ptr;
697
#endif
698

    
699
    data_reg = *args++;
700
    addr_reg = *args++;
701
    mem_index = *args;
702

    
703
    s_bits = opc;
704

    
705
    r0 = TCG_REG_L0;
706
    r1 = TCG_REG_L1;
707
    arg0 = TCG_REG_O0;
708
    arg1 = TCG_REG_O1;
709
    arg2 = TCG_REG_O2;
710

    
711
#if TARGET_LONG_BITS == 32
712
    target_ld_op = LDUW;
713
#else
714
    target_ld_op = LDX;
715
#endif
716

    
717
#ifdef __arch64__
718
    host_ld_op = LDX;
719
#else
720
    host_ld_op = LDUW;
721
#endif
722

    
723
#if defined(CONFIG_SOFTMMU)
724
    /* srl addr_reg, x, r1 */
725
    tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
726
                   SHIFT_SRL);
727

    
728
    /* and addr_reg, x, r0 */
729
    tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
730
                   ARITH_AND);
731

    
732
    /* and r1, x, r1 */
733
    tcg_out_andi(s, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
734

    
735
    /* add r1, x, r1 */
736
    tcg_out_addi(s, r1, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
737

    
738
    /* add env, r1, r1 */
739
    tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD);
740

    
741
    /* ld [r1], arg1 */
742
    tcg_out32(s, target_ld_op | INSN_RD(arg1) | INSN_RS1(r1) | INSN_RS2(TCG_REG_G0));
743

    
744
    /* subcc r0, arg1, %g0 */
745
    tcg_out_arith(s, TCG_REG_G0, r0, arg1, ARITH_SUBCC);
746

    
747
    /* will become:
748
       be label1 */
749
    label1_ptr = (uint32_t *)s->code_ptr;
750
    tcg_out32(s, 0);
751

    
752
    /* mov (delay slot) */
753
    tcg_out_mov(s, arg0, addr_reg);
754

    
755
    /* arg1 = sign_extend(data_reg); */
756
    switch(opc) {
757
    case 0 | 4:
758
        /* sll data_reg, 24/56, arg1 */
759
        tcg_out_arithi(s, arg1, data_reg, sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL);
760
        /* sra arg1, 24/56, arg1 */
761
        tcg_out_arithi(s, arg1, arg1, sizeof(tcg_target_long) * 8 - 8,
762
                       SHIFT_SRA);
763
        break;
764
    case 1 | 4:
765
        /* sll data_reg, 16/48, arg1 */
766
        tcg_out_arithi(s, data_reg, arg1, sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL);
767
        /* sra arg1, 16/48, arg1 */
768
        tcg_out_arithi(s, arg1, arg1, sizeof(tcg_target_long) * 8 - 16,
769
                       SHIFT_SRA);
770
        break;
771
    case 2 | 4:
772
        /* sll data_reg, 32, arg1 */
773
        tcg_out_arithi(s, data_reg, arg1, 32, SHIFT_SLL);
774
        /* sra arg1, 32, arg1 */
775
        tcg_out_arithi(s, arg1, arg1, 32, SHIFT_SRA);
776
        break;
777
    case 0:
778
    case 1:
779
    case 2:
780
    case 3:
781
    default:
782
        /* mov */
783
        tcg_out_mov(s, arg1, data_reg);
784
        break;
785
    }
786

    
787
    /* mov */
788
    tcg_out_mov(s, arg0, addr_reg);
789

    
790
    /* XXX: move that code at the end of the TB */
791
    /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
792
    tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
793
                           - (tcg_target_ulong)s->code_ptr) >> 2)
794
                         & 0x3fffffff));
795
    /* mov (delay slot) */
796
    tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
797

    
798
    /* will become:
799
       ba label2 */
800
    label2_ptr = (uint32_t *)s->code_ptr;
801
    tcg_out32(s, 0);
802

    
803
    /* nop (delay slot) */
804
    tcg_out_nop(s);
805

    
806
    /* label1: */
807
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
808
                   INSN_OFF22((unsigned long)s->code_ptr -
809
                              (unsigned long)label1_ptr));
810

    
811
    /* ld [r1 + x], r1 */
812
    tcg_out_ldst(s, arg1, r1, offsetof(CPUTLBEntry, addend) -
813
                 offsetof(CPUTLBEntry, addr_write), host_ld_op);
814

    
815
    /* add r0, r1, r0 */
816
    tcg_out_arith(s, r0, arg1, r0, ARITH_ADD);
817
#else
818
    r0 = addr_reg;
819
#endif
820

    
821
    switch(opc) {
822
    case 0:
823
        /* stb data_reg, [r0] */
824
        tcg_out_ldst(s, data_reg, r0, 0, STB);
825
        break;
826
    case 1:
827
#ifdef TARGET_WORDS_BIGENDIAN
828
        /* sth data_reg, [r0] */
829
        tcg_out_ldst(s, data_reg, r0, 0, STH);
830
#else
831
        /* stha data_reg, [r0] ASI_PRIMARY_LITTLE */
832
        tcg_out_ldst_asi(s, data_reg, r0, 0, STHA, ASI_PRIMARY_LITTLE);
833
#endif
834
        break;
835
    case 2:
836
#ifdef TARGET_WORDS_BIGENDIAN
837
        /* stw data_reg, [r0] */
838
        tcg_out_ldst(s, data_reg, r0, 0, STW);
839
#else
840
        /* stwa data_reg, [r0] ASI_PRIMARY_LITTLE */
841
        tcg_out_ldst_asi(s, data_reg, r0, 0, STWA, ASI_PRIMARY_LITTLE);
842
#endif
843
        break;
844
    case 3:
845
#ifdef TARGET_WORDS_BIGENDIAN
846
        /* stx data_reg, [r0] */
847
        tcg_out_ldst(s, data_reg, r0, 0, STX);
848
#else
849
        /* stxa data_reg, [r0] ASI_PRIMARY_LITTLE */
850
        tcg_out_ldst_asi(s, data_reg, r0, 0, STXA, ASI_PRIMARY_LITTLE);
851
#endif
852
        break;
853
    default:
854
        tcg_abort();
855
    }
856

    
857
#if defined(CONFIG_SOFTMMU)
858
    /* label2: */
859
    *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
860
                   INSN_OFF22((unsigned long)s->code_ptr -
861
                              (unsigned long)label2_ptr));
862
#endif
863
}
864

    
865
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
866
                              const int *const_args)
867
{
868
    int c;
869

    
870
    switch (opc) {
871
    case INDEX_op_exit_tb:
872
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
873
        tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
874
                  INSN_IMM13(8));
875
        tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
876
                      INSN_RS2(TCG_REG_G0));
877
        break;
878
    case INDEX_op_goto_tb:
879
        if (s->tb_jmp_offset) {
880
            /* direct jump method */
881
            tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
882
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
883
                      INSN_IMM13((args[0] & 0x1fff)));
884
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
885
        } else {
886
            /* indirect jump method */
887
            tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
888
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
889
                      INSN_RS2(TCG_REG_G0));
890
        }
891
        tcg_out_nop(s);
892
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
893
        break;
894
    case INDEX_op_call:
895
        {
896
            unsigned int st_op, ld_op;
897

    
898
#ifdef __arch64__
899
            st_op = STX;
900
            ld_op = LDX;
901
#else
902
            st_op = STW;
903
            ld_op = LDUW;
904
#endif
905
            if (const_args[0])
906
                tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
907
                                       - (tcg_target_ulong)s->code_ptr) >> 2)
908
                                     & 0x3fffffff));
909
            else {
910
                tcg_out_ld_ptr(s, TCG_REG_I5,
911
                               (tcg_target_long)(s->tb_next + args[0]));
912
                tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
913
                          INSN_RS2(TCG_REG_G0));
914
            }
915
            /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
916
               global registers */
917
            tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
918
                         TCG_TARGET_CALL_STACK_OFFSET - sizeof(long),
919
                         st_op); // delay slot
920
            tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
921
                         TCG_TARGET_CALL_STACK_OFFSET - sizeof(long),
922
                         ld_op);
923
        }
924
        break;
925
    case INDEX_op_jmp:
926
    case INDEX_op_br:
927
        tcg_out_branch(s, COND_A, args[0]);
928
        tcg_out_nop(s);
929
        break;
930
    case INDEX_op_movi_i32:
931
        tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
932
        break;
933

    
934
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
935
#define OP_32_64(x)                             \
936
        glue(glue(case INDEX_op_, x), _i32:)    \
937
        glue(glue(case INDEX_op_, x), _i64:)
938
#else
939
#define OP_32_64(x)                             \
940
        glue(glue(case INDEX_op_, x), _i32:)
941
#endif
942
        OP_32_64(ld8u);
943
        tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
944
        break;
945
        OP_32_64(ld8s);
946
        tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
947
        break;
948
        OP_32_64(ld16u);
949
        tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
950
        break;
951
        OP_32_64(ld16s);
952
        tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
953
        break;
954
    case INDEX_op_ld_i32:
955
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
956
    case INDEX_op_ld32u_i64:
957
#endif
958
        tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
959
        break;
960
        OP_32_64(st8);
961
        tcg_out_ldst(s, args[0], args[1], args[2], STB);
962
        break;
963
        OP_32_64(st16);
964
        tcg_out_ldst(s, args[0], args[1], args[2], STH);
965
        break;
966
    case INDEX_op_st_i32:
967
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
968
    case INDEX_op_st32_i64:
969
#endif
970
        tcg_out_ldst(s, args[0], args[1], args[2], STW);
971
        break;
972
        OP_32_64(add);
973
        c = ARITH_ADD;
974
        goto gen_arith32;
975
        OP_32_64(sub);
976
        c = ARITH_SUB;
977
        goto gen_arith32;
978
        OP_32_64(and);
979
        c = ARITH_AND;
980
        goto gen_arith32;
981
        OP_32_64(or);
982
        c = ARITH_OR;
983
        goto gen_arith32;
984
        OP_32_64(xor);
985
        c = ARITH_XOR;
986
        goto gen_arith32;
987
    case INDEX_op_shl_i32:
988
        c = SHIFT_SLL;
989
        goto gen_arith32;
990
    case INDEX_op_shr_i32:
991
        c = SHIFT_SRL;
992
        goto gen_arith32;
993
    case INDEX_op_sar_i32:
994
        c = SHIFT_SRA;
995
        goto gen_arith32;
996
    case INDEX_op_mul_i32:
997
        c = ARITH_UMUL;
998
        goto gen_arith32;
999
    case INDEX_op_div2_i32:
1000
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
1001
        c = ARITH_SDIVX;
1002
        goto gen_arith32;
1003
#else
1004
        tcg_out_sety(s, 0);
1005
        c = ARITH_SDIV;
1006
        goto gen_arith32;
1007
#endif
1008
    case INDEX_op_divu2_i32:
1009
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
1010
        c = ARITH_UDIVX;
1011
        goto gen_arith32;
1012
#else
1013
        tcg_out_sety(s, 0);
1014
        c = ARITH_UDIV;
1015
        goto gen_arith32;
1016
#endif
1017

    
1018
    case INDEX_op_brcond_i32:
1019
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1020
                       args[3]);
1021
        break;
1022

    
1023
    case INDEX_op_qemu_ld8u:
1024
        tcg_out_qemu_ld(s, args, 0);
1025
        break;
1026
    case INDEX_op_qemu_ld8s:
1027
        tcg_out_qemu_ld(s, args, 0 | 4);
1028
        break;
1029
    case INDEX_op_qemu_ld16u:
1030
        tcg_out_qemu_ld(s, args, 1);
1031
        break;
1032
    case INDEX_op_qemu_ld16s:
1033
        tcg_out_qemu_ld(s, args, 1 | 4);
1034
        break;
1035
    case INDEX_op_qemu_ld32u:
1036
        tcg_out_qemu_ld(s, args, 2);
1037
        break;
1038
    case INDEX_op_qemu_ld32s:
1039
        tcg_out_qemu_ld(s, args, 2 | 4);
1040
        break;
1041
    case INDEX_op_qemu_st8:
1042
        tcg_out_qemu_st(s, args, 0);
1043
        break;
1044
    case INDEX_op_qemu_st16:
1045
        tcg_out_qemu_st(s, args, 1);
1046
        break;
1047
    case INDEX_op_qemu_st32:
1048
        tcg_out_qemu_st(s, args, 2);
1049
        break;
1050

    
1051
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1052
    case INDEX_op_movi_i64:
1053
        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1054
        break;
1055
    case INDEX_op_ld32s_i64:
1056
        tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1057
        break;
1058
    case INDEX_op_ld_i64:
1059
        tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1060
        break;
1061
    case INDEX_op_st_i64:
1062
        tcg_out_ldst(s, args[0], args[1], args[2], STX);
1063
        break;
1064
    case INDEX_op_shl_i64:
1065
        c = SHIFT_SLLX;
1066
        goto gen_arith32;
1067
    case INDEX_op_shr_i64:
1068
        c = SHIFT_SRLX;
1069
        goto gen_arith32;
1070
    case INDEX_op_sar_i64:
1071
        c = SHIFT_SRAX;
1072
        goto gen_arith32;
1073
    case INDEX_op_mul_i64:
1074
        c = ARITH_MULX;
1075
        goto gen_arith32;
1076
    case INDEX_op_div2_i64:
1077
        c = ARITH_SDIVX;
1078
        goto gen_arith32;
1079
    case INDEX_op_divu2_i64:
1080
        c = ARITH_UDIVX;
1081
        goto gen_arith32;
1082

    
1083
    case INDEX_op_brcond_i64:
1084
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1085
                       args[3]);
1086
        break;
1087
    case INDEX_op_qemu_ld64:
1088
        tcg_out_qemu_ld(s, args, 3);
1089
        break;
1090
    case INDEX_op_qemu_st64:
1091
        tcg_out_qemu_st(s, args, 3);
1092
        break;
1093

    
1094
#endif
1095
    gen_arith32:
1096
        if (const_args[2]) {
1097
            tcg_out_arithi(s, args[0], args[1], args[2], c);
1098
        } else {
1099
            tcg_out_arith(s, args[0], args[1], args[2], c);
1100
        }
1101
        break;
1102

    
1103
    default:
1104
        fprintf(stderr, "unknown opcode 0x%x\n", opc);
1105
        tcg_abort();
1106
    }
1107
}
1108

    
1109
static const TCGTargetOpDef sparc_op_defs[] = {
1110
    { INDEX_op_exit_tb, { } },
1111
    { INDEX_op_goto_tb, { } },
1112
    { INDEX_op_call, { "ri" } },
1113
    { INDEX_op_jmp, { "ri" } },
1114
    { INDEX_op_br, { } },
1115

    
1116
    { INDEX_op_mov_i32, { "r", "r" } },
1117
    { INDEX_op_movi_i32, { "r" } },
1118
    { INDEX_op_ld8u_i32, { "r", "r" } },
1119
    { INDEX_op_ld8s_i32, { "r", "r" } },
1120
    { INDEX_op_ld16u_i32, { "r", "r" } },
1121
    { INDEX_op_ld16s_i32, { "r", "r" } },
1122
    { INDEX_op_ld_i32, { "r", "r" } },
1123
    { INDEX_op_st8_i32, { "r", "r" } },
1124
    { INDEX_op_st16_i32, { "r", "r" } },
1125
    { INDEX_op_st_i32, { "r", "r" } },
1126

    
1127
    { INDEX_op_add_i32, { "r", "r", "rJ" } },
1128
    { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1129
    { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
1130
    { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
1131
    { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1132
    { INDEX_op_and_i32, { "r", "r", "rJ" } },
1133
    { INDEX_op_or_i32, { "r", "r", "rJ" } },
1134
    { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1135

    
1136
    { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1137
    { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1138
    { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1139

    
1140
    { INDEX_op_brcond_i32, { "r", "ri" } },
1141

    
1142
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1143
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1144
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1145
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1146
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1147
    { INDEX_op_qemu_ld32s, { "r", "L" } },
1148

    
1149
    { INDEX_op_qemu_st8, { "L", "L" } },
1150
    { INDEX_op_qemu_st16, { "L", "L" } },
1151
    { INDEX_op_qemu_st32, { "L", "L" } },
1152

    
1153
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1154
    { INDEX_op_mov_i64, { "r", "r" } },
1155
    { INDEX_op_movi_i64, { "r" } },
1156
    { INDEX_op_ld8u_i64, { "r", "r" } },
1157
    { INDEX_op_ld8s_i64, { "r", "r" } },
1158
    { INDEX_op_ld16u_i64, { "r", "r" } },
1159
    { INDEX_op_ld16s_i64, { "r", "r" } },
1160
    { INDEX_op_ld32u_i64, { "r", "r" } },
1161
    { INDEX_op_ld32s_i64, { "r", "r" } },
1162
    { INDEX_op_ld_i64, { "r", "r" } },
1163
    { INDEX_op_st8_i64, { "r", "r" } },
1164
    { INDEX_op_st16_i64, { "r", "r" } },
1165
    { INDEX_op_st32_i64, { "r", "r" } },
1166
    { INDEX_op_st_i64, { "r", "r" } },
1167

    
1168
    { INDEX_op_add_i64, { "r", "r", "rJ" } },
1169
    { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1170
    { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
1171
    { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
1172
    { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1173
    { INDEX_op_and_i64, { "r", "r", "rJ" } },
1174
    { INDEX_op_or_i64, { "r", "r", "rJ" } },
1175
    { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1176

    
1177
    { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1178
    { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1179
    { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1180

    
1181
    { INDEX_op_brcond_i64, { "r", "ri" } },
1182
#endif
1183
    { -1 },
1184
};
1185

    
1186
void tcg_target_init(TCGContext *s)
1187
{
1188
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1189
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1190
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1191
#endif
1192
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1193
                     (1 << TCG_REG_G1) |
1194
                     (1 << TCG_REG_G2) |
1195
                     (1 << TCG_REG_G3) |
1196
                     (1 << TCG_REG_G4) |
1197
                     (1 << TCG_REG_G5) |
1198
                     (1 << TCG_REG_G6) |
1199
                     (1 << TCG_REG_G7) |
1200
                     (1 << TCG_REG_O0) |
1201
                     (1 << TCG_REG_O1) |
1202
                     (1 << TCG_REG_O2) |
1203
                     (1 << TCG_REG_O3) |
1204
                     (1 << TCG_REG_O4) |
1205
                     (1 << TCG_REG_O5) |
1206
                     (1 << TCG_REG_O7));
1207

    
1208
    tcg_regset_clear(s->reserved_regs);
1209
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1210
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1211
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1212
#endif
1213
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1214
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1215
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1216
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1217
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1218
    tcg_add_target_add_op_defs(sparc_op_defs);
1219
}