Revision 53cd9273
| b/tcg/sparc/tcg-target.c | ||
|---|---|---|
| 297 | 297 |
|
| 298 | 298 |
switch (opc) {
|
| 299 | 299 |
case INDEX_op_exit_tb: |
| 300 |
tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_O0, args[0]);
|
|
| 300 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_O0, args[0]);
|
|
| 301 | 301 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_O7) | |
| 302 | 302 |
INSN_IMM13(8)); |
| 303 | 303 |
tcg_out_nop(s); |
| ... | ... | |
| 305 | 305 |
case INDEX_op_goto_tb: |
| 306 | 306 |
if (s->tb_jmp_offset) {
|
| 307 | 307 |
/* direct jump method */ |
| 308 |
tcg_out32(s, CALL | 0);
|
|
| 308 |
tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_I5, args[0]);
|
|
| 309 | 309 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; |
| 310 |
tcg_out_nop(s); |
|
| 311 | 310 |
} else {
|
| 312 | 311 |
/* indirect jump method */ |
| 313 |
tcg_out_ld_raw(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0])); |
|
| 314 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_O7) | |
|
| 315 |
INSN_RS2(TCG_REG_G0)); |
|
| 316 |
tcg_out_nop(s); |
|
| 312 |
tcg_out_ld_raw(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0])); |
|
| 317 | 313 |
} |
| 314 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
|
| 315 |
INSN_RS2(TCG_REG_G0)); |
|
| 316 |
tcg_out_nop(s); |
|
| 318 | 317 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; |
| 319 | 318 |
break; |
| 320 | 319 |
case INDEX_op_call: |
| ... | ... | |
| 362 | 361 |
break; |
| 363 | 362 |
case INDEX_op_ld_i32: |
| 364 | 363 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) |
| 365 |
case INDEX_op_ld_i32u_i64:
|
|
| 364 |
case INDEX_op_ld32u_i64: |
|
| 366 | 365 |
#endif |
| 367 | 366 |
tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
| 368 | 367 |
break; |
| ... | ... | |
| 374 | 373 |
break; |
| 375 | 374 |
case INDEX_op_st_i32: |
| 376 | 375 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) |
| 377 |
case INDEX_op_st_i32_i64:
|
|
| 376 |
case INDEX_op_st32_i64: |
|
| 378 | 377 |
#endif |
| 379 | 378 |
tcg_out_ldst(s, args[0], args[1], args[2], STW); |
| 380 | 379 |
break; |
| 380 |
OP_32_64(add); |
|
| 381 |
c = ARITH_ADD; |
|
| 382 |
goto gen_arith32; |
|
| 381 | 383 |
OP_32_64(sub); |
| 382 | 384 |
c = ARITH_SUB; |
| 383 | 385 |
goto gen_arith32; |
| ... | ... | |
| 402 | 404 |
case INDEX_op_mul_i32: |
| 403 | 405 |
c = ARITH_UMUL; |
| 404 | 406 |
goto gen_arith32; |
| 405 |
OP_32_64(add); |
|
| 406 |
c = ARITH_ADD; |
|
| 407 |
gen_arith32: |
|
| 408 |
if (const_args[2]) {
|
|
| 409 |
tcg_out_arithi(s, args[0], args[1], args[2], c); |
|
| 410 |
} else {
|
|
| 411 |
tcg_out_arith(s, args[0], args[1], args[2], c); |
|
| 412 |
} |
|
| 413 |
break; |
|
| 414 |
|
|
| 415 | 407 |
case INDEX_op_div2_i32: |
| 416 | 408 |
#if defined(__sparc_v9__) || defined(__sparc_v8plus__) |
| 417 | 409 |
c = ARITH_SDIVX; |
| ... | ... | |
| 467 | 459 |
case INDEX_op_movi_i64: |
| 468 | 460 |
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
| 469 | 461 |
break; |
| 462 |
case INDEX_op_ld32s_i64: |
|
| 463 |
tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
|
| 464 |
break; |
|
| 470 | 465 |
case INDEX_op_ld_i64: |
| 471 | 466 |
tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
| 472 | 467 |
break; |
| ... | ... | |
| 486 | 481 |
c = ARITH_MULX; |
| 487 | 482 |
goto gen_arith32; |
| 488 | 483 |
case INDEX_op_div2_i64: |
| 489 |
c = ARITH_DIVX; |
|
| 484 |
c = ARITH_SDIVX;
|
|
| 490 | 485 |
goto gen_arith32; |
| 491 | 486 |
case INDEX_op_divu2_i64: |
| 492 | 487 |
c = ARITH_UDIVX; |
| ... | ... | |
| 503 | 498 |
break; |
| 504 | 499 |
|
| 505 | 500 |
#endif |
| 501 |
gen_arith32: |
|
| 502 |
if (const_args[2]) {
|
|
| 503 |
tcg_out_arithi(s, args[0], args[1], args[2], c); |
|
| 504 |
} else {
|
|
| 505 |
tcg_out_arith(s, args[0], args[1], args[2], c); |
|
| 506 |
} |
|
| 507 |
break; |
|
| 508 |
|
|
| 506 | 509 |
default: |
| 507 | 510 |
fprintf(stderr, "unknown opcode 0x%x\n", opc); |
| 508 | 511 |
tcg_abort(); |
| ... | ... | |
| 511 | 514 |
|
| 512 | 515 |
static const TCGTargetOpDef sparc_op_defs[] = {
|
| 513 | 516 |
{ INDEX_op_exit_tb, { } },
|
| 514 |
{ INDEX_op_goto_tb, { } },
|
|
| 517 |
{ INDEX_op_goto_tb, { "r" } },
|
|
| 515 | 518 |
{ INDEX_op_call, { "ri" } },
|
| 516 | 519 |
{ INDEX_op_jmp, { "ri" } },
|
| 517 | 520 |
{ INDEX_op_br, { } },
|
| ... | ... | |
| 527 | 530 |
{ INDEX_op_st16_i32, { "r", "r" } },
|
| 528 | 531 |
{ INDEX_op_st_i32, { "r", "r" } },
|
| 529 | 532 |
|
| 530 |
{ INDEX_op_add_i32, { "r", "0", "rJ" } },
|
|
| 531 |
{ INDEX_op_mul_i32, { "r", "0", "rJ" } },
|
|
| 533 |
{ INDEX_op_add_i32, { "r", "r", "rJ" } },
|
|
| 534 |
{ INDEX_op_mul_i32, { "r", "r", "rJ" } },
|
|
| 532 | 535 |
{ INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
|
| 533 | 536 |
{ INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
|
| 534 |
{ INDEX_op_sub_i32, { "r", "0", "rJ" } },
|
|
| 535 |
{ INDEX_op_and_i32, { "r", "0", "rJ" } },
|
|
| 536 |
{ INDEX_op_or_i32, { "r", "0", "rJ" } },
|
|
| 537 |
{ INDEX_op_xor_i32, { "r", "0", "rJ" } },
|
|
| 537 |
{ INDEX_op_sub_i32, { "r", "r", "rJ" } },
|
|
| 538 |
{ INDEX_op_and_i32, { "r", "r", "rJ" } },
|
|
| 539 |
{ INDEX_op_or_i32, { "r", "r", "rJ" } },
|
|
| 540 |
{ INDEX_op_xor_i32, { "r", "r", "rJ" } },
|
|
| 538 | 541 |
|
| 539 |
{ INDEX_op_shl_i32, { "r", "0", "rJ" } },
|
|
| 540 |
{ INDEX_op_shr_i32, { "r", "0", "rJ" } },
|
|
| 541 |
{ INDEX_op_sar_i32, { "r", "0", "rJ" } },
|
|
| 542 |
{ INDEX_op_shl_i32, { "r", "r", "rJ" } },
|
|
| 543 |
{ INDEX_op_shr_i32, { "r", "r", "rJ" } },
|
|
| 544 |
{ INDEX_op_sar_i32, { "r", "r", "rJ" } },
|
|
| 542 | 545 |
|
| 543 | 546 |
{ INDEX_op_brcond_i32, { "r", "ri" } },
|
| 544 | 547 |
|
| ... | ... | |
| 568 | 571 |
{ INDEX_op_st32_i64, { "r", "r" } },
|
| 569 | 572 |
{ INDEX_op_st_i64, { "r", "r" } },
|
| 570 | 573 |
|
| 571 |
{ INDEX_op_add_i64, { "r", "0", "rJ" } },
|
|
| 572 |
{ INDEX_op_mul_i64, { "r", "0", "rJ" } },
|
|
| 574 |
{ INDEX_op_add_i64, { "r", "r", "rJ" } },
|
|
| 575 |
{ INDEX_op_mul_i64, { "r", "r", "rJ" } },
|
|
| 573 | 576 |
{ INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
|
| 574 | 577 |
{ INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
|
| 575 |
{ INDEX_op_sub_i64, { "r", "0", "rJ" } },
|
|
| 576 |
{ INDEX_op_and_i64, { "r", "0", "rJ" } },
|
|
| 577 |
{ INDEX_op_or_i64, { "r", "0", "rJ" } },
|
|
| 578 |
{ INDEX_op_xor_i64, { "r", "0", "rJ" } },
|
|
| 578 |
{ INDEX_op_sub_i64, { "r", "r", "rJ" } },
|
|
| 579 |
{ INDEX_op_and_i64, { "r", "r", "rJ" } },
|
|
| 580 |
{ INDEX_op_or_i64, { "r", "r", "rJ" } },
|
|
| 581 |
{ INDEX_op_xor_i64, { "r", "r", "rJ" } },
|
|
| 579 | 582 |
|
| 580 |
{ INDEX_op_shl_i64, { "r", "0", "rJ" } },
|
|
| 581 |
{ INDEX_op_shr_i64, { "r", "0", "rJ" } },
|
|
| 582 |
{ INDEX_op_sar_i64, { "r", "0", "rJ" } },
|
|
| 583 |
{ INDEX_op_shl_i64, { "r", "r", "rJ" } },
|
|
| 584 |
{ INDEX_op_shr_i64, { "r", "r", "rJ" } },
|
|
| 585 |
{ INDEX_op_sar_i64, { "r", "r", "rJ" } },
|
|
| 583 | 586 |
|
| 584 | 587 |
{ INDEX_op_brcond_i64, { "r", "ri" } },
|
| 585 | 588 |
#endif |
| ... | ... | |
| 604 | 607 |
|
| 605 | 608 |
tcg_regset_clear(s->reserved_regs); |
| 606 | 609 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
| 610 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use |
|
| 607 | 611 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
| 608 | 612 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
| 609 | 613 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
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