root / tcg / sparc / tcg-target.c @ 53cd9273
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"%g0",
|
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"%g1",
|
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"%g2",
|
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"%g3",
|
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"%g4",
|
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"%g5",
|
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"%g6",
|
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"%g7",
|
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"%o0",
|
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"%o1",
|
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"%o2",
|
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"%o3",
|
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"%o4",
|
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"%o5",
|
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"%o6",
|
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"%o7",
|
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"%l0",
|
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"%l1",
|
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"%l2",
|
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"%l3",
|
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"%l4",
|
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"%l5",
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"%l6",
|
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"%l7",
|
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"%i0",
|
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"%i1",
|
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"%i2",
|
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"%i3",
|
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"%i4",
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"%i5",
|
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"%i6",
|
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"%i7",
|
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}; |
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|
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static const int tcg_target_reg_alloc_order[TCG_TARGET_NB_REGS] = { |
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TCG_REG_L0, |
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TCG_REG_L1, |
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TCG_REG_L2, |
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TCG_REG_L3, |
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TCG_REG_L4, |
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TCG_REG_L5, |
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TCG_REG_L6, |
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TCG_REG_L7, |
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TCG_REG_I0, |
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TCG_REG_I1, |
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TCG_REG_I2, |
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TCG_REG_I3, |
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TCG_REG_I4, |
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TCG_REG_I5, |
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}; |
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|
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static const int tcg_target_call_iarg_regs[6] = { |
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TCG_REG_O0, |
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TCG_REG_O1, |
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TCG_REG_O2, |
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TCG_REG_O3, |
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TCG_REG_O4, |
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TCG_REG_O5, |
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}; |
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|
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static const int tcg_target_call_oarg_regs[2] = { |
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TCG_REG_O0, |
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TCG_REG_O1, |
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}; |
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|
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static void patch_reloc(uint8_t *code_ptr, int type, |
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tcg_target_long value) |
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{
|
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switch (type) {
|
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case R_SPARC_32:
|
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if (value != (uint32_t)value)
|
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tcg_abort(); |
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*(uint32_t *)code_ptr = value; |
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break;
|
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default:
|
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tcg_abort(); |
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} |
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} |
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|
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/* maximum number of register used for input function arguments */
|
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static inline int tcg_target_get_call_iarg_regs_count(int flags) |
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{
|
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return 6; |
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} |
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|
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/* parse target specific constraints */
|
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
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{
|
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const char *ct_str; |
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|
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ct_str = *pct_str; |
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switch (ct_str[0]) { |
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case 'r': |
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case 'L': /* qemu_ld/st constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
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break;
|
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case 'I': |
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ct->ct |= TCG_CT_CONST_S11; |
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break;
|
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case 'J': |
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ct->ct |= TCG_CT_CONST_S13; |
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break;
|
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default:
|
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return -1; |
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} |
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ct_str++; |
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*pct_str = ct_str; |
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return 0; |
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} |
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|
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#define ABS(x) ((x) < 0? -(x) : (x)) |
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/* test if a constant matches the constraint */
|
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static inline int tcg_target_const_match(tcg_target_long val, |
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const TCGArgConstraint *arg_ct)
|
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{
|
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int ct;
|
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|
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ct = arg_ct->ct; |
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if (ct & TCG_CT_CONST)
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return 1; |
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else if ((ct & TCG_CT_CONST_S11) && ABS(val) == (ABS(val) & 0x3ff)) |
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return 1; |
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else if ((ct & TCG_CT_CONST_S13) && ABS(val) == (ABS(val) & 0xfff)) |
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return 1; |
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else
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return 0; |
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} |
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|
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#define INSN_OP(x) ((x) << 30) |
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#define INSN_OP2(x) ((x) << 22) |
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#define INSN_OP3(x) ((x) << 19) |
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#define INSN_OPF(x) ((x) << 5) |
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#define INSN_RD(x) ((x) << 25) |
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#define INSN_RS1(x) ((x) << 14) |
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#define INSN_RS2(x) (x)
|
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|
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#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
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|
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#define INSN_COND(x, a) (((x) << 25) | ((a) << 29) |
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|
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#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
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#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
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#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
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#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
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#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x08)) |
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#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10)) |
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#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
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#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
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#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
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#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
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#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
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#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
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#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
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|
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#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
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#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
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#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
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|
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#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
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#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
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#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
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|
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#define WRY (INSN_OP(2) | INSN_OP3(0x30)) |
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#define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
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#define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
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#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
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#define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
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#define CALL INSN_OP(1) |
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#define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
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#define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
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#define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
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#define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
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#define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
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#define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
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#define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
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#define STB (INSN_OP(3) | INSN_OP3(0x05)) |
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#define STH (INSN_OP(3) | INSN_OP3(0x06)) |
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#define STW (INSN_OP(3) | INSN_OP3(0x04)) |
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#define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
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|
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
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{
|
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tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(arg) | |
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INSN_RS2(TCG_REG_G0)); |
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} |
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|
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static inline void tcg_out_movi(TCGContext *s, TCGType type, |
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int ret, tcg_target_long arg)
|
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{
|
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if (arg == (arg & 0xfff)) |
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tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(TCG_REG_G0) | |
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INSN_IMM13(arg)); |
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else {
|
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tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
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if (arg & 0x3ff) |
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tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(ret) | |
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INSN_IMM13(arg & 0x3ff));
|
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} |
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} |
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|
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static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
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tcg_target_long arg) |
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{
|
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tcg_out32(s, SETHI | INSN_RD(ret) | (((uint32_t)arg & 0xfffffc00) >> 10)); |
| 231 |
tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
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INSN_IMM13(arg & 0x3ff));
|
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} |
| 234 |
|
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static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) |
| 236 |
{
|
| 237 |
if (offset == (offset & 0xfff)) |
| 238 |
tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
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INSN_IMM13(offset)); |
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else
|
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fprintf(stderr, "unimplemented %s with offset %d\n", __func__, offset);
|
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} |
| 243 |
|
| 244 |
static inline void tcg_out_ld(TCGContext *s, int ret, |
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int arg1, tcg_target_long arg2)
|
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{
|
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fprintf(stderr, "unimplemented %s\n", __func__);
|
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} |
| 249 |
|
| 250 |
static inline void tcg_out_st(TCGContext *s, int arg, |
| 251 |
int arg1, tcg_target_long arg2)
|
| 252 |
{
|
| 253 |
fprintf(stderr, "unimplemented %s\n", __func__);
|
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} |
| 255 |
|
| 256 |
static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
| 257 |
int op)
|
| 258 |
{
|
| 259 |
tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
| 260 |
INSN_RS2(rs2)); |
| 261 |
} |
| 262 |
|
| 263 |
static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset, |
| 264 |
int op)
|
| 265 |
{
|
| 266 |
tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
| 267 |
INSN_IMM13(offset)); |
| 268 |
} |
| 269 |
|
| 270 |
static inline void tcg_out_sety(TCGContext *s, tcg_target_long val) |
| 271 |
{
|
| 272 |
if (val == 0 || val == -1) |
| 273 |
tcg_out32(s, WRY | INSN_IMM13(val)); |
| 274 |
else
|
| 275 |
fprintf(stderr, "unimplemented sety %ld\n", (long)val); |
| 276 |
} |
| 277 |
|
| 278 |
static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
| 279 |
{
|
| 280 |
if (val != 0) { |
| 281 |
if (val == (val & 0xfff)) |
| 282 |
tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
| 283 |
else
|
| 284 |
fprintf(stderr, "unimplemented addi %ld\n", (long)val); |
| 285 |
} |
| 286 |
} |
| 287 |
|
| 288 |
static inline void tcg_out_nop(TCGContext *s) |
| 289 |
{
|
| 290 |
tcg_out32(s, SETHI | INSN_RD(TCG_REG_G0) | 0);
|
| 291 |
} |
| 292 |
|
| 293 |
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
| 294 |
const int *const_args) |
| 295 |
{
|
| 296 |
int c;
|
| 297 |
|
| 298 |
switch (opc) {
|
| 299 |
case INDEX_op_exit_tb:
|
| 300 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_O0, args[0]);
|
| 301 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_O7) | |
| 302 |
INSN_IMM13(8));
|
| 303 |
tcg_out_nop(s); |
| 304 |
break;
|
| 305 |
case INDEX_op_goto_tb:
|
| 306 |
if (s->tb_jmp_offset) {
|
| 307 |
/* direct jump method */
|
| 308 |
tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_I5, args[0]);
|
| 309 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
| 310 |
} else {
|
| 311 |
/* indirect jump method */
|
| 312 |
tcg_out_ld_raw(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
| 313 |
} |
| 314 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
| 315 |
INSN_RS2(TCG_REG_G0)); |
| 316 |
tcg_out_nop(s); |
| 317 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
| 318 |
break;
|
| 319 |
case INDEX_op_call:
|
| 320 |
if (const_args[0]) { |
| 321 |
tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
|
| 322 |
- (tcg_target_ulong)s->code_ptr) >> 2)
|
| 323 |
& 0x3fffffff));
|
| 324 |
tcg_out_nop(s); |
| 325 |
} else {
|
| 326 |
tcg_out_ld_raw(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0]));
|
| 327 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_O7) | |
| 328 |
INSN_RS2(TCG_REG_G0)); |
| 329 |
tcg_out_nop(s); |
| 330 |
} |
| 331 |
break;
|
| 332 |
case INDEX_op_jmp:
|
| 333 |
fprintf(stderr, "unimplemented jmp\n");
|
| 334 |
break;
|
| 335 |
case INDEX_op_br:
|
| 336 |
fprintf(stderr, "unimplemented br\n");
|
| 337 |
break;
|
| 338 |
case INDEX_op_movi_i32:
|
| 339 |
tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
| 340 |
break;
|
| 341 |
|
| 342 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 343 |
#define OP_32_64(x) \
|
| 344 |
glue(glue(case INDEX_op_, x), _i32:) \
|
| 345 |
glue(glue(case INDEX_op_, x), _i64:)
|
| 346 |
#else
|
| 347 |
#define OP_32_64(x) \
|
| 348 |
glue(glue(case INDEX_op_, x), _i32:)
|
| 349 |
#endif
|
| 350 |
OP_32_64(ld8u); |
| 351 |
tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
| 352 |
break;
|
| 353 |
OP_32_64(ld8s); |
| 354 |
tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
| 355 |
break;
|
| 356 |
OP_32_64(ld16u); |
| 357 |
tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
| 358 |
break;
|
| 359 |
OP_32_64(ld16s); |
| 360 |
tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
| 361 |
break;
|
| 362 |
case INDEX_op_ld_i32:
|
| 363 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 364 |
case INDEX_op_ld32u_i64:
|
| 365 |
#endif
|
| 366 |
tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
| 367 |
break;
|
| 368 |
OP_32_64(st8); |
| 369 |
tcg_out_ldst(s, args[0], args[1], args[2], STB); |
| 370 |
break;
|
| 371 |
OP_32_64(st16); |
| 372 |
tcg_out_ldst(s, args[0], args[1], args[2], STH); |
| 373 |
break;
|
| 374 |
case INDEX_op_st_i32:
|
| 375 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 376 |
case INDEX_op_st32_i64:
|
| 377 |
#endif
|
| 378 |
tcg_out_ldst(s, args[0], args[1], args[2], STW); |
| 379 |
break;
|
| 380 |
OP_32_64(add); |
| 381 |
c = ARITH_ADD; |
| 382 |
goto gen_arith32;
|
| 383 |
OP_32_64(sub); |
| 384 |
c = ARITH_SUB; |
| 385 |
goto gen_arith32;
|
| 386 |
OP_32_64(and); |
| 387 |
c = ARITH_AND; |
| 388 |
goto gen_arith32;
|
| 389 |
OP_32_64(or); |
| 390 |
c = ARITH_OR; |
| 391 |
goto gen_arith32;
|
| 392 |
OP_32_64(xor); |
| 393 |
c = ARITH_XOR; |
| 394 |
goto gen_arith32;
|
| 395 |
case INDEX_op_shl_i32:
|
| 396 |
c = SHIFT_SLL; |
| 397 |
goto gen_arith32;
|
| 398 |
case INDEX_op_shr_i32:
|
| 399 |
c = SHIFT_SRL; |
| 400 |
goto gen_arith32;
|
| 401 |
case INDEX_op_sar_i32:
|
| 402 |
c = SHIFT_SRA; |
| 403 |
goto gen_arith32;
|
| 404 |
case INDEX_op_mul_i32:
|
| 405 |
c = ARITH_UMUL; |
| 406 |
goto gen_arith32;
|
| 407 |
case INDEX_op_div2_i32:
|
| 408 |
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
| 409 |
c = ARITH_SDIVX; |
| 410 |
goto gen_arith32;
|
| 411 |
#else
|
| 412 |
tcg_out_sety(s, 0);
|
| 413 |
c = ARITH_SDIV; |
| 414 |
goto gen_arith32;
|
| 415 |
#endif
|
| 416 |
case INDEX_op_divu2_i32:
|
| 417 |
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
| 418 |
c = ARITH_UDIVX; |
| 419 |
goto gen_arith32;
|
| 420 |
#else
|
| 421 |
tcg_out_sety(s, 0);
|
| 422 |
c = ARITH_UDIV; |
| 423 |
goto gen_arith32;
|
| 424 |
#endif
|
| 425 |
|
| 426 |
case INDEX_op_brcond_i32:
|
| 427 |
fprintf(stderr, "unimplemented brcond\n");
|
| 428 |
break;
|
| 429 |
|
| 430 |
case INDEX_op_qemu_ld8u:
|
| 431 |
fprintf(stderr, "unimplemented qld\n");
|
| 432 |
break;
|
| 433 |
case INDEX_op_qemu_ld8s:
|
| 434 |
fprintf(stderr, "unimplemented qld\n");
|
| 435 |
break;
|
| 436 |
case INDEX_op_qemu_ld16u:
|
| 437 |
fprintf(stderr, "unimplemented qld\n");
|
| 438 |
break;
|
| 439 |
case INDEX_op_qemu_ld16s:
|
| 440 |
fprintf(stderr, "unimplemented qld\n");
|
| 441 |
break;
|
| 442 |
case INDEX_op_qemu_ld32u:
|
| 443 |
fprintf(stderr, "unimplemented qld\n");
|
| 444 |
break;
|
| 445 |
case INDEX_op_qemu_ld32s:
|
| 446 |
fprintf(stderr, "unimplemented qld\n");
|
| 447 |
break;
|
| 448 |
case INDEX_op_qemu_st8:
|
| 449 |
fprintf(stderr, "unimplemented qst\n");
|
| 450 |
break;
|
| 451 |
case INDEX_op_qemu_st16:
|
| 452 |
fprintf(stderr, "unimplemented qst\n");
|
| 453 |
break;
|
| 454 |
case INDEX_op_qemu_st32:
|
| 455 |
fprintf(stderr, "unimplemented qst\n");
|
| 456 |
break;
|
| 457 |
|
| 458 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 459 |
case INDEX_op_movi_i64:
|
| 460 |
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
| 461 |
break;
|
| 462 |
case INDEX_op_ld32s_i64:
|
| 463 |
tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
| 464 |
break;
|
| 465 |
case INDEX_op_ld_i64:
|
| 466 |
tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
| 467 |
break;
|
| 468 |
case INDEX_op_st_i64:
|
| 469 |
tcg_out_ldst(s, args[0], args[1], args[2], STX); |
| 470 |
break;
|
| 471 |
case INDEX_op_shl_i64:
|
| 472 |
c = SHIFT_SLLX; |
| 473 |
goto gen_arith32;
|
| 474 |
case INDEX_op_shr_i64:
|
| 475 |
c = SHIFT_SRLX; |
| 476 |
goto gen_arith32;
|
| 477 |
case INDEX_op_sar_i64:
|
| 478 |
c = SHIFT_SRAX; |
| 479 |
goto gen_arith32;
|
| 480 |
case INDEX_op_mul_i64:
|
| 481 |
c = ARITH_MULX; |
| 482 |
goto gen_arith32;
|
| 483 |
case INDEX_op_div2_i64:
|
| 484 |
c = ARITH_SDIVX; |
| 485 |
goto gen_arith32;
|
| 486 |
case INDEX_op_divu2_i64:
|
| 487 |
c = ARITH_UDIVX; |
| 488 |
goto gen_arith32;
|
| 489 |
|
| 490 |
case INDEX_op_brcond_i64:
|
| 491 |
fprintf(stderr, "unimplemented brcond\n");
|
| 492 |
break;
|
| 493 |
case INDEX_op_qemu_ld64:
|
| 494 |
fprintf(stderr, "unimplemented qld\n");
|
| 495 |
break;
|
| 496 |
case INDEX_op_qemu_st64:
|
| 497 |
fprintf(stderr, "unimplemented qst\n");
|
| 498 |
break;
|
| 499 |
|
| 500 |
#endif
|
| 501 |
gen_arith32:
|
| 502 |
if (const_args[2]) { |
| 503 |
tcg_out_arithi(s, args[0], args[1], args[2], c); |
| 504 |
} else {
|
| 505 |
tcg_out_arith(s, args[0], args[1], args[2], c); |
| 506 |
} |
| 507 |
break;
|
| 508 |
|
| 509 |
default:
|
| 510 |
fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
| 511 |
tcg_abort(); |
| 512 |
} |
| 513 |
} |
| 514 |
|
| 515 |
static const TCGTargetOpDef sparc_op_defs[] = { |
| 516 |
{ INDEX_op_exit_tb, { } },
|
| 517 |
{ INDEX_op_goto_tb, { "r" } },
|
| 518 |
{ INDEX_op_call, { "ri" } },
|
| 519 |
{ INDEX_op_jmp, { "ri" } },
|
| 520 |
{ INDEX_op_br, { } },
|
| 521 |
|
| 522 |
{ INDEX_op_mov_i32, { "r", "r" } },
|
| 523 |
{ INDEX_op_movi_i32, { "r" } },
|
| 524 |
{ INDEX_op_ld8u_i32, { "r", "r" } },
|
| 525 |
{ INDEX_op_ld8s_i32, { "r", "r" } },
|
| 526 |
{ INDEX_op_ld16u_i32, { "r", "r" } },
|
| 527 |
{ INDEX_op_ld16s_i32, { "r", "r" } },
|
| 528 |
{ INDEX_op_ld_i32, { "r", "r" } },
|
| 529 |
{ INDEX_op_st8_i32, { "r", "r" } },
|
| 530 |
{ INDEX_op_st16_i32, { "r", "r" } },
|
| 531 |
{ INDEX_op_st_i32, { "r", "r" } },
|
| 532 |
|
| 533 |
{ INDEX_op_add_i32, { "r", "r", "rJ" } },
|
| 534 |
{ INDEX_op_mul_i32, { "r", "r", "rJ" } },
|
| 535 |
{ INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
|
| 536 |
{ INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
|
| 537 |
{ INDEX_op_sub_i32, { "r", "r", "rJ" } },
|
| 538 |
{ INDEX_op_and_i32, { "r", "r", "rJ" } },
|
| 539 |
{ INDEX_op_or_i32, { "r", "r", "rJ" } },
|
| 540 |
{ INDEX_op_xor_i32, { "r", "r", "rJ" } },
|
| 541 |
|
| 542 |
{ INDEX_op_shl_i32, { "r", "r", "rJ" } },
|
| 543 |
{ INDEX_op_shr_i32, { "r", "r", "rJ" } },
|
| 544 |
{ INDEX_op_sar_i32, { "r", "r", "rJ" } },
|
| 545 |
|
| 546 |
{ INDEX_op_brcond_i32, { "r", "ri" } },
|
| 547 |
|
| 548 |
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
| 549 |
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
| 550 |
{ INDEX_op_qemu_ld16u, { "r", "L" } },
|
| 551 |
{ INDEX_op_qemu_ld16s, { "r", "L" } },
|
| 552 |
{ INDEX_op_qemu_ld32u, { "r", "L" } },
|
| 553 |
{ INDEX_op_qemu_ld32s, { "r", "L" } },
|
| 554 |
|
| 555 |
{ INDEX_op_qemu_st8, { "L", "L" } },
|
| 556 |
{ INDEX_op_qemu_st16, { "L", "L" } },
|
| 557 |
{ INDEX_op_qemu_st32, { "L", "L" } },
|
| 558 |
|
| 559 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 560 |
{ INDEX_op_mov_i64, { "r", "r" } },
|
| 561 |
{ INDEX_op_movi_i64, { "r" } },
|
| 562 |
{ INDEX_op_ld8u_i64, { "r", "r" } },
|
| 563 |
{ INDEX_op_ld8s_i64, { "r", "r" } },
|
| 564 |
{ INDEX_op_ld16u_i64, { "r", "r" } },
|
| 565 |
{ INDEX_op_ld16s_i64, { "r", "r" } },
|
| 566 |
{ INDEX_op_ld32u_i64, { "r", "r" } },
|
| 567 |
{ INDEX_op_ld32s_i64, { "r", "r" } },
|
| 568 |
{ INDEX_op_ld_i64, { "r", "r" } },
|
| 569 |
{ INDEX_op_st8_i64, { "r", "r" } },
|
| 570 |
{ INDEX_op_st16_i64, { "r", "r" } },
|
| 571 |
{ INDEX_op_st32_i64, { "r", "r" } },
|
| 572 |
{ INDEX_op_st_i64, { "r", "r" } },
|
| 573 |
|
| 574 |
{ INDEX_op_add_i64, { "r", "r", "rJ" } },
|
| 575 |
{ INDEX_op_mul_i64, { "r", "r", "rJ" } },
|
| 576 |
{ INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
|
| 577 |
{ INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
|
| 578 |
{ INDEX_op_sub_i64, { "r", "r", "rJ" } },
|
| 579 |
{ INDEX_op_and_i64, { "r", "r", "rJ" } },
|
| 580 |
{ INDEX_op_or_i64, { "r", "r", "rJ" } },
|
| 581 |
{ INDEX_op_xor_i64, { "r", "r", "rJ" } },
|
| 582 |
|
| 583 |
{ INDEX_op_shl_i64, { "r", "r", "rJ" } },
|
| 584 |
{ INDEX_op_shr_i64, { "r", "r", "rJ" } },
|
| 585 |
{ INDEX_op_sar_i64, { "r", "r", "rJ" } },
|
| 586 |
|
| 587 |
{ INDEX_op_brcond_i64, { "r", "ri" } },
|
| 588 |
#endif
|
| 589 |
{ -1 },
|
| 590 |
}; |
| 591 |
|
| 592 |
void tcg_target_init(TCGContext *s)
|
| 593 |
{
|
| 594 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
| 595 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 596 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
| 597 |
#endif
|
| 598 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
| 599 |
(1 << TCG_REG_O0) |
|
| 600 |
(1 << TCG_REG_O1) |
|
| 601 |
(1 << TCG_REG_O2) |
|
| 602 |
(1 << TCG_REG_O3) |
|
| 603 |
(1 << TCG_REG_O4) |
|
| 604 |
(1 << TCG_REG_O5) |
|
| 605 |
(1 << TCG_REG_O6) |
|
| 606 |
(1 << TCG_REG_O7));
|
| 607 |
|
| 608 |
tcg_regset_clear(s->reserved_regs); |
| 609 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
| 610 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
|
| 611 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
| 612 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
| 613 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
| 614 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); |
| 615 |
tcg_add_target_add_op_defs(sparc_op_defs); |
| 616 |
} |