Revision 540635ba target-mips/translate_init.c

b/target-mips/translate_init.c
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                    (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
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        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
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    },
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#ifdef TARGET_MIPS64
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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    {
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        .name = "R4000",
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        .CP0_PRid = 0x00000400,
......
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    env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
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    env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
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    env->CP0_SRSCtl = def->CP0_SRSCtl;
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#ifdef TARGET_MIPS64
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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    if (def->insn_flags & ISA_MIPS3)
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    {
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        env->hflags |= MIPS_HFLAG_64;

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