Revision 54454097 target-mips/op_helper.c
| b/target-mips/op_helper.c | ||
|---|---|---|
| 613 | 613 |
#define FLOAT_ONE64 (0x3ffULL << 52) |
| 614 | 614 |
#define FLOAT_TWO32 (1 << 30) |
| 615 | 615 |
#define FLOAT_TWO64 (1ULL << 62) |
| 616 |
#define FLOAT_QNAN32 0x7fbfffff |
|
| 617 |
#define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
|
| 618 |
#define FLOAT_SNAN32 0x7fffffff |
|
| 619 |
#define FLOAT_SNAN64 0x7fffffffffffffffULL |
|
| 616 | 620 |
|
| 617 | 621 |
/* convert MIPS rounding mode in FCR31 to IEEE library */ |
| 618 | 622 |
unsigned int ieee_rm[] = {
|
| ... | ... | |
| 736 | 740 |
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
| 737 | 741 |
update_fcr31(); |
| 738 | 742 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 739 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 743 |
DT2 = FLOAT_SNAN64;
|
|
| 740 | 744 |
} |
| 741 | 745 |
FLOAT_OP(cvtl, s) |
| 742 | 746 |
{
|
| ... | ... | |
| 744 | 748 |
DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
| 745 | 749 |
update_fcr31(); |
| 746 | 750 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 747 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 751 |
DT2 = FLOAT_SNAN64;
|
|
| 748 | 752 |
} |
| 749 | 753 |
|
| 750 | 754 |
FLOAT_OP(cvtps, pw) |
| ... | ... | |
| 761 | 765 |
WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status); |
| 762 | 766 |
update_fcr31(); |
| 763 | 767 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 764 |
WT2 = 0x7fffffff;
|
|
| 768 |
WT2 = FLOAT_SNAN32;
|
|
| 765 | 769 |
} |
| 766 | 770 |
FLOAT_OP(cvts, d) |
| 767 | 771 |
{
|
| ... | ... | |
| 799 | 803 |
WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
| 800 | 804 |
update_fcr31(); |
| 801 | 805 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 802 |
WT2 = 0x7fffffff;
|
|
| 806 |
WT2 = FLOAT_SNAN32;
|
|
| 803 | 807 |
} |
| 804 | 808 |
FLOAT_OP(cvtw, d) |
| 805 | 809 |
{
|
| ... | ... | |
| 807 | 811 |
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
| 808 | 812 |
update_fcr31(); |
| 809 | 813 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 810 |
WT2 = 0x7fffffff;
|
|
| 814 |
WT2 = FLOAT_SNAN32;
|
|
| 811 | 815 |
} |
| 812 | 816 |
|
| 813 | 817 |
FLOAT_OP(roundl, d) |
| ... | ... | |
| 817 | 821 |
RESTORE_ROUNDING_MODE; |
| 818 | 822 |
update_fcr31(); |
| 819 | 823 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 820 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 824 |
DT2 = FLOAT_SNAN64;
|
|
| 821 | 825 |
} |
| 822 | 826 |
FLOAT_OP(roundl, s) |
| 823 | 827 |
{
|
| ... | ... | |
| 826 | 830 |
RESTORE_ROUNDING_MODE; |
| 827 | 831 |
update_fcr31(); |
| 828 | 832 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 829 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 833 |
DT2 = FLOAT_SNAN64;
|
|
| 830 | 834 |
} |
| 831 | 835 |
FLOAT_OP(roundw, d) |
| 832 | 836 |
{
|
| ... | ... | |
| 835 | 839 |
RESTORE_ROUNDING_MODE; |
| 836 | 840 |
update_fcr31(); |
| 837 | 841 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 838 |
WT2 = 0x7fffffff;
|
|
| 842 |
WT2 = FLOAT_SNAN32;
|
|
| 839 | 843 |
} |
| 840 | 844 |
FLOAT_OP(roundw, s) |
| 841 | 845 |
{
|
| ... | ... | |
| 844 | 848 |
RESTORE_ROUNDING_MODE; |
| 845 | 849 |
update_fcr31(); |
| 846 | 850 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 847 |
WT2 = 0x7fffffff;
|
|
| 851 |
WT2 = FLOAT_SNAN32;
|
|
| 848 | 852 |
} |
| 849 | 853 |
|
| 850 | 854 |
FLOAT_OP(truncl, d) |
| ... | ... | |
| 852 | 856 |
DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status); |
| 853 | 857 |
update_fcr31(); |
| 854 | 858 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 855 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 859 |
DT2 = FLOAT_SNAN64;
|
|
| 856 | 860 |
} |
| 857 | 861 |
FLOAT_OP(truncl, s) |
| 858 | 862 |
{
|
| 859 | 863 |
DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status); |
| 860 | 864 |
update_fcr31(); |
| 861 | 865 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 862 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 866 |
DT2 = FLOAT_SNAN64;
|
|
| 863 | 867 |
} |
| 864 | 868 |
FLOAT_OP(truncw, d) |
| 865 | 869 |
{
|
| 866 | 870 |
WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status); |
| 867 | 871 |
update_fcr31(); |
| 868 | 872 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 869 |
WT2 = 0x7fffffff;
|
|
| 873 |
WT2 = FLOAT_SNAN32;
|
|
| 870 | 874 |
} |
| 871 | 875 |
FLOAT_OP(truncw, s) |
| 872 | 876 |
{
|
| 873 | 877 |
WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status); |
| 874 | 878 |
update_fcr31(); |
| 875 | 879 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 876 |
WT2 = 0x7fffffff;
|
|
| 880 |
WT2 = FLOAT_SNAN32;
|
|
| 877 | 881 |
} |
| 878 | 882 |
|
| 879 | 883 |
FLOAT_OP(ceill, d) |
| ... | ... | |
| 883 | 887 |
RESTORE_ROUNDING_MODE; |
| 884 | 888 |
update_fcr31(); |
| 885 | 889 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 886 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 890 |
DT2 = FLOAT_SNAN64;
|
|
| 887 | 891 |
} |
| 888 | 892 |
FLOAT_OP(ceill, s) |
| 889 | 893 |
{
|
| ... | ... | |
| 892 | 896 |
RESTORE_ROUNDING_MODE; |
| 893 | 897 |
update_fcr31(); |
| 894 | 898 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 895 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 899 |
DT2 = FLOAT_SNAN64;
|
|
| 896 | 900 |
} |
| 897 | 901 |
FLOAT_OP(ceilw, d) |
| 898 | 902 |
{
|
| ... | ... | |
| 901 | 905 |
RESTORE_ROUNDING_MODE; |
| 902 | 906 |
update_fcr31(); |
| 903 | 907 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 904 |
WT2 = 0x7fffffff;
|
|
| 908 |
WT2 = FLOAT_SNAN32;
|
|
| 905 | 909 |
} |
| 906 | 910 |
FLOAT_OP(ceilw, s) |
| 907 | 911 |
{
|
| ... | ... | |
| 910 | 914 |
RESTORE_ROUNDING_MODE; |
| 911 | 915 |
update_fcr31(); |
| 912 | 916 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 913 |
WT2 = 0x7fffffff;
|
|
| 917 |
WT2 = FLOAT_SNAN32;
|
|
| 914 | 918 |
} |
| 915 | 919 |
|
| 916 | 920 |
FLOAT_OP(floorl, d) |
| ... | ... | |
| 920 | 924 |
RESTORE_ROUNDING_MODE; |
| 921 | 925 |
update_fcr31(); |
| 922 | 926 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 923 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 927 |
DT2 = FLOAT_SNAN64;
|
|
| 924 | 928 |
} |
| 925 | 929 |
FLOAT_OP(floorl, s) |
| 926 | 930 |
{
|
| ... | ... | |
| 929 | 933 |
RESTORE_ROUNDING_MODE; |
| 930 | 934 |
update_fcr31(); |
| 931 | 935 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 932 |
DT2 = 0x7fffffffffffffffULL;
|
|
| 936 |
DT2 = FLOAT_SNAN64;
|
|
| 933 | 937 |
} |
| 934 | 938 |
FLOAT_OP(floorw, d) |
| 935 | 939 |
{
|
| ... | ... | |
| 938 | 942 |
RESTORE_ROUNDING_MODE; |
| 939 | 943 |
update_fcr31(); |
| 940 | 944 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 941 |
WT2 = 0x7fffffff;
|
|
| 945 |
WT2 = FLOAT_SNAN32;
|
|
| 942 | 946 |
} |
| 943 | 947 |
FLOAT_OP(floorw, s) |
| 944 | 948 |
{
|
| ... | ... | |
| 947 | 951 |
RESTORE_ROUNDING_MODE; |
| 948 | 952 |
update_fcr31(); |
| 949 | 953 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
| 950 |
WT2 = 0x7fffffff;
|
|
| 954 |
WT2 = FLOAT_SNAN32;
|
|
| 951 | 955 |
} |
| 952 | 956 |
|
| 953 | 957 |
/* MIPS specific unary operations */ |
| ... | ... | |
| 1031 | 1035 |
FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \ |
| 1032 | 1036 |
update_fcr31(); \ |
| 1033 | 1037 |
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \ |
| 1034 |
FDT2 = 0x7ff7ffffffffffffULL; \
|
|
| 1038 |
FDT2 = FLOAT_QNAN64; \
|
|
| 1035 | 1039 |
} \ |
| 1036 | 1040 |
FLOAT_OP(name, s) \ |
| 1037 | 1041 |
{ \
|
| ... | ... | |
| 1039 | 1043 |
FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
| 1040 | 1044 |
update_fcr31(); \ |
| 1041 | 1045 |
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \ |
| 1042 |
FST2 = 0x7fbfffff; \
|
|
| 1046 |
FST2 = FLOAT_QNAN32; \
|
|
| 1043 | 1047 |
} \ |
| 1044 | 1048 |
FLOAT_OP(name, ps) \ |
| 1045 | 1049 |
{ \
|
| ... | ... | |
| 1048 | 1052 |
FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \ |
| 1049 | 1053 |
update_fcr31(); \ |
| 1050 | 1054 |
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
|
| 1051 |
FST2 = 0x7fbfffff; \
|
|
| 1052 |
FSTH2 = 0x7fbfffff; \
|
|
| 1055 |
FST2 = FLOAT_QNAN32; \
|
|
| 1056 |
FSTH2 = FLOAT_QNAN32; \
|
|
| 1053 | 1057 |
} \ |
| 1054 | 1058 |
} |
| 1055 | 1059 |
FLOAT_BINOP(add) |
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