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1 | 420557e8 | bellard | /*
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2 | 8d5f07fa | bellard | * QEMU interrupt controller emulation
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3 | 420557e8 | bellard | *
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4 | 420557e8 | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 420557e8 | bellard | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 420557e8 | bellard | #include "vl.h" |
25 | 8d5f07fa | bellard | //#define DEBUG_IRQ_COUNT
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26 | 420557e8 | bellard | |
27 | 420557e8 | bellard | /* These registers are used for sending/receiving irqs from/to
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28 | 420557e8 | bellard | * different cpu's.
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29 | 420557e8 | bellard | */
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30 | 420557e8 | bellard | struct sun4m_intreg_percpu {
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31 | 420557e8 | bellard | unsigned int tbt; /* Intrs pending for this cpu, by PIL. */ |
32 | 420557e8 | bellard | /* These next two registers are WRITE-ONLY and are only
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33 | 420557e8 | bellard | * "on bit" sensitive, "off bits" written have NO affect.
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34 | 420557e8 | bellard | */
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35 | 420557e8 | bellard | unsigned int clear; /* Clear this cpus irqs here. */ |
36 | 420557e8 | bellard | unsigned int set; /* Set this cpus irqs here. */ |
37 | 420557e8 | bellard | }; |
38 | 420557e8 | bellard | /*
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39 | 420557e8 | bellard | * djhr
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40 | 420557e8 | bellard | * Actually the clear and set fields in this struct are misleading..
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41 | 420557e8 | bellard | * according to the SLAVIO manual (and the same applies for the SEC)
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42 | 420557e8 | bellard | * the clear field clears bits in the mask which will ENABLE that IRQ
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43 | 420557e8 | bellard | * the set field sets bits in the mask to DISABLE the IRQ.
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44 | 420557e8 | bellard | *
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45 | 420557e8 | bellard | * Also the undirected_xx address in the SLAVIO is defined as
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46 | 420557e8 | bellard | * RESERVED and write only..
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47 | 420557e8 | bellard | *
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48 | 420557e8 | bellard | * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
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49 | 420557e8 | bellard | * sun4m machines, for MP the layout makes more sense.
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50 | 420557e8 | bellard | */
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51 | 420557e8 | bellard | struct sun4m_intreg_master {
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52 | 420557e8 | bellard | unsigned int tbt; /* IRQ's that are pending, see sun4m masks. */ |
53 | 420557e8 | bellard | unsigned int irqs; /* Master IRQ bits. */ |
54 | 420557e8 | bellard | |
55 | 420557e8 | bellard | /* Again, like the above, two these registers are WRITE-ONLY. */
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56 | 420557e8 | bellard | unsigned int clear; /* Clear master IRQ's by setting bits here. */ |
57 | 420557e8 | bellard | unsigned int set; /* Set master IRQ's by setting bits here. */ |
58 | 420557e8 | bellard | |
59 | 420557e8 | bellard | /* This register is both READ and WRITE. */
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60 | 420557e8 | bellard | unsigned int undirected_target; /* Which cpu gets undirected irqs. */ |
61 | 420557e8 | bellard | }; |
62 | 420557e8 | bellard | |
63 | 420557e8 | bellard | #define SUN4M_INT_ENABLE 0x80000000 |
64 | 420557e8 | bellard | #define SUN4M_INT_E14 0x00000080 |
65 | 420557e8 | bellard | #define SUN4M_INT_E10 0x00080000 |
66 | 420557e8 | bellard | |
67 | 420557e8 | bellard | #define SUN4M_HARD_INT(x) (0x000000001 << (x)) |
68 | 420557e8 | bellard | #define SUN4M_SOFT_INT(x) (0x000010000 << (x)) |
69 | 420557e8 | bellard | |
70 | 420557e8 | bellard | #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ |
71 | 420557e8 | bellard | #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ |
72 | 420557e8 | bellard | #define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */ |
73 | 420557e8 | bellard | #define SUN4M_INT_ECC 0x10000000 /* ecc memory error */ |
74 | 420557e8 | bellard | #define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */ |
75 | 420557e8 | bellard | #define SUN4M_INT_MODULE 0x00200000 /* module interrupt */ |
76 | 420557e8 | bellard | #define SUN4M_INT_VIDEO 0x00100000 /* onboard video */ |
77 | 420557e8 | bellard | #define SUN4M_INT_REALTIME 0x00080000 /* system timer */ |
78 | 420557e8 | bellard | #define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */ |
79 | 420557e8 | bellard | #define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */ |
80 | 420557e8 | bellard | #define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */ |
81 | 420557e8 | bellard | #define SUN4M_INT_SERIAL 0x00008000 /* serial ports */ |
82 | 420557e8 | bellard | #define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */ |
83 | 420557e8 | bellard | |
84 | 420557e8 | bellard | #define SUN4M_INT_SBUS(x) (1 << (x+7)) |
85 | 420557e8 | bellard | #define SUN4M_INT_VME(x) (1 << (x)) |
86 | 420557e8 | bellard | |
87 | 420557e8 | bellard | typedef struct SCHEDState { |
88 | 8d5f07fa | bellard | uint32_t addr, addrg; |
89 | 420557e8 | bellard | uint32_t intreg_pending; |
90 | 420557e8 | bellard | uint32_t intreg_enabled; |
91 | 420557e8 | bellard | uint32_t intregm_pending; |
92 | 420557e8 | bellard | uint32_t intregm_enabled; |
93 | 420557e8 | bellard | } SCHEDState; |
94 | 420557e8 | bellard | |
95 | 420557e8 | bellard | static SCHEDState *ps;
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96 | 420557e8 | bellard | |
97 | 8d5f07fa | bellard | #ifdef DEBUG_IRQ_COUNT
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98 | 8d5f07fa | bellard | static uint64_t irq_count[32]; |
99 | 8d5f07fa | bellard | #endif
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100 | 420557e8 | bellard | |
101 | 420557e8 | bellard | static uint32_t intreg_mem_readl(void *opaque, target_phys_addr_t addr) |
102 | 420557e8 | bellard | { |
103 | 420557e8 | bellard | SCHEDState *s = opaque; |
104 | 420557e8 | bellard | uint32_t saddr; |
105 | 420557e8 | bellard | |
106 | 8d5f07fa | bellard | saddr = (addr - s->addr) >> 2;
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107 | 420557e8 | bellard | switch (saddr) {
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108 | 420557e8 | bellard | case 0: |
109 | 420557e8 | bellard | return s->intreg_pending;
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110 | 420557e8 | bellard | break;
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111 | 420557e8 | bellard | default:
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112 | 420557e8 | bellard | break;
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113 | 420557e8 | bellard | } |
114 | 420557e8 | bellard | return 0; |
115 | 420557e8 | bellard | } |
116 | 420557e8 | bellard | |
117 | 420557e8 | bellard | static void intreg_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
118 | 420557e8 | bellard | { |
119 | 420557e8 | bellard | SCHEDState *s = opaque; |
120 | 420557e8 | bellard | uint32_t saddr; |
121 | 420557e8 | bellard | |
122 | 8d5f07fa | bellard | saddr = (addr - s->addr) >> 2;
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123 | 420557e8 | bellard | switch (saddr) {
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124 | 420557e8 | bellard | case 0: |
125 | 420557e8 | bellard | s->intreg_pending = val; |
126 | 420557e8 | bellard | break;
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127 | 420557e8 | bellard | case 1: // clear |
128 | 420557e8 | bellard | s->intreg_enabled &= ~val; |
129 | 420557e8 | bellard | break;
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130 | 420557e8 | bellard | case 2: // set |
131 | 420557e8 | bellard | s->intreg_enabled |= val; |
132 | 420557e8 | bellard | break;
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133 | 420557e8 | bellard | default:
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134 | 420557e8 | bellard | break;
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135 | 420557e8 | bellard | } |
136 | 420557e8 | bellard | } |
137 | 420557e8 | bellard | |
138 | 420557e8 | bellard | static CPUReadMemoryFunc *intreg_mem_read[3] = { |
139 | 420557e8 | bellard | intreg_mem_readl, |
140 | 420557e8 | bellard | intreg_mem_readl, |
141 | 420557e8 | bellard | intreg_mem_readl, |
142 | 420557e8 | bellard | }; |
143 | 420557e8 | bellard | |
144 | 420557e8 | bellard | static CPUWriteMemoryFunc *intreg_mem_write[3] = { |
145 | 420557e8 | bellard | intreg_mem_writel, |
146 | 420557e8 | bellard | intreg_mem_writel, |
147 | 420557e8 | bellard | intreg_mem_writel, |
148 | 420557e8 | bellard | }; |
149 | 420557e8 | bellard | |
150 | 420557e8 | bellard | static uint32_t intregm_mem_readl(void *opaque, target_phys_addr_t addr) |
151 | 420557e8 | bellard | { |
152 | 420557e8 | bellard | SCHEDState *s = opaque; |
153 | 420557e8 | bellard | uint32_t saddr; |
154 | 420557e8 | bellard | |
155 | 8d5f07fa | bellard | saddr = (addr - s->addrg) >> 2;
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156 | 420557e8 | bellard | switch (saddr) {
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157 | 420557e8 | bellard | case 0: |
158 | 420557e8 | bellard | return s->intregm_pending;
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159 | 420557e8 | bellard | break;
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160 | 420557e8 | bellard | case 1: |
161 | 420557e8 | bellard | return s->intregm_enabled;
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162 | 420557e8 | bellard | break;
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163 | 420557e8 | bellard | default:
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164 | 420557e8 | bellard | break;
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165 | 420557e8 | bellard | } |
166 | 420557e8 | bellard | return 0; |
167 | 420557e8 | bellard | } |
168 | 420557e8 | bellard | |
169 | 420557e8 | bellard | static void intregm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
170 | 420557e8 | bellard | { |
171 | 420557e8 | bellard | SCHEDState *s = opaque; |
172 | 420557e8 | bellard | uint32_t saddr; |
173 | 420557e8 | bellard | |
174 | 8d5f07fa | bellard | saddr = (addr - s->addrg) >> 2;
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175 | 420557e8 | bellard | switch (saddr) {
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176 | 420557e8 | bellard | case 0: |
177 | 420557e8 | bellard | s->intregm_pending = val; |
178 | 420557e8 | bellard | break;
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179 | 420557e8 | bellard | case 1: |
180 | 420557e8 | bellard | s->intregm_enabled = val; |
181 | 420557e8 | bellard | break;
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182 | 420557e8 | bellard | case 2: // clear |
183 | 420557e8 | bellard | s->intregm_enabled &= ~val; |
184 | 420557e8 | bellard | break;
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185 | 420557e8 | bellard | case 3: // set |
186 | 420557e8 | bellard | s->intregm_enabled |= val; |
187 | 420557e8 | bellard | break;
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188 | 420557e8 | bellard | default:
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189 | 420557e8 | bellard | break;
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190 | 420557e8 | bellard | } |
191 | 420557e8 | bellard | } |
192 | 420557e8 | bellard | |
193 | 420557e8 | bellard | static CPUReadMemoryFunc *intregm_mem_read[3] = { |
194 | 420557e8 | bellard | intregm_mem_readl, |
195 | 420557e8 | bellard | intregm_mem_readl, |
196 | 420557e8 | bellard | intregm_mem_readl, |
197 | 420557e8 | bellard | }; |
198 | 420557e8 | bellard | |
199 | 420557e8 | bellard | static CPUWriteMemoryFunc *intregm_mem_write[3] = { |
200 | 420557e8 | bellard | intregm_mem_writel, |
201 | 420557e8 | bellard | intregm_mem_writel, |
202 | 420557e8 | bellard | intregm_mem_writel, |
203 | 420557e8 | bellard | }; |
204 | 420557e8 | bellard | |
205 | 8d5f07fa | bellard | void pic_info(void) |
206 | 420557e8 | bellard | { |
207 | 8d5f07fa | bellard | term_printf("per-cpu: pending 0x%08x, enabled 0x%08x\n", ps->intreg_pending, ps->intreg_enabled);
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208 | 8d5f07fa | bellard | term_printf("master: pending 0x%08x, enabled 0x%08x\n", ps->intregm_pending, ps->intregm_enabled);
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209 | 420557e8 | bellard | } |
210 | 420557e8 | bellard | |
211 | 8d5f07fa | bellard | void irq_info(void) |
212 | 420557e8 | bellard | { |
213 | 8d5f07fa | bellard | #ifndef DEBUG_IRQ_COUNT
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214 | 8d5f07fa | bellard | term_printf("irq statistic code not compiled.\n");
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215 | 8d5f07fa | bellard | #else
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216 | 8d5f07fa | bellard | int i;
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217 | 8d5f07fa | bellard | int64_t count; |
218 | 8d5f07fa | bellard | |
219 | 8d5f07fa | bellard | term_printf("IRQ statistics:\n");
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220 | 8d5f07fa | bellard | for (i = 0; i < 32; i++) { |
221 | 8d5f07fa | bellard | count = irq_count[i]; |
222 | 8d5f07fa | bellard | if (count > 0) |
223 | 8d5f07fa | bellard | term_printf("%2d: %lld\n", i, count);
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224 | 420557e8 | bellard | } |
225 | 8d5f07fa | bellard | #endif
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226 | 420557e8 | bellard | } |
227 | 420557e8 | bellard | |
228 | 420557e8 | bellard | static const unsigned int intr_to_mask[16] = { |
229 | 420557e8 | bellard | 0, 0, 0, 0, 0, 0, SUN4M_INT_ETHERNET, 0, |
230 | 420557e8 | bellard | 0, 0, 0, 0, 0, 0, 0, 0, |
231 | 420557e8 | bellard | }; |
232 | 420557e8 | bellard | |
233 | 420557e8 | bellard | void pic_set_irq(int irq, int level) |
234 | 420557e8 | bellard | { |
235 | 420557e8 | bellard | if (irq < 16) { |
236 | 420557e8 | bellard | unsigned int mask = intr_to_mask[irq]; |
237 | 420557e8 | bellard | ps->intreg_pending |= 1 << irq;
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238 | 420557e8 | bellard | if (ps->intregm_enabled & mask) {
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239 | 420557e8 | bellard | cpu_single_env->interrupt_index = irq; |
240 | 420557e8 | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
241 | 420557e8 | bellard | } |
242 | 420557e8 | bellard | } |
243 | 8d5f07fa | bellard | #ifdef DEBUG_IRQ_COUNT
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244 | 8d5f07fa | bellard | if (level == 1) |
245 | 8d5f07fa | bellard | irq_count[irq]++; |
246 | 8d5f07fa | bellard | #endif
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247 | 420557e8 | bellard | } |
248 | 420557e8 | bellard | |
249 | 8d5f07fa | bellard | void sched_init(uint32_t addr, uint32_t addrg)
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250 | 420557e8 | bellard | { |
251 | 8d5f07fa | bellard | int intreg_io_memory, intregm_io_memory;
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252 | 420557e8 | bellard | SCHEDState *s; |
253 | 420557e8 | bellard | |
254 | 420557e8 | bellard | s = qemu_mallocz(sizeof(SCHEDState));
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255 | 420557e8 | bellard | if (!s)
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256 | 420557e8 | bellard | return;
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257 | 8d5f07fa | bellard | s->addr = addr; |
258 | 8d5f07fa | bellard | s->addrg = addrg; |
259 | 420557e8 | bellard | |
260 | 420557e8 | bellard | intreg_io_memory = cpu_register_io_memory(0, intreg_mem_read, intreg_mem_write, s);
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261 | 8d5f07fa | bellard | cpu_register_physical_memory(addr, 3, intreg_io_memory);
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262 | 420557e8 | bellard | |
263 | 420557e8 | bellard | intregm_io_memory = cpu_register_io_memory(0, intregm_mem_read, intregm_mem_write, s);
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264 | 8d5f07fa | bellard | cpu_register_physical_memory(addrg, 5, intregm_io_memory);
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265 | 420557e8 | bellard | |
266 | 420557e8 | bellard | ps = s; |
267 | 420557e8 | bellard | } |