Revision 54c96da7
| b/hw/apic.c | ||
|---|---|---|
| 19 | 19 |
*/ |
| 20 | 20 |
#include "hw.h" |
| 21 | 21 |
#include "pc.h" |
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#include "pci.h" |
|
| 23 |
#include "msix.h" |
|
| 22 | 24 |
#include "qemu-timer.h" |
| 23 | 25 |
#include "host-utils.h" |
| 24 | 26 |
|
| ... | ... | |
| 63 | 65 |
#define MAX_APICS 255 |
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#define MAX_APIC_WORDS 8 |
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|
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/* Intel APIC constants: from include/asm/msidef.h */ |
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#define MSI_DATA_VECTOR_SHIFT 0 |
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#define MSI_DATA_VECTOR_MASK 0x000000ff |
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#define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
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#define MSI_DATA_TRIGGER_SHIFT 15 |
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#define MSI_DATA_LEVEL_SHIFT 14 |
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#define MSI_ADDR_DEST_MODE_SHIFT 2 |
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#define MSI_ADDR_DEST_ID_SHIFT 12 |
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#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
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|
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#define MSI_ADDR_BASE 0xfee00000 |
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#define MSI_ADDR_SIZE 0x100000 |
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|
|
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typedef struct APICState {
|
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CPUState *cpu_env; |
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uint32_t apicbase; |
| ... | ... | |
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return val; |
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} |
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|
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static void apic_send_msi(target_phys_addr_t addr, uint32 data) |
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{
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uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
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uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
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uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; |
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uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; |
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uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; |
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/* XXX: Ignore redirection hint. */ |
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apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode); |
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} |
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|
|
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static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 749 | 775 |
{
|
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CPUState *env; |
| 751 | 777 |
APICState *s; |
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int index; |
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int index = (addr >> 4) & 0xff; |
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if (addr > 0xfff || !index) {
|
|
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/* MSI and MMIO APIC are at the same memory location, |
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* but actually not on the global bus: MSI is on PCI bus |
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* APIC is connected directly to the CPU. |
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* Mapping them on the global bus happens to work because |
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* MSI registers are reserved in APIC MMIO and vice versa. */ |
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apic_send_msi(addr, val); |
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return; |
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} |
|
| 753 | 788 |
|
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env = cpu_single_env; |
| 755 | 790 |
if (!env) |
| ... | ... | |
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printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
|
| 761 | 796 |
#endif |
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|
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index = (addr >> 4) & 0xff; |
|
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switch(index) {
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case 0x02: |
| 766 | 800 |
s->id = (val >> 24); |
| ... | ... | |
| 946 | 980 |
s->cpu_env = env; |
| 947 | 981 |
|
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apic_reset(s); |
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msix_supported = 1; |
|
| 949 | 984 |
|
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/* XXX: mapping more APICs at the same memory location */ |
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if (apic_io_memory == 0) {
|
| ... | ... | |
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on the global memory bus. */ |
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apic_io_memory = cpu_register_io_memory(apic_mem_read, |
| 955 | 990 |
apic_mem_write, NULL); |
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cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, |
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/* XXX: what if the base changes? */ |
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cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE, |
|
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apic_io_memory); |
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} |
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s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
| ... | ... | |
| 964 | 1000 |
local_apics[s->idx] = s; |
| 965 | 1001 |
return 0; |
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} |
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