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# Date Author Comment
403946c0 05/08/2011 07:55 pm Richard Henderson

target-arm: Privatize CPU_INTERRUPT_FIQ.

This interrupt name was only used by the ARM port.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
5bc95aa2 04/20/2011 01:59 pm Dmitry Eremin-Solenikov

Implement basic part of SA-1110/SA-1100

Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.
Implemented:
- IRQs
- GPIO
- PPC
- RTC
- UARTs (no IrDA/etc.)
- OST reused from pxa25x

Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the...
be5e7a76 04/10/2011 01:53 am Dmitry Eremin-Solenikov

arm: basic support for ARMv4/ARMv4T emulation

Currently target-arm/ assumes at least ARMv5 core. Add support for
handling also ARMv4/ARMv4T. This changes the following instructions:

BX

BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...
f8bf8606 03/07/2011 12:37 am Adam Lackorzynski

target-arm: Implement cp15 VA->PA translation

Implement VA->PA translations by cp15-c7 that went through unchanged
previously.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>
3213883e 02/11/2011 02:10 am Dmitry Eremin-Solenikov

arm: drop unused irq-related part of CPUARMState

These two fields were added as a part of ARMv7 support patch (back in
2007), were never used by any code, so can be dropped.

Signed-off-by: Dmitry Eremin-Solenikov <>
Reviewed-by: Peter Maydell <>...
e1bbf446 02/04/2011 10:30 pm Peter Maydell

target-arm: Add CPU feature flag for v7MP

Add a CPU feature flag for v7MP (the multiprocessing extensions); some
instructions exist only for v7MP and not for the base v7 architecture.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
05ed9a99 01/14/2011 09:39 pm Peter Maydell

target-arm: Set privileged bit in TB flags correctly for M profile

M profile ARM cores don't have a CPSR mode field. Set the bit in the
TB flags that indicates non-user mode correctly for these cores.

Signed-off-by: Peter Maydell <>...
3a492f3a 01/14/2011 09:39 pm Peter Maydell

target-arm: Add support for 'Standard FPSCR Value' as used by Neon

Add support to the ARM helper routines for a second fp_status value
which should be used for operations which the ARM ARM indicates use
"ARM standard floating-point arithmetic" rather than being controlled...
a1705768 01/14/2011 09:39 pm Peter Maydell

target-arm: Add symbolic constants for bitfields in TB flags

Add symbolic constants for the bitfields we use in the TB flags.

Signed-off-by: Peter Maydell <>
Reviewed-by: Aurelien Jarno <>
Signed-off-by: Aurelien Jarno <>
01653295 12/03/2010 03:09 pm Peter Maydell

ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C code

Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to C
code as well as generated code, so we can use them to read and
write the FPSCR when saving and restoring VFP registers across
signal handlers in linux-user mode....
b0e102dd 12/03/2010 03:09 pm Peter Maydell

[PATCH] target-arm: remove unused functions cpu_lock(), cpu_unlock()

Signed-off-by: Riku Voipio <>
9a78eead 10/30/2010 11:01 am Stefan Weil

target-xxx: Use fprintf_function (format checking)

fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
  • target-i386/helper.c
  • target-mips/translate.c
  • target-ppc/translate.c

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>...
a88790a1 07/03/2010 09:48 am Paolo Bonzini

remove exec-all.h inclusion from cpu.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>
10eb0cc0 07/03/2010 09:48 am Paolo Bonzini

move cpu_pc_from_tb to target-*/exec.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>
9ba8c3f4 05/28/2010 10:25 pm Lars Munch

arm: prevent coprocessor IO reset

This prevent coprocessor IO structure from being reset on cpu reset. This was
a problem for PXA which uses coprocessor 6 and 14.

Signed-off-by: Lars Munch <>
Signed-off-by: Aurelien Jarno <>
983fe826 04/05/2010 09:43 pm Paul Brook

ARMv7-M reset fixes

Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a board
reset routine to call this. Also load values directly from ROM as
images have not been copied yet.

Avoid clearing the NVIC pointer on cpu reset.

Signed-off-by: Paul Brook <>
52705890 03/12/2010 06:28 pm Richard Henderson

Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.

Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha. This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place....
426f5abc 11/22/2009 11:35 pm Paul Brook

ARM atomic ops rewrite

Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <>
60011498 11/19/2009 06:45 pm Paul Brook

ARM FP16 support

Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <>
10055562 11/19/2009 06:45 pm Paul Brook

ARM Cortex-A9 cpu support

Basic Cortex-A9 support.

Signed-off-by: Paul Brook <>
0b5c1ce8 08/24/2009 04:21 pm Nathan Froyd

cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal

handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations. This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets...
ffe47d33 07/31/2009 03:19 pm Paul Brook

Save/restore ARMv6 MMU state

Correctly save/restore ARMV6 MMU state.

Signed-off-by: Paul Brook <>
8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>
c2764719 03/07/2009 05:24 pm pbrook

The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications. Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.

Signed-off-by: Paul Brook <>...
84a031c6 02/07/2009 05:19 pm aurel32

Fix cpu_arm_handle_mmu_fault warning

This patch fixes:

/scratch/froydnj/qemu.git/target-arm/helper.c:451: warning: no previous prototype for 'cpu_arm_handle_mmu_fault'

by moving the declaration of the function to cpu.h from exec.h. cpu.h
seems to be the place most other ports declare the corresponding...
fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...
a49ea279 12/19/2008 03:37 pm pbrook

Implement ARMv7 cp15 cache ID registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
fe1479c3 12/19/2008 03:18 pm pbrook

Implement (very) basic Thumb2-EE support. This doesn't actually implement
EE state, just the associated system coprocessor registers. It is sufficient
to keep OS setup and context switching code happy.

Signed-off-by: Paul Brook <>
...
6b917547 11/18/2008 09:46 pm aliguori

Refactor translation block CPU state handling (Jan Kiszka)

This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()...
622ed360 11/18/2008 09:36 pm aliguori

Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)

as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
b2fa1797 10/22/2008 10:22 pm pbrook

Fix ARMv6 translation table base address calculation.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
9656f324 07/01/2008 11:01 pm pbrook

Move interrupt_request and user_mode_only to common cpu state.
Save and restore env->interrupt_request and env->halted.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
b3c7724c 06/30/2008 07:31 pm pbrook

Move CPU save/load registration to common code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
2e70f6ef 06/29/2008 04:03 am pbrook

Add instruction counter.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
f8ed7070 05/30/2008 08:54 pm pbrook

Fix typo.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
6e68e076 05/30/2008 08:22 pm pbrook

Move clone() register setup to target specific code. Handle fork-like clone.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
9133e39b 05/29/2008 01:08 pm bellard

Push common interrupt variables to cpu-defs.h (Glauber Costa)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
fbb4a2e3 05/29/2008 03:20 am pbrook

Implement ARM magic kernel page and TLS register.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4610 c046a42c-6fe2-441c-8c8c-71466251a162
ce5232c5 05/28/2008 08:14 pm bellard

moved halted field to CPU_COMMON

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
827df9f3 04/15/2008 12:05 am balrog

Add basic OMAP2 chip support.

Add the OMAP242x (arm1136 core) initialisation with basic on-chip
peripherals and update OMAP1 peripherals which are re-used in OMAP2.
Make palmte.c and sd.c errors go to stderr.
Allow disabling SD chipselect.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
f93eb9ff 04/14/2008 11:27 pm balrog

Move the excess of arm_load_kernel() parameters into a struct.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4212 c046a42c-6fe2-441c-8c8c-71466251a162
6fbe23d5 04/01/2008 08:19 pm pbrook

ARM N=Z=1 flag fix.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
4373f3ce 03/31/2008 06:47 am pbrook

ARM TCG conversion 10/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
b26eefb6 03/31/2008 06:44 am pbrook

ARM TCG conversion 1/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4138 c046a42c-6fe2-441c-8c8c-71466251a162
2f4a40e5 11/13/2007 03:50 am balrog

Prevent cpsr_write/_read be put out of line in op.o (fixes a segfault on some platforms).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3633 c046a42c-6fe2-441c-8c8c-71466251a162
9ee6e8bb 11/11/2007 02:04 am pbrook

ARMv7 support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
aaed909a 11/10/2007 05:15 pm bellard

added cpu_model parameter to cpu_init()

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
6ebbf390 10/14/2007 10:07 am j_mayer

Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions....
c732abe2 10/12/2007 09:47 am j_mayer

Unify '-cpu ?' option.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
198a74de 09/27/2007 07:44 pm ths

Move get_sp_from_cpustate from cpu.h to target_signal.h.
Enable sigaltstack processing for more architectures.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
a04e134a 09/27/2007 04:57 pm ths

linux-user sigaltstack() syscall, by Thayne Harbaugh.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162
3b46e624 09/17/2007 11:09 am ths

find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
5fafdf24 09/17/2007 12:08 am ths

find -type f | xargs sed -i 's/[\t ]$//g' # on most files

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
c3d2689d 07/29/2007 08:57 pm balrog

Basic OMAP310 support. Basic Palm Tungsten|E machine emulation.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3091 c046a42c-6fe2-441c-8c8c-71466251a162
82d17978 07/24/2007 04:07 am balrog

Various reg offset shift typos.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3085 c046a42c-6fe2-441c-8c8c-71466251a162
610c3c8a 06/24/2007 03:09 pm balrog

Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3013 c046a42c-6fe2-441c-8c8c-71466251a162
9467d44c 06/04/2007 12:02 am ths

Move target-specific defines to the target directories.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162
ce819861 05/08/2007 05:30 am pbrook

ARM946 CPU support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2783 c046a42c-6fe2-441c-8c8c-71466251a162
9d551997 04/30/2007 05:24 am balrog

Account for machine with RAM which is not mapped at 0x0 in arm_boot.c.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2757 c046a42c-6fe2-441c-8c8c-71466251a162
18c9b560 04/30/2007 05:02 am balrog

Implement iwMMXt instruction set for the PXA270 cpu.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2752 c046a42c-6fe2-441c-8c8c-71466251a162
c1713132 04/30/2007 04:26 am balrog

Core features of ARM XScale processors. Main PXA270 and PXA255 peripherals.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2749 c046a42c-6fe2-441c-8c8c-71466251a162
f3d6b95e 03/11/2007 03:03 pm pbrook

ARM reabbot support (orginal patch by Aurelien Jarno).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2476 c046a42c-6fe2-441c-8c8c-71466251a162
5adb4839 03/08/2007 05:15 am pbrook

Fix typo in help output.
List ARM cpus.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2475 c046a42c-6fe2-441c-8c8c-71466251a162
3371d272 03/08/2007 05:04 am pbrook

Implement --cpu for ARM.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2474 c046a42c-6fe2-441c-8c8c-71466251a162
5a7b542b 01/31/2007 02:16 pm ths

siginfo fix for Darwin/Mac OS X, by Pierre d'Herbemont.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2369 c046a42c-6fe2-441c-8c8c-71466251a162
9042c0e2 12/23/2006 04:18 pm ths

Check ELF binaries for machine type and endianness.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2274 c046a42c-6fe2-441c-8c8c-71466251a162
d37aca66 10/22/2006 02:54 pm pbrook

Fix comment typo.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2197 c046a42c-6fe2-441c-8c8c-71466251a162
40f137e1 02/20/2006 02:33 am pbrook

Add Arm926 core support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1765 c046a42c-6fe2-441c-8c8c-71466251a162
ce4defa0 02/09/2006 06:49 pm pbrook

Arm Linux EABI syscall support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1756 c046a42c-6fe2-441c-8c8c-71466251a162
06c949e6 02/04/2006 09:35 pm pbrook

Implement Arm BKPT instruction.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1740 c046a42c-6fe2-441c-8c8c-71466251a162
9332f9da 11/26/2005 12:46 pm bellard

ARM CPU suspend/halt (Paul Brook)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1663 c046a42c-6fe2-441c-8c8c-71466251a162
b5ff1b31 11/26/2005 12:38 pm bellard

ARM system emulation (Paul Brook)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1661 c046a42c-6fe2-441c-8c8c-71466251a162
a316d335 11/20/2005 12:32 pm bellard

added CPU_COMMON and CPUState.tb_jmp_cache[]

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1630 c046a42c-6fe2-441c-8c8c-71466251a162
1fddef4b 04/17/2005 10:16 pm bellard

gdb support for user mode (Paul Brook)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1367 c046a42c-6fe2-441c-8c8c-71466251a162
8e96005d 04/07/2005 10:42 pm bellard

VFP register ordering (Paul Brook)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1355 c046a42c-6fe2-441c-8c8c-71466251a162
53cd6637 03/13/2005 08:50 pm bellard

soft float support

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1337 c046a42c-6fe2-441c-8c8c-71466251a162
b7bcbe95 02/22/2005 09:27 pm bellard

ARM VFP support (Paul Brook)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1309 c046a42c-6fe2-441c-8c8c-71466251a162
b8a9e8f1 02/08/2005 01:10 am bellard

initial user mmu support

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1270 c046a42c-6fe2-441c-8c8c-71466251a162
99c475ab 01/31/2005 10:45 pm bellard

armv5te support (Paul Brook)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1258 c046a42c-6fe2-441c-8c8c-71466251a162
7fe48483 10/09/2004 09:08 pm bellard

monitor fixes

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1110 c046a42c-6fe2-441c-8c8c-71466251a162
d720b93d 04/25/2004 08:57 pm bellard

precise self modifying code support

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@745 c046a42c-6fe2-441c-8c8c-71466251a162
3cf1e035 01/24/2004 05:19 pm bellard

added TARGET_LONG_BITS

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@580 c046a42c-6fe2-441c-8c8c-71466251a162
2c0262af 09/30/2003 11:34 pm bellard

new directory structure

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@385 c046a42c-6fe2-441c-8c8c-71466251a162