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/*
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 *  MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support
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 *
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 *  Copyright (c) 2005 Fabrice Bellard
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 *  Copyright (c) 2008 Intel Corporation  <andrew.zaborowski@intel.com>
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#if SHIFT == 0
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#define Reg MMXReg
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#define XMM_ONLY(...)
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#define B(n) MMX_B(n)
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#define W(n) MMX_W(n)
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#define L(n) MMX_L(n)
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#define Q(n) q
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#define SUFFIX _mmx
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#else
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#define Reg XMMReg
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#define XMM_ONLY(...) __VA_ARGS__
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#define B(n) XMM_B(n)
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#define W(n) XMM_W(n)
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#define L(n) XMM_L(n)
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#define Q(n) XMM_Q(n)
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#define SUFFIX _xmm
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#endif
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void glue(helper_psrlw, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 15) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->W(0) >>= shift;
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        d->W(1) >>= shift;
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        d->W(2) >>= shift;
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        d->W(3) >>= shift;
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#if SHIFT == 1
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        d->W(4) >>= shift;
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        d->W(5) >>= shift;
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        d->W(6) >>= shift;
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        d->W(7) >>= shift;
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#endif
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    }
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}
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void glue(helper_psraw, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 15) {
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        shift = 15;
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    } else {
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        shift = s->B(0);
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    }
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    d->W(0) = (int16_t)d->W(0) >> shift;
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    d->W(1) = (int16_t)d->W(1) >> shift;
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    d->W(2) = (int16_t)d->W(2) >> shift;
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    d->W(3) = (int16_t)d->W(3) >> shift;
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#if SHIFT == 1
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    d->W(4) = (int16_t)d->W(4) >> shift;
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    d->W(5) = (int16_t)d->W(5) >> shift;
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    d->W(6) = (int16_t)d->W(6) >> shift;
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    d->W(7) = (int16_t)d->W(7) >> shift;
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#endif
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}
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void glue(helper_psllw, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 15) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->W(0) <<= shift;
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        d->W(1) <<= shift;
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        d->W(2) <<= shift;
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        d->W(3) <<= shift;
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#if SHIFT == 1
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        d->W(4) <<= shift;
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        d->W(5) <<= shift;
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        d->W(6) <<= shift;
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        d->W(7) <<= shift;
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#endif
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    }
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}
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void glue(helper_psrld, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 31) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->L(0) >>= shift;
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        d->L(1) >>= shift;
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#if SHIFT == 1
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        d->L(2) >>= shift;
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        d->L(3) >>= shift;
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#endif
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    }
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}
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void glue(helper_psrad, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 31) {
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        shift = 31;
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    } else {
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        shift = s->B(0);
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    }
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    d->L(0) = (int32_t)d->L(0) >> shift;
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    d->L(1) = (int32_t)d->L(1) >> shift;
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#if SHIFT == 1
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    d->L(2) = (int32_t)d->L(2) >> shift;
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    d->L(3) = (int32_t)d->L(3) >> shift;
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#endif
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}
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void glue(helper_pslld, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 31) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->L(0) <<= shift;
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        d->L(1) <<= shift;
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#if SHIFT == 1
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        d->L(2) <<= shift;
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        d->L(3) <<= shift;
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#endif
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    }
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}
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void glue(helper_psrlq, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 63) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->Q(0) >>= shift;
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#if SHIFT == 1
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        d->Q(1) >>= shift;
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#endif
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    }
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}
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void glue(helper_psllq, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 63) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->Q(0) <<= shift;
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#if SHIFT == 1
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        d->Q(1) <<= shift;
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#endif
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    }
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}
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#if SHIFT == 1
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void glue(helper_psrldq, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift, i;
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    shift = s->L(0);
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    if (shift > 16)
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        shift = 16;
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    for(i = 0; i < 16 - shift; i++)
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        d->B(i) = d->B(i + shift);
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    for(i = 16 - shift; i < 16; i++)
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        d->B(i) = 0;
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}
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void glue(helper_pslldq, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift, i;
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    shift = s->L(0);
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    if (shift > 16)
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        shift = 16;
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    for(i = 15; i >= shift; i--)
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        d->B(i) = d->B(i - shift);
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    for(i = 0; i < shift; i++)
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        d->B(i) = 0;
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}
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#endif
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#define SSE_HELPER_B(name, F)\
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void glue(name, SUFFIX) (Reg *d, Reg *s)\
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{\
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    d->B(0) = F(d->B(0), s->B(0));\
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    d->B(1) = F(d->B(1), s->B(1));\
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    d->B(2) = F(d->B(2), s->B(2));\
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    d->B(3) = F(d->B(3), s->B(3));\
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    d->B(4) = F(d->B(4), s->B(4));\
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    d->B(5) = F(d->B(5), s->B(5));\
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    d->B(6) = F(d->B(6), s->B(6));\
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    d->B(7) = F(d->B(7), s->B(7));\
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    XMM_ONLY(\
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    d->B(8) = F(d->B(8), s->B(8));\
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    d->B(9) = F(d->B(9), s->B(9));\
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    d->B(10) = F(d->B(10), s->B(10));\
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    d->B(11) = F(d->B(11), s->B(11));\
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    d->B(12) = F(d->B(12), s->B(12));\
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    d->B(13) = F(d->B(13), s->B(13));\
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    d->B(14) = F(d->B(14), s->B(14));\
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    d->B(15) = F(d->B(15), s->B(15));\
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    )\
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}
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#define SSE_HELPER_W(name, F)\
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void glue(name, SUFFIX) (Reg *d, Reg *s)\
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{\
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    d->W(0) = F(d->W(0), s->W(0));\
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    d->W(1) = F(d->W(1), s->W(1));\
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    d->W(2) = F(d->W(2), s->W(2));\
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    d->W(3) = F(d->W(3), s->W(3));\
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    XMM_ONLY(\
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    d->W(4) = F(d->W(4), s->W(4));\
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    d->W(5) = F(d->W(5), s->W(5));\
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    d->W(6) = F(d->W(6), s->W(6));\
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    d->W(7) = F(d->W(7), s->W(7));\
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    )\
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}
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#define SSE_HELPER_L(name, F)\
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void glue(name, SUFFIX) (Reg *d, Reg *s)\
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{\
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    d->L(0) = F(d->L(0), s->L(0));\
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    d->L(1) = F(d->L(1), s->L(1));\
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    XMM_ONLY(\
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    d->L(2) = F(d->L(2), s->L(2));\
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    d->L(3) = F(d->L(3), s->L(3));\
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    )\
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}
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#define SSE_HELPER_Q(name, F)\
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void glue(name, SUFFIX) (Reg *d, Reg *s)\
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{\
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    d->Q(0) = F(d->Q(0), s->Q(0));\
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    XMM_ONLY(\
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    d->Q(1) = F(d->Q(1), s->Q(1));\
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    )\
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}
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#if SHIFT == 0
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static inline int satub(int x)
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{
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    if (x < 0)
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        return 0;
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    else if (x > 255)
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        return 255;
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    else
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        return x;
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}
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static inline int satuw(int x)
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{
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    if (x < 0)
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        return 0;
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    else if (x > 65535)
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        return 65535;
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    else
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        return x;
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}
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static inline int satsb(int x)
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{
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    if (x < -128)
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        return -128;
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    else if (x > 127)
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        return 127;
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    else
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        return x;
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}
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static inline int satsw(int x)
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{
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    if (x < -32768)
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        return -32768;
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    else if (x > 32767)
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        return 32767;
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    else
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        return x;
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}
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#define FADD(a, b) ((a) + (b))
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#define FADDUB(a, b) satub((a) + (b))
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#define FADDUW(a, b) satuw((a) + (b))
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#define FADDSB(a, b) satsb((int8_t)(a) + (int8_t)(b))
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#define FADDSW(a, b) satsw((int16_t)(a) + (int16_t)(b))
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#define FSUB(a, b) ((a) - (b))
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#define FSUBUB(a, b) satub((a) - (b))
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#define FSUBUW(a, b) satuw((a) - (b))
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#define FSUBSB(a, b) satsb((int8_t)(a) - (int8_t)(b))
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#define FSUBSW(a, b) satsw((int16_t)(a) - (int16_t)(b))
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#define FMINUB(a, b) ((a) < (b)) ? (a) : (b)
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#define FMINSW(a, b) ((int16_t)(a) < (int16_t)(b)) ? (a) : (b)
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#define FMAXUB(a, b) ((a) > (b)) ? (a) : (b)
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#define FMAXSW(a, b) ((int16_t)(a) > (int16_t)(b)) ? (a) : (b)
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#define FAND(a, b) (a) & (b)
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#define FANDN(a, b) ((~(a)) & (b))
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#define FOR(a, b) (a) | (b)
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#define FXOR(a, b) (a) ^ (b)
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#define FCMPGTB(a, b) (int8_t)(a) > (int8_t)(b) ? -1 : 0
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#define FCMPGTW(a, b) (int16_t)(a) > (int16_t)(b) ? -1 : 0
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#define FCMPGTL(a, b) (int32_t)(a) > (int32_t)(b) ? -1 : 0
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#define FCMPEQ(a, b) (a) == (b) ? -1 : 0
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#define FMULLW(a, b) (a) * (b)
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#define FMULHRW(a, b) ((int16_t)(a) * (int16_t)(b) + 0x8000) >> 16
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#define FMULHUW(a, b) (a) * (b) >> 16
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#define FMULHW(a, b) (int16_t)(a) * (int16_t)(b) >> 16
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#define FAVG(a, b) ((a) + (b) + 1) >> 1
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#endif
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SSE_HELPER_B(helper_paddb, FADD)
362 5af45186 bellard
SSE_HELPER_W(helper_paddw, FADD)
363 5af45186 bellard
SSE_HELPER_L(helper_paddl, FADD)
364 5af45186 bellard
SSE_HELPER_Q(helper_paddq, FADD)
365 664e0f19 bellard
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SSE_HELPER_B(helper_psubb, FSUB)
367 5af45186 bellard
SSE_HELPER_W(helper_psubw, FSUB)
368 5af45186 bellard
SSE_HELPER_L(helper_psubl, FSUB)
369 5af45186 bellard
SSE_HELPER_Q(helper_psubq, FSUB)
370 664e0f19 bellard
371 5af45186 bellard
SSE_HELPER_B(helper_paddusb, FADDUB)
372 5af45186 bellard
SSE_HELPER_B(helper_paddsb, FADDSB)
373 5af45186 bellard
SSE_HELPER_B(helper_psubusb, FSUBUB)
374 5af45186 bellard
SSE_HELPER_B(helper_psubsb, FSUBSB)
375 664e0f19 bellard
376 5af45186 bellard
SSE_HELPER_W(helper_paddusw, FADDUW)
377 5af45186 bellard
SSE_HELPER_W(helper_paddsw, FADDSW)
378 5af45186 bellard
SSE_HELPER_W(helper_psubusw, FSUBUW)
379 5af45186 bellard
SSE_HELPER_W(helper_psubsw, FSUBSW)
380 664e0f19 bellard
381 5af45186 bellard
SSE_HELPER_B(helper_pminub, FMINUB)
382 5af45186 bellard
SSE_HELPER_B(helper_pmaxub, FMAXUB)
383 664e0f19 bellard
384 5af45186 bellard
SSE_HELPER_W(helper_pminsw, FMINSW)
385 5af45186 bellard
SSE_HELPER_W(helper_pmaxsw, FMAXSW)
386 664e0f19 bellard
387 5af45186 bellard
SSE_HELPER_Q(helper_pand, FAND)
388 5af45186 bellard
SSE_HELPER_Q(helper_pandn, FANDN)
389 5af45186 bellard
SSE_HELPER_Q(helper_por, FOR)
390 5af45186 bellard
SSE_HELPER_Q(helper_pxor, FXOR)
391 664e0f19 bellard
392 5af45186 bellard
SSE_HELPER_B(helper_pcmpgtb, FCMPGTB)
393 5af45186 bellard
SSE_HELPER_W(helper_pcmpgtw, FCMPGTW)
394 5af45186 bellard
SSE_HELPER_L(helper_pcmpgtl, FCMPGTL)
395 664e0f19 bellard
396 5af45186 bellard
SSE_HELPER_B(helper_pcmpeqb, FCMPEQ)
397 5af45186 bellard
SSE_HELPER_W(helper_pcmpeqw, FCMPEQ)
398 5af45186 bellard
SSE_HELPER_L(helper_pcmpeql, FCMPEQ)
399 664e0f19 bellard
400 5af45186 bellard
SSE_HELPER_W(helper_pmullw, FMULLW)
401 a35f3ec7 aurel32
#if SHIFT == 0
402 5af45186 bellard
SSE_HELPER_W(helper_pmulhrw, FMULHRW)
403 a35f3ec7 aurel32
#endif
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SSE_HELPER_W(helper_pmulhuw, FMULHUW)
405 5af45186 bellard
SSE_HELPER_W(helper_pmulhw, FMULHW)
406 664e0f19 bellard
407 5af45186 bellard
SSE_HELPER_B(helper_pavgb, FAVG)
408 5af45186 bellard
SSE_HELPER_W(helper_pavgw, FAVG)
409 664e0f19 bellard
410 5af45186 bellard
void glue(helper_pmuludq, SUFFIX) (Reg *d, Reg *s)
411 664e0f19 bellard
{
412 664e0f19 bellard
    d->Q(0) = (uint64_t)s->L(0) * (uint64_t)d->L(0);
413 664e0f19 bellard
#if SHIFT == 1
414 664e0f19 bellard
    d->Q(1) = (uint64_t)s->L(2) * (uint64_t)d->L(2);
415 664e0f19 bellard
#endif
416 664e0f19 bellard
}
417 664e0f19 bellard
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void glue(helper_pmaddwd, SUFFIX) (Reg *d, Reg *s)
419 664e0f19 bellard
{
420 664e0f19 bellard
    int i;
421 664e0f19 bellard
422 664e0f19 bellard
    for(i = 0; i < (2 << SHIFT); i++) {
423 664e0f19 bellard
        d->L(i) = (int16_t)s->W(2*i) * (int16_t)d->W(2*i) +
424 664e0f19 bellard
            (int16_t)s->W(2*i+1) * (int16_t)d->W(2*i+1);
425 664e0f19 bellard
    }
426 664e0f19 bellard
}
427 664e0f19 bellard
428 664e0f19 bellard
#if SHIFT == 0
429 664e0f19 bellard
static inline int abs1(int a)
430 664e0f19 bellard
{
431 664e0f19 bellard
    if (a < 0)
432 664e0f19 bellard
        return -a;
433 664e0f19 bellard
    else
434 664e0f19 bellard
        return a;
435 664e0f19 bellard
}
436 664e0f19 bellard
#endif
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void glue(helper_psadbw, SUFFIX) (Reg *d, Reg *s)
438 664e0f19 bellard
{
439 664e0f19 bellard
    unsigned int val;
440 664e0f19 bellard
441 664e0f19 bellard
    val = 0;
442 664e0f19 bellard
    val += abs1(d->B(0) - s->B(0));
443 664e0f19 bellard
    val += abs1(d->B(1) - s->B(1));
444 664e0f19 bellard
    val += abs1(d->B(2) - s->B(2));
445 664e0f19 bellard
    val += abs1(d->B(3) - s->B(3));
446 664e0f19 bellard
    val += abs1(d->B(4) - s->B(4));
447 664e0f19 bellard
    val += abs1(d->B(5) - s->B(5));
448 664e0f19 bellard
    val += abs1(d->B(6) - s->B(6));
449 664e0f19 bellard
    val += abs1(d->B(7) - s->B(7));
450 664e0f19 bellard
    d->Q(0) = val;
451 664e0f19 bellard
#if SHIFT == 1
452 664e0f19 bellard
    val = 0;
453 664e0f19 bellard
    val += abs1(d->B(8) - s->B(8));
454 664e0f19 bellard
    val += abs1(d->B(9) - s->B(9));
455 664e0f19 bellard
    val += abs1(d->B(10) - s->B(10));
456 664e0f19 bellard
    val += abs1(d->B(11) - s->B(11));
457 664e0f19 bellard
    val += abs1(d->B(12) - s->B(12));
458 664e0f19 bellard
    val += abs1(d->B(13) - s->B(13));
459 664e0f19 bellard
    val += abs1(d->B(14) - s->B(14));
460 664e0f19 bellard
    val += abs1(d->B(15) - s->B(15));
461 664e0f19 bellard
    d->Q(1) = val;
462 664e0f19 bellard
#endif
463 664e0f19 bellard
}
464 664e0f19 bellard
465 b8b6a50b bellard
void glue(helper_maskmov, SUFFIX) (Reg *d, Reg *s, target_ulong a0)
466 664e0f19 bellard
{
467 664e0f19 bellard
    int i;
468 664e0f19 bellard
    for(i = 0; i < (8 << SHIFT); i++) {
469 664e0f19 bellard
        if (s->B(i) & 0x80)
470 b8b6a50b bellard
            stb(a0 + i, d->B(i));
471 664e0f19 bellard
    }
472 664e0f19 bellard
}
473 664e0f19 bellard
474 5af45186 bellard
void glue(helper_movl_mm_T0, SUFFIX) (Reg *d, uint32_t val)
475 664e0f19 bellard
{
476 5af45186 bellard
    d->L(0) = val;
477 664e0f19 bellard
    d->L(1) = 0;
478 664e0f19 bellard
#if SHIFT == 1
479 664e0f19 bellard
    d->Q(1) = 0;
480 664e0f19 bellard
#endif
481 664e0f19 bellard
}
482 664e0f19 bellard
483 dabd98dd bellard
#ifdef TARGET_X86_64
484 5af45186 bellard
void glue(helper_movq_mm_T0, SUFFIX) (Reg *d, uint64_t val)
485 dabd98dd bellard
{
486 5af45186 bellard
    d->Q(0) = val;
487 dabd98dd bellard
#if SHIFT == 1
488 dabd98dd bellard
    d->Q(1) = 0;
489 dabd98dd bellard
#endif
490 dabd98dd bellard
}
491 dabd98dd bellard
#endif
492 dabd98dd bellard
493 664e0f19 bellard
#if SHIFT == 0
494 5af45186 bellard
void glue(helper_pshufw, SUFFIX) (Reg *d, Reg *s, int order)
495 664e0f19 bellard
{
496 5af45186 bellard
    Reg r;
497 664e0f19 bellard
    r.W(0) = s->W(order & 3);
498 664e0f19 bellard
    r.W(1) = s->W((order >> 2) & 3);
499 664e0f19 bellard
    r.W(2) = s->W((order >> 4) & 3);
500 664e0f19 bellard
    r.W(3) = s->W((order >> 6) & 3);
501 664e0f19 bellard
    *d = r;
502 664e0f19 bellard
}
503 664e0f19 bellard
#else
504 5af45186 bellard
void helper_shufps(Reg *d, Reg *s, int order)
505 d52cf7a6 bellard
{
506 5af45186 bellard
    Reg r;
507 d52cf7a6 bellard
    r.L(0) = d->L(order & 3);
508 d52cf7a6 bellard
    r.L(1) = d->L((order >> 2) & 3);
509 d52cf7a6 bellard
    r.L(2) = s->L((order >> 4) & 3);
510 d52cf7a6 bellard
    r.L(3) = s->L((order >> 6) & 3);
511 d52cf7a6 bellard
    *d = r;
512 d52cf7a6 bellard
}
513 d52cf7a6 bellard
514 5af45186 bellard
void helper_shufpd(Reg *d, Reg *s, int order)
515 664e0f19 bellard
{
516 5af45186 bellard
    Reg r;
517 d52cf7a6 bellard
    r.Q(0) = d->Q(order & 1);
518 664e0f19 bellard
    r.Q(1) = s->Q((order >> 1) & 1);
519 664e0f19 bellard
    *d = r;
520 664e0f19 bellard
}
521 664e0f19 bellard
522 5af45186 bellard
void glue(helper_pshufd, SUFFIX) (Reg *d, Reg *s, int order)
523 664e0f19 bellard
{
524 5af45186 bellard
    Reg r;
525 664e0f19 bellard
    r.L(0) = s->L(order & 3);
526 664e0f19 bellard
    r.L(1) = s->L((order >> 2) & 3);
527 664e0f19 bellard
    r.L(2) = s->L((order >> 4) & 3);
528 664e0f19 bellard
    r.L(3) = s->L((order >> 6) & 3);
529 664e0f19 bellard
    *d = r;
530 664e0f19 bellard
}
531 664e0f19 bellard
532 5af45186 bellard
void glue(helper_pshuflw, SUFFIX) (Reg *d, Reg *s, int order)
533 664e0f19 bellard
{
534 5af45186 bellard
    Reg r;
535 664e0f19 bellard
    r.W(0) = s->W(order & 3);
536 664e0f19 bellard
    r.W(1) = s->W((order >> 2) & 3);
537 664e0f19 bellard
    r.W(2) = s->W((order >> 4) & 3);
538 664e0f19 bellard
    r.W(3) = s->W((order >> 6) & 3);
539 664e0f19 bellard
    r.Q(1) = s->Q(1);
540 664e0f19 bellard
    *d = r;
541 664e0f19 bellard
}
542 664e0f19 bellard
543 5af45186 bellard
void glue(helper_pshufhw, SUFFIX) (Reg *d, Reg *s, int order)
544 664e0f19 bellard
{
545 5af45186 bellard
    Reg r;
546 664e0f19 bellard
    r.Q(0) = s->Q(0);
547 664e0f19 bellard
    r.W(4) = s->W(4 + (order & 3));
548 664e0f19 bellard
    r.W(5) = s->W(4 + ((order >> 2) & 3));
549 664e0f19 bellard
    r.W(6) = s->W(4 + ((order >> 4) & 3));
550 664e0f19 bellard
    r.W(7) = s->W(4 + ((order >> 6) & 3));
551 664e0f19 bellard
    *d = r;
552 664e0f19 bellard
}
553 664e0f19 bellard
#endif
554 664e0f19 bellard
555 664e0f19 bellard
#if SHIFT == 1
556 664e0f19 bellard
/* FPU ops */
557 664e0f19 bellard
/* XXX: not accurate */
558 664e0f19 bellard
559 5af45186 bellard
#define SSE_HELPER_S(name, F)\
560 5af45186 bellard
void helper_ ## name ## ps (Reg *d, Reg *s)\
561 664e0f19 bellard
{\
562 7a0e1f41 bellard
    d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
563 7a0e1f41 bellard
    d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1));\
564 7a0e1f41 bellard
    d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2));\
565 7a0e1f41 bellard
    d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3));\
566 664e0f19 bellard
}\
567 664e0f19 bellard
\
568 5af45186 bellard
void helper_ ## name ## ss (Reg *d, Reg *s)\
569 664e0f19 bellard
{\
570 7a0e1f41 bellard
    d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
571 664e0f19 bellard
}\
572 5af45186 bellard
void helper_ ## name ## pd (Reg *d, Reg *s)\
573 664e0f19 bellard
{\
574 7a0e1f41 bellard
    d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
575 7a0e1f41 bellard
    d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1));\
576 664e0f19 bellard
}\
577 664e0f19 bellard
\
578 5af45186 bellard
void helper_ ## name ## sd (Reg *d, Reg *s)\
579 664e0f19 bellard
{\
580 7a0e1f41 bellard
    d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
581 664e0f19 bellard
}
582 664e0f19 bellard
583 7a0e1f41 bellard
#define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status)
584 7a0e1f41 bellard
#define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status)
585 7a0e1f41 bellard
#define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status)
586 7a0e1f41 bellard
#define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status)
587 7a0e1f41 bellard
#define FPU_MIN(size, a, b) (a) < (b) ? (a) : (b)
588 7a0e1f41 bellard
#define FPU_MAX(size, a, b) (a) > (b) ? (a) : (b)
589 7a0e1f41 bellard
#define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status)
590 664e0f19 bellard
591 5af45186 bellard
SSE_HELPER_S(add, FPU_ADD)
592 5af45186 bellard
SSE_HELPER_S(sub, FPU_SUB)
593 5af45186 bellard
SSE_HELPER_S(mul, FPU_MUL)
594 5af45186 bellard
SSE_HELPER_S(div, FPU_DIV)
595 5af45186 bellard
SSE_HELPER_S(min, FPU_MIN)
596 5af45186 bellard
SSE_HELPER_S(max, FPU_MAX)
597 5af45186 bellard
SSE_HELPER_S(sqrt, FPU_SQRT)
598 664e0f19 bellard
599 664e0f19 bellard
600 664e0f19 bellard
/* float to float conversions */
601 5af45186 bellard
void helper_cvtps2pd(Reg *d, Reg *s)
602 664e0f19 bellard
{
603 8422b113 bellard
    float32 s0, s1;
604 664e0f19 bellard
    s0 = s->XMM_S(0);
605 664e0f19 bellard
    s1 = s->XMM_S(1);
606 7a0e1f41 bellard
    d->XMM_D(0) = float32_to_float64(s0, &env->sse_status);
607 7a0e1f41 bellard
    d->XMM_D(1) = float32_to_float64(s1, &env->sse_status);
608 664e0f19 bellard
}
609 664e0f19 bellard
610 5af45186 bellard
void helper_cvtpd2ps(Reg *d, Reg *s)
611 664e0f19 bellard
{
612 7a0e1f41 bellard
    d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
613 7a0e1f41 bellard
    d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status);
614 664e0f19 bellard
    d->Q(1) = 0;
615 664e0f19 bellard
}
616 664e0f19 bellard
617 5af45186 bellard
void helper_cvtss2sd(Reg *d, Reg *s)
618 664e0f19 bellard
{
619 7a0e1f41 bellard
    d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status);
620 664e0f19 bellard
}
621 664e0f19 bellard
622 5af45186 bellard
void helper_cvtsd2ss(Reg *d, Reg *s)
623 664e0f19 bellard
{
624 7a0e1f41 bellard
    d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
625 664e0f19 bellard
}
626 664e0f19 bellard
627 664e0f19 bellard
/* integer to float */
628 5af45186 bellard
void helper_cvtdq2ps(Reg *d, Reg *s)
629 664e0f19 bellard
{
630 7a0e1f41 bellard
    d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status);
631 7a0e1f41 bellard
    d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status);
632 7a0e1f41 bellard
    d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status);
633 7a0e1f41 bellard
    d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status);
634 664e0f19 bellard
}
635 664e0f19 bellard
636 5af45186 bellard
void helper_cvtdq2pd(Reg *d, Reg *s)
637 664e0f19 bellard
{
638 664e0f19 bellard
    int32_t l0, l1;
639 664e0f19 bellard
    l0 = (int32_t)s->XMM_L(0);
640 664e0f19 bellard
    l1 = (int32_t)s->XMM_L(1);
641 7a0e1f41 bellard
    d->XMM_D(0) = int32_to_float64(l0, &env->sse_status);
642 7a0e1f41 bellard
    d->XMM_D(1) = int32_to_float64(l1, &env->sse_status);
643 664e0f19 bellard
}
644 664e0f19 bellard
645 5af45186 bellard
void helper_cvtpi2ps(XMMReg *d, MMXReg *s)
646 664e0f19 bellard
{
647 7a0e1f41 bellard
    d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status);
648 7a0e1f41 bellard
    d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status);
649 664e0f19 bellard
}
650 664e0f19 bellard
651 5af45186 bellard
void helper_cvtpi2pd(XMMReg *d, MMXReg *s)
652 664e0f19 bellard
{
653 7a0e1f41 bellard
    d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status);
654 7a0e1f41 bellard
    d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status);
655 664e0f19 bellard
}
656 664e0f19 bellard
657 5af45186 bellard
void helper_cvtsi2ss(XMMReg *d, uint32_t val)
658 664e0f19 bellard
{
659 5af45186 bellard
    d->XMM_S(0) = int32_to_float32(val, &env->sse_status);
660 664e0f19 bellard
}
661 664e0f19 bellard
662 5af45186 bellard
void helper_cvtsi2sd(XMMReg *d, uint32_t val)
663 664e0f19 bellard
{
664 5af45186 bellard
    d->XMM_D(0) = int32_to_float64(val, &env->sse_status);
665 664e0f19 bellard
}
666 664e0f19 bellard
667 664e0f19 bellard
#ifdef TARGET_X86_64
668 5af45186 bellard
void helper_cvtsq2ss(XMMReg *d, uint64_t val)
669 664e0f19 bellard
{
670 5af45186 bellard
    d->XMM_S(0) = int64_to_float32(val, &env->sse_status);
671 664e0f19 bellard
}
672 664e0f19 bellard
673 5af45186 bellard
void helper_cvtsq2sd(XMMReg *d, uint64_t val)
674 664e0f19 bellard
{
675 5af45186 bellard
    d->XMM_D(0) = int64_to_float64(val, &env->sse_status);
676 664e0f19 bellard
}
677 664e0f19 bellard
#endif
678 664e0f19 bellard
679 664e0f19 bellard
/* float to integer */
680 5af45186 bellard
void helper_cvtps2dq(XMMReg *d, XMMReg *s)
681 664e0f19 bellard
{
682 7a0e1f41 bellard
    d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
683 7a0e1f41 bellard
    d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
684 7a0e1f41 bellard
    d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status);
685 7a0e1f41 bellard
    d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status);
686 664e0f19 bellard
}
687 664e0f19 bellard
688 5af45186 bellard
void helper_cvtpd2dq(XMMReg *d, XMMReg *s)
689 664e0f19 bellard
{
690 7a0e1f41 bellard
    d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
691 7a0e1f41 bellard
    d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
692 664e0f19 bellard
    d->XMM_Q(1) = 0;
693 664e0f19 bellard
}
694 664e0f19 bellard
695 5af45186 bellard
void helper_cvtps2pi(MMXReg *d, XMMReg *s)
696 664e0f19 bellard
{
697 7a0e1f41 bellard
    d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
698 7a0e1f41 bellard
    d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
699 664e0f19 bellard
}
700 664e0f19 bellard
701 5af45186 bellard
void helper_cvtpd2pi(MMXReg *d, XMMReg *s)
702 664e0f19 bellard
{
703 7a0e1f41 bellard
    d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
704 7a0e1f41 bellard
    d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
705 664e0f19 bellard
}
706 664e0f19 bellard
707 5af45186 bellard
int32_t helper_cvtss2si(XMMReg *s)
708 664e0f19 bellard
{
709 5af45186 bellard
    return float32_to_int32(s->XMM_S(0), &env->sse_status);
710 664e0f19 bellard
}
711 664e0f19 bellard
712 5af45186 bellard
int32_t helper_cvtsd2si(XMMReg *s)
713 664e0f19 bellard
{
714 5af45186 bellard
    return float64_to_int32(s->XMM_D(0), &env->sse_status);
715 664e0f19 bellard
}
716 664e0f19 bellard
717 664e0f19 bellard
#ifdef TARGET_X86_64
718 5af45186 bellard
int64_t helper_cvtss2sq(XMMReg *s)
719 664e0f19 bellard
{
720 5af45186 bellard
    return float32_to_int64(s->XMM_S(0), &env->sse_status);
721 664e0f19 bellard
}
722 664e0f19 bellard
723 5af45186 bellard
int64_t helper_cvtsd2sq(XMMReg *s)
724 664e0f19 bellard
{
725 5af45186 bellard
    return float64_to_int64(s->XMM_D(0), &env->sse_status);
726 664e0f19 bellard
}
727 664e0f19 bellard
#endif
728 664e0f19 bellard
729 664e0f19 bellard
/* float to integer truncated */
730 5af45186 bellard
void helper_cvttps2dq(XMMReg *d, XMMReg *s)
731 664e0f19 bellard
{
732 7a0e1f41 bellard
    d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
733 7a0e1f41 bellard
    d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
734 7a0e1f41 bellard
    d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status);
735 7a0e1f41 bellard
    d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status);
736 664e0f19 bellard
}
737 664e0f19 bellard
738 5af45186 bellard
void helper_cvttpd2dq(XMMReg *d, XMMReg *s)
739 664e0f19 bellard
{
740 7a0e1f41 bellard
    d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
741 7a0e1f41 bellard
    d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
742 664e0f19 bellard
    d->XMM_Q(1) = 0;
743 664e0f19 bellard
}
744 664e0f19 bellard
745 5af45186 bellard
void helper_cvttps2pi(MMXReg *d, XMMReg *s)
746 664e0f19 bellard
{
747 7a0e1f41 bellard
    d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
748 7a0e1f41 bellard
    d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
749 664e0f19 bellard
}
750 664e0f19 bellard
751 5af45186 bellard
void helper_cvttpd2pi(MMXReg *d, XMMReg *s)
752 664e0f19 bellard
{
753 7a0e1f41 bellard
    d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
754 7a0e1f41 bellard
    d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
755 664e0f19 bellard
}
756 664e0f19 bellard
757 5af45186 bellard
int32_t helper_cvttss2si(XMMReg *s)
758 664e0f19 bellard
{
759 5af45186 bellard
    return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
760 664e0f19 bellard
}
761 664e0f19 bellard
762 5af45186 bellard
int32_t helper_cvttsd2si(XMMReg *s)
763 664e0f19 bellard
{
764 5af45186 bellard
    return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
765 664e0f19 bellard
}
766 664e0f19 bellard
767 664e0f19 bellard
#ifdef TARGET_X86_64
768 5af45186 bellard
int64_t helper_cvttss2sq(XMMReg *s)
769 664e0f19 bellard
{
770 5af45186 bellard
    return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status);
771 664e0f19 bellard
}
772 664e0f19 bellard
773 5af45186 bellard
int64_t helper_cvttsd2sq(XMMReg *s)
774 664e0f19 bellard
{
775 5af45186 bellard
    return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status);
776 664e0f19 bellard
}
777 664e0f19 bellard
#endif
778 664e0f19 bellard
779 5af45186 bellard
void helper_rsqrtps(XMMReg *d, XMMReg *s)
780 664e0f19 bellard
{
781 664e0f19 bellard
    d->XMM_S(0) = approx_rsqrt(s->XMM_S(0));
782 664e0f19 bellard
    d->XMM_S(1) = approx_rsqrt(s->XMM_S(1));
783 664e0f19 bellard
    d->XMM_S(2) = approx_rsqrt(s->XMM_S(2));
784 664e0f19 bellard
    d->XMM_S(3) = approx_rsqrt(s->XMM_S(3));
785 664e0f19 bellard
}
786 664e0f19 bellard
787 5af45186 bellard
void helper_rsqrtss(XMMReg *d, XMMReg *s)
788 664e0f19 bellard
{
789 664e0f19 bellard
    d->XMM_S(0) = approx_rsqrt(s->XMM_S(0));
790 664e0f19 bellard
}
791 664e0f19 bellard
792 5af45186 bellard
void helper_rcpps(XMMReg *d, XMMReg *s)
793 664e0f19 bellard
{
794 664e0f19 bellard
    d->XMM_S(0) = approx_rcp(s->XMM_S(0));
795 664e0f19 bellard
    d->XMM_S(1) = approx_rcp(s->XMM_S(1));
796 664e0f19 bellard
    d->XMM_S(2) = approx_rcp(s->XMM_S(2));
797 664e0f19 bellard
    d->XMM_S(3) = approx_rcp(s->XMM_S(3));
798 664e0f19 bellard
}
799 664e0f19 bellard
800 5af45186 bellard
void helper_rcpss(XMMReg *d, XMMReg *s)
801 664e0f19 bellard
{
802 664e0f19 bellard
    d->XMM_S(0) = approx_rcp(s->XMM_S(0));
803 664e0f19 bellard
}
804 664e0f19 bellard
805 d9f4bb27 Andre Przywara
static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
806 d9f4bb27 Andre Przywara
{
807 d9f4bb27 Andre Przywara
    uint64_t mask;
808 d9f4bb27 Andre Przywara
809 d9f4bb27 Andre Przywara
    if (len == 0) {
810 d9f4bb27 Andre Przywara
        mask = ~0LL;
811 d9f4bb27 Andre Przywara
    } else {
812 d9f4bb27 Andre Przywara
        mask = (1ULL << len) - 1;
813 d9f4bb27 Andre Przywara
    }
814 d9f4bb27 Andre Przywara
    return (src >> shift) & mask;
815 d9f4bb27 Andre Przywara
}
816 d9f4bb27 Andre Przywara
817 d9f4bb27 Andre Przywara
void helper_extrq_r(XMMReg *d, XMMReg *s)
818 d9f4bb27 Andre Przywara
{
819 d9f4bb27 Andre Przywara
    d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0));
820 d9f4bb27 Andre Przywara
}
821 d9f4bb27 Andre Przywara
822 d9f4bb27 Andre Przywara
void helper_extrq_i(XMMReg *d, int index, int length)
823 d9f4bb27 Andre Przywara
{
824 d9f4bb27 Andre Przywara
    d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length);
825 d9f4bb27 Andre Przywara
}
826 d9f4bb27 Andre Przywara
827 d9f4bb27 Andre Przywara
static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
828 d9f4bb27 Andre Przywara
{
829 d9f4bb27 Andre Przywara
    uint64_t mask;
830 d9f4bb27 Andre Przywara
831 d9f4bb27 Andre Przywara
    if (len == 0) {
832 d9f4bb27 Andre Przywara
        mask = ~0ULL;
833 d9f4bb27 Andre Przywara
    } else {
834 d9f4bb27 Andre Przywara
        mask = (1ULL << len) - 1;
835 d9f4bb27 Andre Przywara
    }
836 d9f4bb27 Andre Przywara
    return (src & ~(mask << shift)) | ((src & mask) << shift);
837 d9f4bb27 Andre Przywara
}
838 d9f4bb27 Andre Przywara
839 d9f4bb27 Andre Przywara
void helper_insertq_r(XMMReg *d, XMMReg *s)
840 d9f4bb27 Andre Przywara
{
841 d9f4bb27 Andre Przywara
    d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8));
842 d9f4bb27 Andre Przywara
}
843 d9f4bb27 Andre Przywara
844 d9f4bb27 Andre Przywara
void helper_insertq_i(XMMReg *d, int index, int length)
845 d9f4bb27 Andre Przywara
{
846 d9f4bb27 Andre Przywara
    d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length);
847 d9f4bb27 Andre Przywara
}
848 d9f4bb27 Andre Przywara
849 5af45186 bellard
void helper_haddps(XMMReg *d, XMMReg *s)
850 664e0f19 bellard
{
851 664e0f19 bellard
    XMMReg r;
852 664e0f19 bellard
    r.XMM_S(0) = d->XMM_S(0) + d->XMM_S(1);
853 664e0f19 bellard
    r.XMM_S(1) = d->XMM_S(2) + d->XMM_S(3);
854 664e0f19 bellard
    r.XMM_S(2) = s->XMM_S(0) + s->XMM_S(1);
855 664e0f19 bellard
    r.XMM_S(3) = s->XMM_S(2) + s->XMM_S(3);
856 664e0f19 bellard
    *d = r;
857 664e0f19 bellard
}
858 664e0f19 bellard
859 5af45186 bellard
void helper_haddpd(XMMReg *d, XMMReg *s)
860 664e0f19 bellard
{
861 664e0f19 bellard
    XMMReg r;
862 664e0f19 bellard
    r.XMM_D(0) = d->XMM_D(0) + d->XMM_D(1);
863 664e0f19 bellard
    r.XMM_D(1) = s->XMM_D(0) + s->XMM_D(1);
864 664e0f19 bellard
    *d = r;
865 664e0f19 bellard
}
866 664e0f19 bellard
867 5af45186 bellard
void helper_hsubps(XMMReg *d, XMMReg *s)
868 664e0f19 bellard
{
869 664e0f19 bellard
    XMMReg r;
870 664e0f19 bellard
    r.XMM_S(0) = d->XMM_S(0) - d->XMM_S(1);
871 664e0f19 bellard
    r.XMM_S(1) = d->XMM_S(2) - d->XMM_S(3);
872 664e0f19 bellard
    r.XMM_S(2) = s->XMM_S(0) - s->XMM_S(1);
873 664e0f19 bellard
    r.XMM_S(3) = s->XMM_S(2) - s->XMM_S(3);
874 664e0f19 bellard
    *d = r;
875 664e0f19 bellard
}
876 664e0f19 bellard
877 5af45186 bellard
void helper_hsubpd(XMMReg *d, XMMReg *s)
878 664e0f19 bellard
{
879 664e0f19 bellard
    XMMReg r;
880 664e0f19 bellard
    r.XMM_D(0) = d->XMM_D(0) - d->XMM_D(1);
881 664e0f19 bellard
    r.XMM_D(1) = s->XMM_D(0) - s->XMM_D(1);
882 664e0f19 bellard
    *d = r;
883 664e0f19 bellard
}
884 664e0f19 bellard
885 5af45186 bellard
void helper_addsubps(XMMReg *d, XMMReg *s)
886 664e0f19 bellard
{
887 664e0f19 bellard
    d->XMM_S(0) = d->XMM_S(0) - s->XMM_S(0);
888 664e0f19 bellard
    d->XMM_S(1) = d->XMM_S(1) + s->XMM_S(1);
889 664e0f19 bellard
    d->XMM_S(2) = d->XMM_S(2) - s->XMM_S(2);
890 664e0f19 bellard
    d->XMM_S(3) = d->XMM_S(3) + s->XMM_S(3);
891 664e0f19 bellard
}
892 664e0f19 bellard
893 5af45186 bellard
void helper_addsubpd(XMMReg *d, XMMReg *s)
894 664e0f19 bellard
{
895 664e0f19 bellard
    d->XMM_D(0) = d->XMM_D(0) - s->XMM_D(0);
896 664e0f19 bellard
    d->XMM_D(1) = d->XMM_D(1) + s->XMM_D(1);
897 664e0f19 bellard
}
898 664e0f19 bellard
899 664e0f19 bellard
/* XXX: unordered */
900 5af45186 bellard
#define SSE_HELPER_CMP(name, F)\
901 5af45186 bellard
void helper_ ## name ## ps (Reg *d, Reg *s)\
902 664e0f19 bellard
{\
903 8422b113 bellard
    d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
904 8422b113 bellard
    d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1));\
905 8422b113 bellard
    d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2));\
906 8422b113 bellard
    d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3));\
907 664e0f19 bellard
}\
908 664e0f19 bellard
\
909 5af45186 bellard
void helper_ ## name ## ss (Reg *d, Reg *s)\
910 664e0f19 bellard
{\
911 8422b113 bellard
    d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
912 664e0f19 bellard
}\
913 5af45186 bellard
void helper_ ## name ## pd (Reg *d, Reg *s)\
914 664e0f19 bellard
{\
915 8422b113 bellard
    d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
916 8422b113 bellard
    d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1));\
917 664e0f19 bellard
}\
918 664e0f19 bellard
\
919 5af45186 bellard
void helper_ ## name ## sd (Reg *d, Reg *s)\
920 664e0f19 bellard
{\
921 8422b113 bellard
    d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
922 664e0f19 bellard
}
923 664e0f19 bellard
924 8422b113 bellard
#define FPU_CMPEQ(size, a, b) float ## size ## _eq(a, b, &env->sse_status) ? -1 : 0
925 8422b113 bellard
#define FPU_CMPLT(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? -1 : 0
926 8422b113 bellard
#define FPU_CMPLE(size, a, b) float ## size ## _le(a, b, &env->sse_status) ? -1 : 0
927 8422b113 bellard
#define FPU_CMPUNORD(size, a, b) float ## size ## _unordered(a, b, &env->sse_status) ? - 1 : 0
928 8422b113 bellard
#define FPU_CMPNEQ(size, a, b) float ## size ## _eq(a, b, &env->sse_status) ? 0 : -1
929 8422b113 bellard
#define FPU_CMPNLT(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? 0 : -1
930 8422b113 bellard
#define FPU_CMPNLE(size, a, b) float ## size ## _le(a, b, &env->sse_status) ? 0 : -1
931 8422b113 bellard
#define FPU_CMPORD(size, a, b) float ## size ## _unordered(a, b, &env->sse_status) ? 0 : -1
932 664e0f19 bellard
933 5af45186 bellard
SSE_HELPER_CMP(cmpeq, FPU_CMPEQ)
934 5af45186 bellard
SSE_HELPER_CMP(cmplt, FPU_CMPLT)
935 5af45186 bellard
SSE_HELPER_CMP(cmple, FPU_CMPLE)
936 5af45186 bellard
SSE_HELPER_CMP(cmpunord, FPU_CMPUNORD)
937 5af45186 bellard
SSE_HELPER_CMP(cmpneq, FPU_CMPNEQ)
938 5af45186 bellard
SSE_HELPER_CMP(cmpnlt, FPU_CMPNLT)
939 5af45186 bellard
SSE_HELPER_CMP(cmpnle, FPU_CMPNLE)
940 5af45186 bellard
SSE_HELPER_CMP(cmpord, FPU_CMPORD)
941 664e0f19 bellard
942 1e6eec8b Blue Swirl
static const int comis_eflags[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
943 43fb823b bellard
944 5af45186 bellard
void helper_ucomiss(Reg *d, Reg *s)
945 664e0f19 bellard
{
946 43fb823b bellard
    int ret;
947 8422b113 bellard
    float32 s0, s1;
948 664e0f19 bellard
949 664e0f19 bellard
    s0 = d->XMM_S(0);
950 664e0f19 bellard
    s1 = s->XMM_S(0);
951 43fb823b bellard
    ret = float32_compare_quiet(s0, s1, &env->sse_status);
952 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
953 664e0f19 bellard
}
954 664e0f19 bellard
955 5af45186 bellard
void helper_comiss(Reg *d, Reg *s)
956 664e0f19 bellard
{
957 43fb823b bellard
    int ret;
958 8422b113 bellard
    float32 s0, s1;
959 664e0f19 bellard
960 664e0f19 bellard
    s0 = d->XMM_S(0);
961 664e0f19 bellard
    s1 = s->XMM_S(0);
962 43fb823b bellard
    ret = float32_compare(s0, s1, &env->sse_status);
963 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
964 664e0f19 bellard
}
965 664e0f19 bellard
966 5af45186 bellard
void helper_ucomisd(Reg *d, Reg *s)
967 664e0f19 bellard
{
968 43fb823b bellard
    int ret;
969 8422b113 bellard
    float64 d0, d1;
970 664e0f19 bellard
971 664e0f19 bellard
    d0 = d->XMM_D(0);
972 664e0f19 bellard
    d1 = s->XMM_D(0);
973 43fb823b bellard
    ret = float64_compare_quiet(d0, d1, &env->sse_status);
974 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
975 664e0f19 bellard
}
976 664e0f19 bellard
977 5af45186 bellard
void helper_comisd(Reg *d, Reg *s)
978 664e0f19 bellard
{
979 43fb823b bellard
    int ret;
980 8422b113 bellard
    float64 d0, d1;
981 664e0f19 bellard
982 664e0f19 bellard
    d0 = d->XMM_D(0);
983 664e0f19 bellard
    d1 = s->XMM_D(0);
984 43fb823b bellard
    ret = float64_compare(d0, d1, &env->sse_status);
985 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
986 664e0f19 bellard
}
987 664e0f19 bellard
988 5af45186 bellard
uint32_t helper_movmskps(Reg *s)
989 664e0f19 bellard
{
990 664e0f19 bellard
    int b0, b1, b2, b3;
991 664e0f19 bellard
    b0 = s->XMM_L(0) >> 31;
992 664e0f19 bellard
    b1 = s->XMM_L(1) >> 31;
993 664e0f19 bellard
    b2 = s->XMM_L(2) >> 31;
994 664e0f19 bellard
    b3 = s->XMM_L(3) >> 31;
995 5af45186 bellard
    return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3);
996 664e0f19 bellard
}
997 664e0f19 bellard
998 5af45186 bellard
uint32_t helper_movmskpd(Reg *s)
999 664e0f19 bellard
{
1000 664e0f19 bellard
    int b0, b1;
1001 664e0f19 bellard
    b0 = s->XMM_L(1) >> 31;
1002 664e0f19 bellard
    b1 = s->XMM_L(3) >> 31;
1003 5af45186 bellard
    return b0 | (b1 << 1);
1004 664e0f19 bellard
}
1005 664e0f19 bellard
1006 664e0f19 bellard
#endif
1007 664e0f19 bellard
1008 5af45186 bellard
uint32_t glue(helper_pmovmskb, SUFFIX)(Reg *s)
1009 5af45186 bellard
{
1010 5af45186 bellard
    uint32_t val;
1011 5af45186 bellard
    val = 0;
1012 30913bae aurel32
    val |= (s->B(0) >> 7);
1013 30913bae aurel32
    val |= (s->B(1) >> 6) & 0x02;
1014 30913bae aurel32
    val |= (s->B(2) >> 5) & 0x04;
1015 30913bae aurel32
    val |= (s->B(3) >> 4) & 0x08;
1016 30913bae aurel32
    val |= (s->B(4) >> 3) & 0x10;
1017 30913bae aurel32
    val |= (s->B(5) >> 2) & 0x20;
1018 30913bae aurel32
    val |= (s->B(6) >> 1) & 0x40;
1019 30913bae aurel32
    val |= (s->B(7)) & 0x80;
1020 664e0f19 bellard
#if SHIFT == 1
1021 30913bae aurel32
    val |= (s->B(8) << 1) & 0x0100;
1022 30913bae aurel32
    val |= (s->B(9) << 2) & 0x0200;
1023 30913bae aurel32
    val |= (s->B(10) << 3) & 0x0400;
1024 30913bae aurel32
    val |= (s->B(11) << 4) & 0x0800;
1025 30913bae aurel32
    val |= (s->B(12) << 5) & 0x1000;
1026 30913bae aurel32
    val |= (s->B(13) << 6) & 0x2000;
1027 30913bae aurel32
    val |= (s->B(14) << 7) & 0x4000;
1028 30913bae aurel32
    val |= (s->B(15) << 8) & 0x8000;
1029 664e0f19 bellard
#endif
1030 5af45186 bellard
    return val;
1031 664e0f19 bellard
}
1032 664e0f19 bellard
1033 5af45186 bellard
void glue(helper_packsswb, SUFFIX) (Reg *d, Reg *s)
1034 664e0f19 bellard
{
1035 5af45186 bellard
    Reg r;
1036 664e0f19 bellard
1037 664e0f19 bellard
    r.B(0) = satsb((int16_t)d->W(0));
1038 664e0f19 bellard
    r.B(1) = satsb((int16_t)d->W(1));
1039 664e0f19 bellard
    r.B(2) = satsb((int16_t)d->W(2));
1040 664e0f19 bellard
    r.B(3) = satsb((int16_t)d->W(3));
1041 664e0f19 bellard
#if SHIFT == 1
1042 664e0f19 bellard
    r.B(4) = satsb((int16_t)d->W(4));
1043 664e0f19 bellard
    r.B(5) = satsb((int16_t)d->W(5));
1044 664e0f19 bellard
    r.B(6) = satsb((int16_t)d->W(6));
1045 664e0f19 bellard
    r.B(7) = satsb((int16_t)d->W(7));
1046 664e0f19 bellard
#endif
1047 664e0f19 bellard
    r.B((4 << SHIFT) + 0) = satsb((int16_t)s->W(0));
1048 664e0f19 bellard
    r.B((4 << SHIFT) + 1) = satsb((int16_t)s->W(1));
1049 664e0f19 bellard
    r.B((4 << SHIFT) + 2) = satsb((int16_t)s->W(2));
1050 664e0f19 bellard
    r.B((4 << SHIFT) + 3) = satsb((int16_t)s->W(3));
1051 664e0f19 bellard
#if SHIFT == 1
1052 664e0f19 bellard
    r.B(12) = satsb((int16_t)s->W(4));
1053 664e0f19 bellard
    r.B(13) = satsb((int16_t)s->W(5));
1054 664e0f19 bellard
    r.B(14) = satsb((int16_t)s->W(6));
1055 664e0f19 bellard
    r.B(15) = satsb((int16_t)s->W(7));
1056 664e0f19 bellard
#endif
1057 664e0f19 bellard
    *d = r;
1058 664e0f19 bellard
}
1059 664e0f19 bellard
1060 5af45186 bellard
void glue(helper_packuswb, SUFFIX) (Reg *d, Reg *s)
1061 664e0f19 bellard
{
1062 5af45186 bellard
    Reg r;
1063 664e0f19 bellard
1064 664e0f19 bellard
    r.B(0) = satub((int16_t)d->W(0));
1065 664e0f19 bellard
    r.B(1) = satub((int16_t)d->W(1));
1066 664e0f19 bellard
    r.B(2) = satub((int16_t)d->W(2));
1067 664e0f19 bellard
    r.B(3) = satub((int16_t)d->W(3));
1068 664e0f19 bellard
#if SHIFT == 1
1069 664e0f19 bellard
    r.B(4) = satub((int16_t)d->W(4));
1070 664e0f19 bellard
    r.B(5) = satub((int16_t)d->W(5));
1071 664e0f19 bellard
    r.B(6) = satub((int16_t)d->W(6));
1072 664e0f19 bellard
    r.B(7) = satub((int16_t)d->W(7));
1073 664e0f19 bellard
#endif
1074 664e0f19 bellard
    r.B((4 << SHIFT) + 0) = satub((int16_t)s->W(0));
1075 664e0f19 bellard
    r.B((4 << SHIFT) + 1) = satub((int16_t)s->W(1));
1076 664e0f19 bellard
    r.B((4 << SHIFT) + 2) = satub((int16_t)s->W(2));
1077 664e0f19 bellard
    r.B((4 << SHIFT) + 3) = satub((int16_t)s->W(3));
1078 664e0f19 bellard
#if SHIFT == 1
1079 664e0f19 bellard
    r.B(12) = satub((int16_t)s->W(4));
1080 664e0f19 bellard
    r.B(13) = satub((int16_t)s->W(5));
1081 664e0f19 bellard
    r.B(14) = satub((int16_t)s->W(6));
1082 664e0f19 bellard
    r.B(15) = satub((int16_t)s->W(7));
1083 664e0f19 bellard
#endif
1084 664e0f19 bellard
    *d = r;
1085 664e0f19 bellard
}
1086 664e0f19 bellard
1087 5af45186 bellard
void glue(helper_packssdw, SUFFIX) (Reg *d, Reg *s)
1088 664e0f19 bellard
{
1089 5af45186 bellard
    Reg r;
1090 664e0f19 bellard
1091 664e0f19 bellard
    r.W(0) = satsw(d->L(0));
1092 664e0f19 bellard
    r.W(1) = satsw(d->L(1));
1093 664e0f19 bellard
#if SHIFT == 1
1094 664e0f19 bellard
    r.W(2) = satsw(d->L(2));
1095 664e0f19 bellard
    r.W(3) = satsw(d->L(3));
1096 664e0f19 bellard
#endif
1097 664e0f19 bellard
    r.W((2 << SHIFT) + 0) = satsw(s->L(0));
1098 664e0f19 bellard
    r.W((2 << SHIFT) + 1) = satsw(s->L(1));
1099 664e0f19 bellard
#if SHIFT == 1
1100 664e0f19 bellard
    r.W(6) = satsw(s->L(2));
1101 664e0f19 bellard
    r.W(7) = satsw(s->L(3));
1102 664e0f19 bellard
#endif
1103 664e0f19 bellard
    *d = r;
1104 664e0f19 bellard
}
1105 664e0f19 bellard
1106 664e0f19 bellard
#define UNPCK_OP(base_name, base)                               \
1107 664e0f19 bellard
                                                                \
1108 5af45186 bellard
void glue(helper_punpck ## base_name ## bw, SUFFIX) (Reg *d, Reg *s)   \
1109 664e0f19 bellard
{                                                               \
1110 5af45186 bellard
    Reg r;                                              \
1111 664e0f19 bellard
                                                                \
1112 664e0f19 bellard
    r.B(0) = d->B((base << (SHIFT + 2)) + 0);                   \
1113 664e0f19 bellard
    r.B(1) = s->B((base << (SHIFT + 2)) + 0);                   \
1114 664e0f19 bellard
    r.B(2) = d->B((base << (SHIFT + 2)) + 1);                   \
1115 664e0f19 bellard
    r.B(3) = s->B((base << (SHIFT + 2)) + 1);                   \
1116 664e0f19 bellard
    r.B(4) = d->B((base << (SHIFT + 2)) + 2);                   \
1117 664e0f19 bellard
    r.B(5) = s->B((base << (SHIFT + 2)) + 2);                   \
1118 664e0f19 bellard
    r.B(6) = d->B((base << (SHIFT + 2)) + 3);                   \
1119 664e0f19 bellard
    r.B(7) = s->B((base << (SHIFT + 2)) + 3);                   \
1120 664e0f19 bellard
XMM_ONLY(                                                       \
1121 664e0f19 bellard
    r.B(8) = d->B((base << (SHIFT + 2)) + 4);                   \
1122 664e0f19 bellard
    r.B(9) = s->B((base << (SHIFT + 2)) + 4);                   \
1123 664e0f19 bellard
    r.B(10) = d->B((base << (SHIFT + 2)) + 5);                  \
1124 664e0f19 bellard
    r.B(11) = s->B((base << (SHIFT + 2)) + 5);                  \
1125 664e0f19 bellard
    r.B(12) = d->B((base << (SHIFT + 2)) + 6);                  \
1126 664e0f19 bellard
    r.B(13) = s->B((base << (SHIFT + 2)) + 6);                  \
1127 664e0f19 bellard
    r.B(14) = d->B((base << (SHIFT + 2)) + 7);                  \
1128 664e0f19 bellard
    r.B(15) = s->B((base << (SHIFT + 2)) + 7);                  \
1129 664e0f19 bellard
)                                                               \
1130 664e0f19 bellard
    *d = r;                                                     \
1131 664e0f19 bellard
}                                                               \
1132 664e0f19 bellard
                                                                \
1133 5af45186 bellard
void glue(helper_punpck ## base_name ## wd, SUFFIX) (Reg *d, Reg *s)   \
1134 664e0f19 bellard
{                                                               \
1135 5af45186 bellard
    Reg r;                                              \
1136 664e0f19 bellard
                                                                \
1137 664e0f19 bellard
    r.W(0) = d->W((base << (SHIFT + 1)) + 0);                   \
1138 664e0f19 bellard
    r.W(1) = s->W((base << (SHIFT + 1)) + 0);                   \
1139 664e0f19 bellard
    r.W(2) = d->W((base << (SHIFT + 1)) + 1);                   \
1140 664e0f19 bellard
    r.W(3) = s->W((base << (SHIFT + 1)) + 1);                   \
1141 664e0f19 bellard
XMM_ONLY(                                                       \
1142 664e0f19 bellard
    r.W(4) = d->W((base << (SHIFT + 1)) + 2);                   \
1143 664e0f19 bellard
    r.W(5) = s->W((base << (SHIFT + 1)) + 2);                   \
1144 664e0f19 bellard
    r.W(6) = d->W((base << (SHIFT + 1)) + 3);                   \
1145 664e0f19 bellard
    r.W(7) = s->W((base << (SHIFT + 1)) + 3);                   \
1146 664e0f19 bellard
)                                                               \
1147 664e0f19 bellard
    *d = r;                                                     \
1148 664e0f19 bellard
}                                                               \
1149 664e0f19 bellard
                                                                \
1150 5af45186 bellard
void glue(helper_punpck ## base_name ## dq, SUFFIX) (Reg *d, Reg *s)   \
1151 664e0f19 bellard
{                                                               \
1152 5af45186 bellard
    Reg r;                                              \
1153 664e0f19 bellard
                                                                \
1154 664e0f19 bellard
    r.L(0) = d->L((base << SHIFT) + 0);                         \
1155 664e0f19 bellard
    r.L(1) = s->L((base << SHIFT) + 0);                         \
1156 664e0f19 bellard
XMM_ONLY(                                                       \
1157 664e0f19 bellard
    r.L(2) = d->L((base << SHIFT) + 1);                         \
1158 664e0f19 bellard
    r.L(3) = s->L((base << SHIFT) + 1);                         \
1159 664e0f19 bellard
)                                                               \
1160 664e0f19 bellard
    *d = r;                                                     \
1161 664e0f19 bellard
}                                                               \
1162 664e0f19 bellard
                                                                \
1163 664e0f19 bellard
XMM_ONLY(                                                       \
1164 5af45186 bellard
void glue(helper_punpck ## base_name ## qdq, SUFFIX) (Reg *d, Reg *s)  \
1165 664e0f19 bellard
{                                                               \
1166 5af45186 bellard
    Reg r;                                              \
1167 664e0f19 bellard
                                                                \
1168 664e0f19 bellard
    r.Q(0) = d->Q(base);                                        \
1169 664e0f19 bellard
    r.Q(1) = s->Q(base);                                        \
1170 664e0f19 bellard
    *d = r;                                                     \
1171 664e0f19 bellard
}                                                               \
1172 664e0f19 bellard
)
1173 664e0f19 bellard
1174 664e0f19 bellard
UNPCK_OP(l, 0)
1175 664e0f19 bellard
UNPCK_OP(h, 1)
1176 664e0f19 bellard
1177 a35f3ec7 aurel32
/* 3DNow! float ops */
1178 a35f3ec7 aurel32
#if SHIFT == 0
1179 5af45186 bellard
void helper_pi2fd(MMXReg *d, MMXReg *s)
1180 a35f3ec7 aurel32
{
1181 a35f3ec7 aurel32
    d->MMX_S(0) = int32_to_float32(s->MMX_L(0), &env->mmx_status);
1182 a35f3ec7 aurel32
    d->MMX_S(1) = int32_to_float32(s->MMX_L(1), &env->mmx_status);
1183 a35f3ec7 aurel32
}
1184 a35f3ec7 aurel32
1185 5af45186 bellard
void helper_pi2fw(MMXReg *d, MMXReg *s)
1186 a35f3ec7 aurel32
{
1187 a35f3ec7 aurel32
    d->MMX_S(0) = int32_to_float32((int16_t)s->MMX_W(0), &env->mmx_status);
1188 a35f3ec7 aurel32
    d->MMX_S(1) = int32_to_float32((int16_t)s->MMX_W(2), &env->mmx_status);
1189 a35f3ec7 aurel32
}
1190 a35f3ec7 aurel32
1191 5af45186 bellard
void helper_pf2id(MMXReg *d, MMXReg *s)
1192 a35f3ec7 aurel32
{
1193 a35f3ec7 aurel32
    d->MMX_L(0) = float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status);
1194 a35f3ec7 aurel32
    d->MMX_L(1) = float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status);
1195 a35f3ec7 aurel32
}
1196 a35f3ec7 aurel32
1197 5af45186 bellard
void helper_pf2iw(MMXReg *d, MMXReg *s)
1198 a35f3ec7 aurel32
{
1199 a35f3ec7 aurel32
    d->MMX_L(0) = satsw(float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status));
1200 a35f3ec7 aurel32
    d->MMX_L(1) = satsw(float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status));
1201 a35f3ec7 aurel32
}
1202 a35f3ec7 aurel32
1203 5af45186 bellard
void helper_pfacc(MMXReg *d, MMXReg *s)
1204 a35f3ec7 aurel32
{
1205 a35f3ec7 aurel32
    MMXReg r;
1206 a35f3ec7 aurel32
    r.MMX_S(0) = float32_add(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1207 a35f3ec7 aurel32
    r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1208 a35f3ec7 aurel32
    *d = r;
1209 a35f3ec7 aurel32
}
1210 a35f3ec7 aurel32
1211 5af45186 bellard
void helper_pfadd(MMXReg *d, MMXReg *s)
1212 a35f3ec7 aurel32
{
1213 a35f3ec7 aurel32
    d->MMX_S(0) = float32_add(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1214 a35f3ec7 aurel32
    d->MMX_S(1) = float32_add(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1215 a35f3ec7 aurel32
}
1216 a35f3ec7 aurel32
1217 5af45186 bellard
void helper_pfcmpeq(MMXReg *d, MMXReg *s)
1218 a35f3ec7 aurel32
{
1219 a35f3ec7 aurel32
    d->MMX_L(0) = float32_eq(d->MMX_S(0), s->MMX_S(0), &env->mmx_status) ? -1 : 0;
1220 a35f3ec7 aurel32
    d->MMX_L(1) = float32_eq(d->MMX_S(1), s->MMX_S(1), &env->mmx_status) ? -1 : 0;
1221 a35f3ec7 aurel32
}
1222 a35f3ec7 aurel32
1223 5af45186 bellard
void helper_pfcmpge(MMXReg *d, MMXReg *s)
1224 a35f3ec7 aurel32
{
1225 a35f3ec7 aurel32
    d->MMX_L(0) = float32_le(s->MMX_S(0), d->MMX_S(0), &env->mmx_status) ? -1 : 0;
1226 a35f3ec7 aurel32
    d->MMX_L(1) = float32_le(s->MMX_S(1), d->MMX_S(1), &env->mmx_status) ? -1 : 0;
1227 a35f3ec7 aurel32
}
1228 a35f3ec7 aurel32
1229 5af45186 bellard
void helper_pfcmpgt(MMXReg *d, MMXReg *s)
1230 a35f3ec7 aurel32
{
1231 a35f3ec7 aurel32
    d->MMX_L(0) = float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status) ? -1 : 0;
1232 a35f3ec7 aurel32
    d->MMX_L(1) = float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status) ? -1 : 0;
1233 a35f3ec7 aurel32
}
1234 a35f3ec7 aurel32
1235 5af45186 bellard
void helper_pfmax(MMXReg *d, MMXReg *s)
1236 a35f3ec7 aurel32
{
1237 a35f3ec7 aurel32
    if (float32_lt(d->MMX_S(0), s->MMX_S(0), &env->mmx_status))
1238 a35f3ec7 aurel32
        d->MMX_S(0) = s->MMX_S(0);
1239 a35f3ec7 aurel32
    if (float32_lt(d->MMX_S(1), s->MMX_S(1), &env->mmx_status))
1240 a35f3ec7 aurel32
        d->MMX_S(1) = s->MMX_S(1);
1241 a35f3ec7 aurel32
}
1242 a35f3ec7 aurel32
1243 5af45186 bellard
void helper_pfmin(MMXReg *d, MMXReg *s)
1244 a35f3ec7 aurel32
{
1245 a35f3ec7 aurel32
    if (float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status))
1246 a35f3ec7 aurel32
        d->MMX_S(0) = s->MMX_S(0);
1247 a35f3ec7 aurel32
    if (float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status))
1248 a35f3ec7 aurel32
        d->MMX_S(1) = s->MMX_S(1);
1249 a35f3ec7 aurel32
}
1250 a35f3ec7 aurel32
1251 5af45186 bellard
void helper_pfmul(MMXReg *d, MMXReg *s)
1252 a35f3ec7 aurel32
{
1253 a35f3ec7 aurel32
    d->MMX_S(0) = float32_mul(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1254 a35f3ec7 aurel32
    d->MMX_S(1) = float32_mul(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1255 a35f3ec7 aurel32
}
1256 a35f3ec7 aurel32
1257 5af45186 bellard
void helper_pfnacc(MMXReg *d, MMXReg *s)
1258 a35f3ec7 aurel32
{
1259 a35f3ec7 aurel32
    MMXReg r;
1260 a35f3ec7 aurel32
    r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1261 a35f3ec7 aurel32
    r.MMX_S(1) = float32_sub(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1262 a35f3ec7 aurel32
    *d = r;
1263 a35f3ec7 aurel32
}
1264 a35f3ec7 aurel32
1265 5af45186 bellard
void helper_pfpnacc(MMXReg *d, MMXReg *s)
1266 a35f3ec7 aurel32
{
1267 a35f3ec7 aurel32
    MMXReg r;
1268 a35f3ec7 aurel32
    r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1269 a35f3ec7 aurel32
    r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1270 a35f3ec7 aurel32
    *d = r;
1271 a35f3ec7 aurel32
}
1272 a35f3ec7 aurel32
1273 5af45186 bellard
void helper_pfrcp(MMXReg *d, MMXReg *s)
1274 a35f3ec7 aurel32
{
1275 a35f3ec7 aurel32
    d->MMX_S(0) = approx_rcp(s->MMX_S(0));
1276 a35f3ec7 aurel32
    d->MMX_S(1) = d->MMX_S(0);
1277 a35f3ec7 aurel32
}
1278 a35f3ec7 aurel32
1279 5af45186 bellard
void helper_pfrsqrt(MMXReg *d, MMXReg *s)
1280 a35f3ec7 aurel32
{
1281 a35f3ec7 aurel32
    d->MMX_L(1) = s->MMX_L(0) & 0x7fffffff;
1282 a35f3ec7 aurel32
    d->MMX_S(1) = approx_rsqrt(d->MMX_S(1));
1283 a35f3ec7 aurel32
    d->MMX_L(1) |= s->MMX_L(0) & 0x80000000;
1284 a35f3ec7 aurel32
    d->MMX_L(0) = d->MMX_L(1);
1285 a35f3ec7 aurel32
}
1286 a35f3ec7 aurel32
1287 5af45186 bellard
void helper_pfsub(MMXReg *d, MMXReg *s)
1288 a35f3ec7 aurel32
{
1289 a35f3ec7 aurel32
    d->MMX_S(0) = float32_sub(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1290 a35f3ec7 aurel32
    d->MMX_S(1) = float32_sub(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1291 a35f3ec7 aurel32
}
1292 a35f3ec7 aurel32
1293 5af45186 bellard
void helper_pfsubr(MMXReg *d, MMXReg *s)
1294 a35f3ec7 aurel32
{
1295 a35f3ec7 aurel32
    d->MMX_S(0) = float32_sub(s->MMX_S(0), d->MMX_S(0), &env->mmx_status);
1296 a35f3ec7 aurel32
    d->MMX_S(1) = float32_sub(s->MMX_S(1), d->MMX_S(1), &env->mmx_status);
1297 a35f3ec7 aurel32
}
1298 a35f3ec7 aurel32
1299 5af45186 bellard
void helper_pswapd(MMXReg *d, MMXReg *s)
1300 a35f3ec7 aurel32
{
1301 a35f3ec7 aurel32
    MMXReg r;
1302 a35f3ec7 aurel32
    r.MMX_L(0) = s->MMX_L(1);
1303 a35f3ec7 aurel32
    r.MMX_L(1) = s->MMX_L(0);
1304 a35f3ec7 aurel32
    *d = r;
1305 a35f3ec7 aurel32
}
1306 a35f3ec7 aurel32
#endif
1307 a35f3ec7 aurel32
1308 4242b1bd balrog
/* SSSE3 op helpers */
1309 4242b1bd balrog
void glue(helper_pshufb, SUFFIX) (Reg *d, Reg *s)
1310 4242b1bd balrog
{
1311 4242b1bd balrog
    int i;
1312 4242b1bd balrog
    Reg r;
1313 4242b1bd balrog
1314 4242b1bd balrog
    for (i = 0; i < (8 << SHIFT); i++)
1315 4242b1bd balrog
        r.B(i) = (s->B(i) & 0x80) ? 0 : (d->B(s->B(i) & ((8 << SHIFT) - 1)));
1316 4242b1bd balrog
1317 4242b1bd balrog
    *d = r;
1318 4242b1bd balrog
}
1319 4242b1bd balrog
1320 4242b1bd balrog
void glue(helper_phaddw, SUFFIX) (Reg *d, Reg *s)
1321 4242b1bd balrog
{
1322 4242b1bd balrog
    d->W(0) = (int16_t)d->W(0) + (int16_t)d->W(1);
1323 4242b1bd balrog
    d->W(1) = (int16_t)d->W(2) + (int16_t)d->W(3);
1324 4242b1bd balrog
    XMM_ONLY(d->W(2) = (int16_t)d->W(4) + (int16_t)d->W(5));
1325 4242b1bd balrog
    XMM_ONLY(d->W(3) = (int16_t)d->W(6) + (int16_t)d->W(7));
1326 4242b1bd balrog
    d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) + (int16_t)s->W(1);
1327 4242b1bd balrog
    d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) + (int16_t)s->W(3);
1328 4242b1bd balrog
    XMM_ONLY(d->W(6) = (int16_t)s->W(4) + (int16_t)s->W(5));
1329 4242b1bd balrog
    XMM_ONLY(d->W(7) = (int16_t)s->W(6) + (int16_t)s->W(7));
1330 4242b1bd balrog
}
1331 4242b1bd balrog
1332 4242b1bd balrog
void glue(helper_phaddd, SUFFIX) (Reg *d, Reg *s)
1333 4242b1bd balrog
{
1334 4242b1bd balrog
    d->L(0) = (int32_t)d->L(0) + (int32_t)d->L(1);
1335 4242b1bd balrog
    XMM_ONLY(d->L(1) = (int32_t)d->L(2) + (int32_t)d->L(3));
1336 4242b1bd balrog
    d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) + (int32_t)s->L(1);
1337 4242b1bd balrog
    XMM_ONLY(d->L(3) = (int32_t)s->L(2) + (int32_t)s->L(3));
1338 4242b1bd balrog
}
1339 4242b1bd balrog
1340 4242b1bd balrog
void glue(helper_phaddsw, SUFFIX) (Reg *d, Reg *s)
1341 4242b1bd balrog
{
1342 4242b1bd balrog
    d->W(0) = satsw((int16_t)d->W(0) + (int16_t)d->W(1));
1343 4242b1bd balrog
    d->W(1) = satsw((int16_t)d->W(2) + (int16_t)d->W(3));
1344 4242b1bd balrog
    XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) + (int16_t)d->W(5)));
1345 4242b1bd balrog
    XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) + (int16_t)d->W(7)));
1346 4242b1bd balrog
    d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) + (int16_t)s->W(1));
1347 4242b1bd balrog
    d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) + (int16_t)s->W(3));
1348 4242b1bd balrog
    XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) + (int16_t)s->W(5)));
1349 4242b1bd balrog
    XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) + (int16_t)s->W(7)));
1350 4242b1bd balrog
}
1351 4242b1bd balrog
1352 4242b1bd balrog
void glue(helper_pmaddubsw, SUFFIX) (Reg *d, Reg *s)
1353 4242b1bd balrog
{
1354 4242b1bd balrog
    d->W(0) = satsw((int8_t)s->B( 0) * (uint8_t)d->B( 0) +
1355 4242b1bd balrog
                    (int8_t)s->B( 1) * (uint8_t)d->B( 1));
1356 4242b1bd balrog
    d->W(1) = satsw((int8_t)s->B( 2) * (uint8_t)d->B( 2) +
1357 4242b1bd balrog
                    (int8_t)s->B( 3) * (uint8_t)d->B( 3));
1358 4242b1bd balrog
    d->W(2) = satsw((int8_t)s->B( 4) * (uint8_t)d->B( 4) +
1359 4242b1bd balrog
                    (int8_t)s->B( 5) * (uint8_t)d->B( 5));
1360 4242b1bd balrog
    d->W(3) = satsw((int8_t)s->B( 6) * (uint8_t)d->B( 6) +
1361 4242b1bd balrog
                    (int8_t)s->B( 7) * (uint8_t)d->B( 7));
1362 4242b1bd balrog
#if SHIFT == 1
1363 4242b1bd balrog
    d->W(4) = satsw((int8_t)s->B( 8) * (uint8_t)d->B( 8) +
1364 4242b1bd balrog
                    (int8_t)s->B( 9) * (uint8_t)d->B( 9));
1365 4242b1bd balrog
    d->W(5) = satsw((int8_t)s->B(10) * (uint8_t)d->B(10) +
1366 4242b1bd balrog
                    (int8_t)s->B(11) * (uint8_t)d->B(11));
1367 4242b1bd balrog
    d->W(6) = satsw((int8_t)s->B(12) * (uint8_t)d->B(12) +
1368 4242b1bd balrog
                    (int8_t)s->B(13) * (uint8_t)d->B(13));
1369 4242b1bd balrog
    d->W(7) = satsw((int8_t)s->B(14) * (uint8_t)d->B(14) +
1370 4242b1bd balrog
                    (int8_t)s->B(15) * (uint8_t)d->B(15));
1371 4242b1bd balrog
#endif
1372 4242b1bd balrog
}
1373 4242b1bd balrog
1374 4242b1bd balrog
void glue(helper_phsubw, SUFFIX) (Reg *d, Reg *s)
1375 4242b1bd balrog
{
1376 4242b1bd balrog
    d->W(0) = (int16_t)d->W(0) - (int16_t)d->W(1);
1377 4242b1bd balrog
    d->W(1) = (int16_t)d->W(2) - (int16_t)d->W(3);
1378 4242b1bd balrog
    XMM_ONLY(d->W(2) = (int16_t)d->W(4) - (int16_t)d->W(5));
1379 4242b1bd balrog
    XMM_ONLY(d->W(3) = (int16_t)d->W(6) - (int16_t)d->W(7));
1380 4242b1bd balrog
    d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) - (int16_t)s->W(1);
1381 4242b1bd balrog
    d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) - (int16_t)s->W(3);
1382 4242b1bd balrog
    XMM_ONLY(d->W(6) = (int16_t)s->W(4) - (int16_t)s->W(5));
1383 4242b1bd balrog
    XMM_ONLY(d->W(7) = (int16_t)s->W(6) - (int16_t)s->W(7));
1384 4242b1bd balrog
}
1385 4242b1bd balrog
1386 4242b1bd balrog
void glue(helper_phsubd, SUFFIX) (Reg *d, Reg *s)
1387 4242b1bd balrog
{
1388 4242b1bd balrog
    d->L(0) = (int32_t)d->L(0) - (int32_t)d->L(1);
1389 4242b1bd balrog
    XMM_ONLY(d->L(1) = (int32_t)d->L(2) - (int32_t)d->L(3));
1390 4242b1bd balrog
    d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) - (int32_t)s->L(1);
1391 4242b1bd balrog
    XMM_ONLY(d->L(3) = (int32_t)s->L(2) - (int32_t)s->L(3));
1392 4242b1bd balrog
}
1393 4242b1bd balrog
1394 4242b1bd balrog
void glue(helper_phsubsw, SUFFIX) (Reg *d, Reg *s)
1395 4242b1bd balrog
{
1396 4242b1bd balrog
    d->W(0) = satsw((int16_t)d->W(0) - (int16_t)d->W(1));
1397 4242b1bd balrog
    d->W(1) = satsw((int16_t)d->W(2) - (int16_t)d->W(3));
1398 4242b1bd balrog
    XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) - (int16_t)d->W(5)));
1399 4242b1bd balrog
    XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) - (int16_t)d->W(7)));
1400 4242b1bd balrog
    d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) - (int16_t)s->W(1));
1401 4242b1bd balrog
    d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) - (int16_t)s->W(3));
1402 4242b1bd balrog
    XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) - (int16_t)s->W(5)));
1403 4242b1bd balrog
    XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) - (int16_t)s->W(7)));
1404 4242b1bd balrog
}
1405 4242b1bd balrog
1406 4242b1bd balrog
#define FABSB(_, x) x > INT8_MAX  ? -(int8_t ) x : x
1407 4242b1bd balrog
#define FABSW(_, x) x > INT16_MAX ? -(int16_t) x : x
1408 4242b1bd balrog
#define FABSL(_, x) x > INT32_MAX ? -(int32_t) x : x
1409 4242b1bd balrog
SSE_HELPER_B(helper_pabsb, FABSB)
1410 4242b1bd balrog
SSE_HELPER_W(helper_pabsw, FABSW)
1411 4242b1bd balrog
SSE_HELPER_L(helper_pabsd, FABSL)
1412 4242b1bd balrog
1413 4242b1bd balrog
#define FMULHRSW(d, s) ((int16_t) d * (int16_t) s + 0x4000) >> 15
1414 4242b1bd balrog
SSE_HELPER_W(helper_pmulhrsw, FMULHRSW)
1415 4242b1bd balrog
1416 4242b1bd balrog
#define FSIGNB(d, s) s <= INT8_MAX  ? s ? d : 0 : -(int8_t ) d
1417 4242b1bd balrog
#define FSIGNW(d, s) s <= INT16_MAX ? s ? d : 0 : -(int16_t) d
1418 4242b1bd balrog
#define FSIGNL(d, s) s <= INT32_MAX ? s ? d : 0 : -(int32_t) d
1419 4242b1bd balrog
SSE_HELPER_B(helper_psignb, FSIGNB)
1420 4242b1bd balrog
SSE_HELPER_W(helper_psignw, FSIGNW)
1421 4242b1bd balrog
SSE_HELPER_L(helper_psignd, FSIGNL)
1422 4242b1bd balrog
1423 4242b1bd balrog
void glue(helper_palignr, SUFFIX) (Reg *d, Reg *s, int32_t shift)
1424 4242b1bd balrog
{
1425 4242b1bd balrog
    Reg r;
1426 4242b1bd balrog
1427 4242b1bd balrog
    /* XXX could be checked during translation */
1428 4242b1bd balrog
    if (shift >= (16 << SHIFT)) {
1429 4242b1bd balrog
        r.Q(0) = 0;
1430 4242b1bd balrog
        XMM_ONLY(r.Q(1) = 0);
1431 4242b1bd balrog
    } else {
1432 4242b1bd balrog
        shift <<= 3;
1433 4242b1bd balrog
#define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0)
1434 4242b1bd balrog
#if SHIFT == 0
1435 4242b1bd balrog
        r.Q(0) = SHR(s->Q(0), shift -   0) |
1436 4242b1bd balrog
                 SHR(d->Q(0), shift -  64);
1437 4242b1bd balrog
#else
1438 4242b1bd balrog
        r.Q(0) = SHR(s->Q(0), shift -   0) |
1439 4242b1bd balrog
                 SHR(s->Q(1), shift -  64) |
1440 4242b1bd balrog
                 SHR(d->Q(0), shift - 128) |
1441 4242b1bd balrog
                 SHR(d->Q(1), shift - 192);
1442 4242b1bd balrog
        r.Q(1) = SHR(s->Q(0), shift +  64) |
1443 4242b1bd balrog
                 SHR(s->Q(1), shift -   0) |
1444 4242b1bd balrog
                 SHR(d->Q(0), shift -  64) |
1445 4242b1bd balrog
                 SHR(d->Q(1), shift - 128);
1446 4242b1bd balrog
#endif
1447 4242b1bd balrog
#undef SHR
1448 4242b1bd balrog
    }
1449 4242b1bd balrog
1450 4242b1bd balrog
    *d = r;
1451 4242b1bd balrog
}
1452 4242b1bd balrog
1453 222a3336 balrog
#define XMM0 env->xmm_regs[0]
1454 222a3336 balrog
1455 222a3336 balrog
#if SHIFT == 1
1456 222a3336 balrog
#define SSE_HELPER_V(name, elem, num, F)\
1457 222a3336 balrog
void glue(name, SUFFIX) (Reg *d, Reg *s)\
1458 222a3336 balrog
{\
1459 222a3336 balrog
    d->elem(0) = F(d->elem(0), s->elem(0), XMM0.elem(0));\
1460 222a3336 balrog
    d->elem(1) = F(d->elem(1), s->elem(1), XMM0.elem(1));\
1461 222a3336 balrog
    if (num > 2) {\
1462 222a3336 balrog
        d->elem(2) = F(d->elem(2), s->elem(2), XMM0.elem(2));\
1463 222a3336 balrog
        d->elem(3) = F(d->elem(3), s->elem(3), XMM0.elem(3));\
1464 222a3336 balrog
        if (num > 4) {\
1465 222a3336 balrog
            d->elem(4) = F(d->elem(4), s->elem(4), XMM0.elem(4));\
1466 222a3336 balrog
            d->elem(5) = F(d->elem(5), s->elem(5), XMM0.elem(5));\
1467 222a3336 balrog
            d->elem(6) = F(d->elem(6), s->elem(6), XMM0.elem(6));\
1468 222a3336 balrog
            d->elem(7) = F(d->elem(7), s->elem(7), XMM0.elem(7));\
1469 222a3336 balrog
            if (num > 8) {\
1470 222a3336 balrog
                d->elem(8) = F(d->elem(8), s->elem(8), XMM0.elem(8));\
1471 222a3336 balrog
                d->elem(9) = F(d->elem(9), s->elem(9), XMM0.elem(9));\
1472 222a3336 balrog
                d->elem(10) = F(d->elem(10), s->elem(10), XMM0.elem(10));\
1473 222a3336 balrog
                d->elem(11) = F(d->elem(11), s->elem(11), XMM0.elem(11));\
1474 222a3336 balrog
                d->elem(12) = F(d->elem(12), s->elem(12), XMM0.elem(12));\
1475 222a3336 balrog
                d->elem(13) = F(d->elem(13), s->elem(13), XMM0.elem(13));\
1476 222a3336 balrog
                d->elem(14) = F(d->elem(14), s->elem(14), XMM0.elem(14));\
1477 222a3336 balrog
                d->elem(15) = F(d->elem(15), s->elem(15), XMM0.elem(15));\
1478 222a3336 balrog
            }\
1479 222a3336 balrog
        }\
1480 222a3336 balrog
    }\
1481 222a3336 balrog
}
1482 222a3336 balrog
1483 222a3336 balrog
#define SSE_HELPER_I(name, elem, num, F)\
1484 222a3336 balrog
void glue(name, SUFFIX) (Reg *d, Reg *s, uint32_t imm)\
1485 222a3336 balrog
{\
1486 222a3336 balrog
    d->elem(0) = F(d->elem(0), s->elem(0), ((imm >> 0) & 1));\
1487 222a3336 balrog
    d->elem(1) = F(d->elem(1), s->elem(1), ((imm >> 1) & 1));\
1488 222a3336 balrog
    if (num > 2) {\
1489 222a3336 balrog
        d->elem(2) = F(d->elem(2), s->elem(2), ((imm >> 2) & 1));\
1490 222a3336 balrog
        d->elem(3) = F(d->elem(3), s->elem(3), ((imm >> 3) & 1));\
1491 222a3336 balrog
        if (num > 4) {\
1492 222a3336 balrog
            d->elem(4) = F(d->elem(4), s->elem(4), ((imm >> 4) & 1));\
1493 222a3336 balrog
            d->elem(5) = F(d->elem(5), s->elem(5), ((imm >> 5) & 1));\
1494 222a3336 balrog
            d->elem(6) = F(d->elem(6), s->elem(6), ((imm >> 6) & 1));\
1495 222a3336 balrog
            d->elem(7) = F(d->elem(7), s->elem(7), ((imm >> 7) & 1));\
1496 222a3336 balrog
            if (num > 8) {\
1497 222a3336 balrog
                d->elem(8) = F(d->elem(8), s->elem(8), ((imm >> 8) & 1));\
1498 222a3336 balrog
                d->elem(9) = F(d->elem(9), s->elem(9), ((imm >> 9) & 1));\
1499 222a3336 balrog
                d->elem(10) = F(d->elem(10), s->elem(10), ((imm >> 10) & 1));\
1500 222a3336 balrog
                d->elem(11) = F(d->elem(11), s->elem(11), ((imm >> 11) & 1));\
1501 222a3336 balrog
                d->elem(12) = F(d->elem(12), s->elem(12), ((imm >> 12) & 1));\
1502 222a3336 balrog
                d->elem(13) = F(d->elem(13), s->elem(13), ((imm >> 13) & 1));\
1503 222a3336 balrog
                d->elem(14) = F(d->elem(14), s->elem(14), ((imm >> 14) & 1));\
1504 222a3336 balrog
                d->elem(15) = F(d->elem(15), s->elem(15), ((imm >> 15) & 1));\
1505 222a3336 balrog
            }\
1506 222a3336 balrog
        }\
1507 222a3336 balrog
    }\
1508 222a3336 balrog
}
1509 222a3336 balrog
1510 222a3336 balrog
/* SSE4.1 op helpers */
1511 222a3336 balrog
#define FBLENDVB(d, s, m) (m & 0x80) ? s : d
1512 222a3336 balrog
#define FBLENDVPS(d, s, m) (m & 0x80000000) ? s : d
1513 000cacf6 balrog
#define FBLENDVPD(d, s, m) (m & 0x8000000000000000LL) ? s : d
1514 222a3336 balrog
SSE_HELPER_V(helper_pblendvb, B, 16, FBLENDVB)
1515 222a3336 balrog
SSE_HELPER_V(helper_blendvps, L, 4, FBLENDVPS)
1516 222a3336 balrog
SSE_HELPER_V(helper_blendvpd, Q, 2, FBLENDVPD)
1517 222a3336 balrog
1518 222a3336 balrog
void glue(helper_ptest, SUFFIX) (Reg *d, Reg *s)
1519 222a3336 balrog
{
1520 222a3336 balrog
    uint64_t zf = (s->Q(0) &  d->Q(0)) | (s->Q(1) &  d->Q(1));
1521 222a3336 balrog
    uint64_t cf = (s->Q(0) & ~d->Q(0)) | (s->Q(1) & ~d->Q(1));
1522 222a3336 balrog
1523 222a3336 balrog
    CC_SRC = (zf ? 0 : CC_Z) | (cf ? 0 : CC_C);
1524 222a3336 balrog
}
1525 222a3336 balrog
1526 222a3336 balrog
#define SSE_HELPER_F(name, elem, num, F)\
1527 222a3336 balrog
void glue(name, SUFFIX) (Reg *d, Reg *s)\
1528 222a3336 balrog
{\
1529 222a3336 balrog
    d->elem(0) = F(0);\
1530 222a3336 balrog
    d->elem(1) = F(1);\
1531 dcfd12b8 balrog
    if (num > 2) {\
1532 dcfd12b8 balrog
        d->elem(2) = F(2);\
1533 dcfd12b8 balrog
        d->elem(3) = F(3);\
1534 dcfd12b8 balrog
        if (num > 4) {\
1535 dcfd12b8 balrog
            d->elem(4) = F(4);\
1536 dcfd12b8 balrog
            d->elem(5) = F(5);\
1537 222a3336 balrog
            d->elem(6) = F(6);\
1538 222a3336 balrog
            d->elem(7) = F(7);\
1539 222a3336 balrog
        }\
1540 222a3336 balrog
    }\
1541 222a3336 balrog
}
1542 222a3336 balrog
1543 222a3336 balrog
SSE_HELPER_F(helper_pmovsxbw, W, 8, (int8_t) s->B)
1544 222a3336 balrog
SSE_HELPER_F(helper_pmovsxbd, L, 4, (int8_t) s->B)
1545 222a3336 balrog
SSE_HELPER_F(helper_pmovsxbq, Q, 2, (int8_t) s->B)
1546 222a3336 balrog
SSE_HELPER_F(helper_pmovsxwd, L, 4, (int16_t) s->W)
1547 222a3336 balrog
SSE_HELPER_F(helper_pmovsxwq, Q, 2, (int16_t) s->W)
1548 222a3336 balrog
SSE_HELPER_F(helper_pmovsxdq, Q, 2, (int32_t) s->L)
1549 222a3336 balrog
SSE_HELPER_F(helper_pmovzxbw, W, 8, s->B)
1550 222a3336 balrog
SSE_HELPER_F(helper_pmovzxbd, L, 4, s->B)
1551 222a3336 balrog
SSE_HELPER_F(helper_pmovzxbq, Q, 2, s->B)
1552 222a3336 balrog
SSE_HELPER_F(helper_pmovzxwd, L, 4, s->W)
1553 222a3336 balrog
SSE_HELPER_F(helper_pmovzxwq, Q, 2, s->W)
1554 222a3336 balrog
SSE_HELPER_F(helper_pmovzxdq, Q, 2, s->L)
1555 222a3336 balrog
1556 222a3336 balrog
void glue(helper_pmuldq, SUFFIX) (Reg *d, Reg *s)
1557 222a3336 balrog
{
1558 222a3336 balrog
    d->Q(0) = (int64_t) (int32_t) d->L(0) * (int32_t) s->L(0);
1559 222a3336 balrog
    d->Q(1) = (int64_t) (int32_t) d->L(2) * (int32_t) s->L(2);
1560 222a3336 balrog
}
1561 222a3336 balrog
1562 222a3336 balrog
#define FCMPEQQ(d, s) d == s ? -1 : 0
1563 222a3336 balrog
SSE_HELPER_Q(helper_pcmpeqq, FCMPEQQ)
1564 222a3336 balrog
1565 222a3336 balrog
void glue(helper_packusdw, SUFFIX) (Reg *d, Reg *s)
1566 222a3336 balrog
{
1567 222a3336 balrog
    d->W(0) = satuw((int32_t) d->L(0));
1568 222a3336 balrog
    d->W(1) = satuw((int32_t) d->L(1));
1569 222a3336 balrog
    d->W(2) = satuw((int32_t) d->L(2));
1570 222a3336 balrog
    d->W(3) = satuw((int32_t) d->L(3));
1571 222a3336 balrog
    d->W(4) = satuw((int32_t) s->L(0));
1572 222a3336 balrog
    d->W(5) = satuw((int32_t) s->L(1));
1573 222a3336 balrog
    d->W(6) = satuw((int32_t) s->L(2));
1574 222a3336 balrog
    d->W(7) = satuw((int32_t) s->L(3));
1575 222a3336 balrog
}
1576 222a3336 balrog
1577 222a3336 balrog
#define FMINSB(d, s) MIN((int8_t) d, (int8_t) s)
1578 222a3336 balrog
#define FMINSD(d, s) MIN((int32_t) d, (int32_t) s)
1579 222a3336 balrog
#define FMAXSB(d, s) MAX((int8_t) d, (int8_t) s)
1580 222a3336 balrog
#define FMAXSD(d, s) MAX((int32_t) d, (int32_t) s)
1581 222a3336 balrog
SSE_HELPER_B(helper_pminsb, FMINSB)
1582 222a3336 balrog
SSE_HELPER_L(helper_pminsd, FMINSD)
1583 222a3336 balrog
SSE_HELPER_W(helper_pminuw, MIN)
1584 222a3336 balrog
SSE_HELPER_L(helper_pminud, MIN)
1585 222a3336 balrog
SSE_HELPER_B(helper_pmaxsb, FMAXSB)
1586 222a3336 balrog
SSE_HELPER_L(helper_pmaxsd, FMAXSD)
1587 222a3336 balrog
SSE_HELPER_W(helper_pmaxuw, MAX)
1588 222a3336 balrog
SSE_HELPER_L(helper_pmaxud, MAX)
1589 222a3336 balrog
1590 222a3336 balrog
#define FMULLD(d, s) (int32_t) d * (int32_t) s
1591 222a3336 balrog
SSE_HELPER_L(helper_pmulld, FMULLD)
1592 222a3336 balrog
1593 222a3336 balrog
void glue(helper_phminposuw, SUFFIX) (Reg *d, Reg *s)
1594 222a3336 balrog
{
1595 222a3336 balrog
    int idx = 0;
1596 222a3336 balrog
1597 222a3336 balrog
    if (s->W(1) < s->W(idx))
1598 222a3336 balrog
        idx = 1;
1599 222a3336 balrog
    if (s->W(2) < s->W(idx))
1600 222a3336 balrog
        idx = 2;
1601 222a3336 balrog
    if (s->W(3) < s->W(idx))
1602 222a3336 balrog
        idx = 3;
1603 222a3336 balrog
    if (s->W(4) < s->W(idx))
1604 222a3336 balrog
        idx = 4;
1605 222a3336 balrog
    if (s->W(5) < s->W(idx))
1606 222a3336 balrog
        idx = 5;
1607 222a3336 balrog
    if (s->W(6) < s->W(idx))
1608 222a3336 balrog
        idx = 6;
1609 222a3336 balrog
    if (s->W(7) < s->W(idx))
1610 222a3336 balrog
        idx = 7;
1611 222a3336 balrog
1612 222a3336 balrog
    d->Q(1) = 0;
1613 222a3336 balrog
    d->L(1) = 0;
1614 222a3336 balrog
    d->W(1) = idx;
1615 222a3336 balrog
    d->W(0) = s->W(idx);
1616 222a3336 balrog
}
1617 222a3336 balrog
1618 222a3336 balrog
void glue(helper_roundps, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
1619 222a3336 balrog
{
1620 222a3336 balrog
    signed char prev_rounding_mode;
1621 222a3336 balrog
1622 222a3336 balrog
    prev_rounding_mode = env->sse_status.float_rounding_mode;
1623 222a3336 balrog
    if (!(mode & (1 << 2)))
1624 222a3336 balrog
        switch (mode & 3) {
1625 222a3336 balrog
        case 0:
1626 222a3336 balrog
            set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1627 222a3336 balrog
            break;
1628 222a3336 balrog
        case 1:
1629 222a3336 balrog
            set_float_rounding_mode(float_round_down, &env->sse_status);
1630 222a3336 balrog
            break;
1631 222a3336 balrog
        case 2:
1632 222a3336 balrog
            set_float_rounding_mode(float_round_up, &env->sse_status);
1633 222a3336 balrog
            break;
1634 222a3336 balrog
        case 3:
1635 222a3336 balrog
            set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1636 222a3336 balrog
            break;
1637 222a3336 balrog
        }
1638 222a3336 balrog
1639 222a3336 balrog
    d->L(0) = float64_round_to_int(s->L(0), &env->sse_status);
1640 222a3336 balrog
    d->L(1) = float64_round_to_int(s->L(1), &env->sse_status);
1641 222a3336 balrog
    d->L(2) = float64_round_to_int(s->L(2), &env->sse_status);
1642 222a3336 balrog
    d->L(3) = float64_round_to_int(s->L(3), &env->sse_status);
1643 222a3336 balrog
1644 222a3336 balrog
#if 0 /* TODO */
1645 222a3336 balrog
    if (mode & (1 << 3))
1646 222a3336 balrog
        set_float_exception_flags(
1647 222a3336 balrog
                        get_float_exception_flags(&env->sse_status) &
1648 222a3336 balrog
                        ~float_flag_inexact,
1649 222a3336 balrog
                        &env->sse_status);
1650 222a3336 balrog
#endif
1651 222a3336 balrog
    env->sse_status.float_rounding_mode = prev_rounding_mode;
1652 222a3336 balrog
}
1653 222a3336 balrog
1654 222a3336 balrog
void glue(helper_roundpd, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
1655 222a3336 balrog
{
1656 222a3336 balrog
    signed char prev_rounding_mode;
1657 222a3336 balrog
1658 222a3336 balrog
    prev_rounding_mode = env->sse_status.float_rounding_mode;
1659 222a3336 balrog
    if (!(mode & (1 << 2)))
1660 222a3336 balrog
        switch (mode & 3) {
1661 222a3336 balrog
        case 0:
1662 222a3336 balrog
            set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1663 222a3336 balrog
            break;
1664 222a3336 balrog
        case 1:
1665 222a3336 balrog
            set_float_rounding_mode(float_round_down, &env->sse_status);
1666 222a3336 balrog
            break;
1667 222a3336 balrog
        case 2:
1668 222a3336 balrog
            set_float_rounding_mode(float_round_up, &env->sse_status);
1669 222a3336 balrog
            break;
1670 222a3336 balrog
        case 3:
1671 222a3336 balrog
            set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1672 222a3336 balrog
            break;
1673 222a3336 balrog
        }
1674 222a3336 balrog
1675 222a3336 balrog
    d->Q(0) = float64_round_to_int(s->Q(0), &env->sse_status);
1676 222a3336 balrog
    d->Q(1) = float64_round_to_int(s->Q(1), &env->sse_status);
1677 222a3336 balrog
1678 222a3336 balrog
#if 0 /* TODO */
1679 222a3336 balrog
    if (mode & (1 << 3))
1680 222a3336 balrog
        set_float_exception_flags(
1681 222a3336 balrog
                        get_float_exception_flags(&env->sse_status) &
1682 222a3336 balrog
                        ~float_flag_inexact,
1683 222a3336 balrog
                        &env->sse_status);
1684 222a3336 balrog
#endif
1685 222a3336 balrog
    env->sse_status.float_rounding_mode = prev_rounding_mode;
1686 222a3336 balrog
}
1687 222a3336 balrog
1688 222a3336 balrog
void glue(helper_roundss, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
1689 222a3336 balrog
{
1690 222a3336 balrog
    signed char prev_rounding_mode;
1691 222a3336 balrog
1692 222a3336 balrog
    prev_rounding_mode = env->sse_status.float_rounding_mode;
1693 222a3336 balrog
    if (!(mode & (1 << 2)))
1694 222a3336 balrog
        switch (mode & 3) {
1695 222a3336 balrog
        case 0:
1696 222a3336 balrog
            set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1697 222a3336 balrog
            break;
1698 222a3336 balrog
        case 1:
1699 222a3336 balrog
            set_float_rounding_mode(float_round_down, &env->sse_status);
1700 222a3336 balrog
            break;
1701 222a3336 balrog
        case 2:
1702 222a3336 balrog
            set_float_rounding_mode(float_round_up, &env->sse_status);
1703 222a3336 balrog
            break;
1704 222a3336 balrog
        case 3:
1705 222a3336 balrog
            set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1706 222a3336 balrog
            break;
1707 222a3336 balrog
        }
1708 222a3336 balrog
1709 222a3336 balrog
    d->L(0) = float64_round_to_int(s->L(0), &env->sse_status);
1710 222a3336 balrog
1711 222a3336 balrog
#if 0 /* TODO */
1712 222a3336 balrog
    if (mode & (1 << 3))
1713 222a3336 balrog
        set_float_exception_flags(
1714 222a3336 balrog
                        get_float_exception_flags(&env->sse_status) &
1715 222a3336 balrog
                        ~float_flag_inexact,
1716 222a3336 balrog
                        &env->sse_status);
1717 222a3336 balrog
#endif
1718 222a3336 balrog
    env->sse_status.float_rounding_mode = prev_rounding_mode;
1719 222a3336 balrog
}
1720 222a3336 balrog
1721 222a3336 balrog
void glue(helper_roundsd, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
1722 222a3336 balrog
{
1723 222a3336 balrog
    signed char prev_rounding_mode;
1724 222a3336 balrog
1725 222a3336 balrog
    prev_rounding_mode = env->sse_status.float_rounding_mode;
1726 222a3336 balrog
    if (!(mode & (1 << 2)))
1727 222a3336 balrog
        switch (mode & 3) {
1728 222a3336 balrog
        case 0:
1729 222a3336 balrog
            set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1730 222a3336 balrog
            break;
1731 222a3336 balrog
        case 1:
1732 222a3336 balrog
            set_float_rounding_mode(float_round_down, &env->sse_status);
1733 222a3336 balrog
            break;
1734 222a3336 balrog
        case 2:
1735 222a3336 balrog
            set_float_rounding_mode(float_round_up, &env->sse_status);
1736 222a3336 balrog
            break;
1737 222a3336 balrog
        case 3:
1738 222a3336 balrog
            set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1739 222a3336 balrog
            break;
1740 222a3336 balrog
        }
1741 222a3336 balrog
1742 222a3336 balrog
    d->Q(0) = float64_round_to_int(s->Q(0), &env->sse_status);
1743 222a3336 balrog
1744 222a3336 balrog
#if 0 /* TODO */
1745 222a3336 balrog
    if (mode & (1 << 3))
1746 222a3336 balrog
        set_float_exception_flags(
1747 222a3336 balrog
                        get_float_exception_flags(&env->sse_status) &
1748 222a3336 balrog
                        ~float_flag_inexact,
1749 222a3336 balrog
                        &env->sse_status);
1750 222a3336 balrog
#endif
1751 222a3336 balrog
    env->sse_status.float_rounding_mode = prev_rounding_mode;
1752 222a3336 balrog
}
1753 222a3336 balrog
1754 222a3336 balrog
#define FBLENDP(d, s, m) m ? s : d
1755 222a3336 balrog
SSE_HELPER_I(helper_blendps, L, 4, FBLENDP)
1756 222a3336 balrog
SSE_HELPER_I(helper_blendpd, Q, 2, FBLENDP)
1757 222a3336 balrog
SSE_HELPER_I(helper_pblendw, W, 8, FBLENDP)
1758 222a3336 balrog
1759 222a3336 balrog
void glue(helper_dpps, SUFFIX) (Reg *d, Reg *s, uint32_t mask)
1760 222a3336 balrog
{
1761 222a3336 balrog
    float32 iresult = 0 /*float32_zero*/;
1762 222a3336 balrog
1763 222a3336 balrog
    if (mask & (1 << 4))
1764 222a3336 balrog
        iresult = float32_add(iresult,
1765 222a3336 balrog
                        float32_mul(d->L(0), s->L(0), &env->sse_status),
1766 222a3336 balrog
                        &env->sse_status);
1767 222a3336 balrog
    if (mask & (1 << 5))
1768 222a3336 balrog
        iresult = float32_add(iresult,
1769 222a3336 balrog
                        float32_mul(d->L(1), s->L(1), &env->sse_status),
1770 222a3336 balrog
                        &env->sse_status);
1771 222a3336 balrog
    if (mask & (1 << 6))
1772 222a3336 balrog
        iresult = float32_add(iresult,
1773 222a3336 balrog
                        float32_mul(d->L(2), s->L(2), &env->sse_status),
1774 222a3336 balrog
                        &env->sse_status);
1775 222a3336 balrog
    if (mask & (1 << 7))
1776 222a3336 balrog
        iresult = float32_add(iresult,
1777 222a3336 balrog
                        float32_mul(d->L(3), s->L(3), &env->sse_status),
1778 222a3336 balrog
                        &env->sse_status);
1779 222a3336 balrog
    d->L(0) = (mask & (1 << 0)) ? iresult : 0 /*float32_zero*/;
1780 222a3336 balrog
    d->L(1) = (mask & (1 << 1)) ? iresult : 0 /*float32_zero*/;
1781 222a3336 balrog
    d->L(2) = (mask & (1 << 2)) ? iresult : 0 /*float32_zero*/;
1782 222a3336 balrog
    d->L(3) = (mask & (1 << 3)) ? iresult : 0 /*float32_zero*/;
1783 222a3336 balrog
}
1784 222a3336 balrog
1785 222a3336 balrog
void glue(helper_dppd, SUFFIX) (Reg *d, Reg *s, uint32_t mask)
1786 222a3336 balrog
{
1787 222a3336 balrog
    float64 iresult = 0 /*float64_zero*/;
1788 222a3336 balrog
1789 222a3336 balrog
    if (mask & (1 << 4))
1790 222a3336 balrog
        iresult = float64_add(iresult,
1791 222a3336 balrog
                        float64_mul(d->Q(0), s->Q(0), &env->sse_status),
1792 222a3336 balrog
                        &env->sse_status);
1793 222a3336 balrog
    if (mask & (1 << 5))
1794 222a3336 balrog
        iresult = float64_add(iresult,
1795 222a3336 balrog
                        float64_mul(d->Q(1), s->Q(1), &env->sse_status),
1796 222a3336 balrog
                        &env->sse_status);
1797 222a3336 balrog
    d->Q(0) = (mask & (1 << 0)) ? iresult : 0 /*float64_zero*/;
1798 222a3336 balrog
    d->Q(1) = (mask & (1 << 1)) ? iresult : 0 /*float64_zero*/;
1799 222a3336 balrog
}
1800 222a3336 balrog
1801 222a3336 balrog
void glue(helper_mpsadbw, SUFFIX) (Reg *d, Reg *s, uint32_t offset)
1802 222a3336 balrog
{
1803 222a3336 balrog
    int s0 = (offset & 3) << 2;
1804 222a3336 balrog
    int d0 = (offset & 4) << 0;
1805 222a3336 balrog
    int i;
1806 222a3336 balrog
    Reg r;
1807 222a3336 balrog
1808 222a3336 balrog
    for (i = 0; i < 8; i++, d0++) {
1809 222a3336 balrog
        r.W(i) = 0;
1810 222a3336 balrog
        r.W(i) += abs1(d->B(d0 + 0) - s->B(s0 + 0));
1811 222a3336 balrog
        r.W(i) += abs1(d->B(d0 + 1) - s->B(s0 + 1));
1812 222a3336 balrog
        r.W(i) += abs1(d->B(d0 + 2) - s->B(s0 + 2));
1813 222a3336 balrog
        r.W(i) += abs1(d->B(d0 + 3) - s->B(s0 + 3));
1814 222a3336 balrog
    }
1815 222a3336 balrog
1816 222a3336 balrog
    *d = r;
1817 222a3336 balrog
}
1818 222a3336 balrog
1819 222a3336 balrog
/* SSE4.2 op helpers */
1820 222a3336 balrog
/* it's unclear whether signed or unsigned */
1821 222a3336 balrog
#define FCMPGTQ(d, s) d > s ? -1 : 0
1822 222a3336 balrog
SSE_HELPER_Q(helper_pcmpgtq, FCMPGTQ)
1823 222a3336 balrog
1824 222a3336 balrog
static inline int pcmp_elen(int reg, uint32_t ctrl)
1825 222a3336 balrog
{
1826 222a3336 balrog
    int val;
1827 222a3336 balrog
1828 222a3336 balrog
    /* Presence of REX.W is indicated by a bit higher than 7 set */
1829 222a3336 balrog
    if (ctrl >> 8)
1830 222a3336 balrog
        val = abs1((int64_t) env->regs[reg]);
1831 222a3336 balrog
    else
1832 222a3336 balrog
        val = abs1((int32_t) env->regs[reg]);
1833 222a3336 balrog
1834 222a3336 balrog
    if (ctrl & 1) {
1835 222a3336 balrog
        if (val > 8)
1836 222a3336 balrog
            return 8;
1837 222a3336 balrog
    } else
1838 222a3336 balrog
        if (val > 16)
1839 222a3336 balrog
            return 16;
1840 222a3336 balrog
1841 222a3336 balrog
    return val;
1842 222a3336 balrog
}
1843 222a3336 balrog
1844 222a3336 balrog
static inline int pcmp_ilen(Reg *r, uint8_t ctrl)
1845 222a3336 balrog
{
1846 222a3336 balrog
    int val = 0;
1847 222a3336 balrog
1848 222a3336 balrog
    if (ctrl & 1) {
1849 222a3336 balrog
        while (val < 8 && r->W(val))
1850 222a3336 balrog
            val++;
1851 222a3336 balrog
    } else
1852 222a3336 balrog
        while (val < 16 && r->B(val))
1853 222a3336 balrog
            val++;
1854 222a3336 balrog
1855 222a3336 balrog
    return val;
1856 222a3336 balrog
}
1857 222a3336 balrog
1858 222a3336 balrog
static inline int pcmp_val(Reg *r, uint8_t ctrl, int i)
1859 222a3336 balrog
{
1860 222a3336 balrog
    switch ((ctrl >> 0) & 3) {
1861 222a3336 balrog
    case 0:
1862 222a3336 balrog
        return r->B(i);
1863 222a3336 balrog
    case 1:
1864 222a3336 balrog
        return r->W(i);
1865 222a3336 balrog
    case 2:
1866 222a3336 balrog
        return (int8_t) r->B(i);
1867 222a3336 balrog
    case 3:
1868 222a3336 balrog
    default:
1869 222a3336 balrog
        return (int16_t) r->W(i);
1870 222a3336 balrog
    }
1871 222a3336 balrog
}
1872 222a3336 balrog
1873 222a3336 balrog
static inline unsigned pcmpxstrx(Reg *d, Reg *s,
1874 222a3336 balrog
                int8_t ctrl, int valids, int validd)
1875 222a3336 balrog
{
1876 222a3336 balrog
    unsigned int res = 0;
1877 222a3336 balrog
    int v;
1878 222a3336 balrog
    int j, i;
1879 222a3336 balrog
    int upper = (ctrl & 1) ? 7 : 15;
1880 222a3336 balrog
1881 222a3336 balrog
    valids--;
1882 222a3336 balrog
    validd--;
1883 222a3336 balrog
1884 222a3336 balrog
    CC_SRC = (valids < upper ? CC_Z : 0) | (validd < upper ? CC_S : 0);
1885 222a3336 balrog
1886 222a3336 balrog
    switch ((ctrl >> 2) & 3) {
1887 222a3336 balrog
    case 0:
1888 222a3336 balrog
        for (j = valids; j >= 0; j--) {
1889 222a3336 balrog
            res <<= 1;
1890 222a3336 balrog
            v = pcmp_val(s, ctrl, j);
1891 222a3336 balrog
            for (i = validd; i >= 0; i--)
1892 222a3336 balrog
                res |= (v == pcmp_val(d, ctrl, i));
1893 222a3336 balrog
        }
1894 222a3336 balrog
        break;
1895 222a3336 balrog
    case 1:
1896 222a3336 balrog
        for (j = valids; j >= 0; j--) {
1897 222a3336 balrog
            res <<= 1;
1898 222a3336 balrog
            v = pcmp_val(s, ctrl, j);
1899 222a3336 balrog
            for (i = ((validd - 1) | 1); i >= 0; i -= 2)
1900 222a3336 balrog
                res |= (pcmp_val(d, ctrl, i - 0) <= v &&
1901 222a3336 balrog
                        pcmp_val(d, ctrl, i - 1) >= v);
1902 222a3336 balrog
        }
1903 222a3336 balrog
        break;
1904 222a3336 balrog
    case 2:
1905 222a3336 balrog
        res = (2 << (upper - MAX(valids, validd))) - 1;
1906 222a3336 balrog
        res <<= MAX(valids, validd) - MIN(valids, validd);
1907 222a3336 balrog
        for (i = MIN(valids, validd); i >= 0; i--) {
1908 222a3336 balrog
            res <<= 1;
1909 222a3336 balrog
            v = pcmp_val(s, ctrl, i);
1910 222a3336 balrog
            res |= (v == pcmp_val(d, ctrl, i));
1911 222a3336 balrog
        }
1912 222a3336 balrog
        break;
1913 222a3336 balrog
    case 3:
1914 222a3336 balrog
        for (j = valids - validd; j >= 0; j--) {
1915 222a3336 balrog
            res <<= 1;
1916 222a3336 balrog
            res |= 1;
1917 222a3336 balrog
            for (i = MIN(upper - j, validd); i >= 0; i--)
1918 222a3336 balrog
                res &= (pcmp_val(s, ctrl, i + j) == pcmp_val(d, ctrl, i));
1919 222a3336 balrog
        }
1920 222a3336 balrog
        break;
1921 222a3336 balrog
    }
1922 222a3336 balrog
1923 222a3336 balrog
    switch ((ctrl >> 4) & 3) {
1924 222a3336 balrog
    case 1:
1925 222a3336 balrog
        res ^= (2 << upper) - 1;
1926 222a3336 balrog
        break;
1927 222a3336 balrog
    case 3:
1928 222a3336 balrog
        res ^= (2 << valids) - 1;
1929 222a3336 balrog
        break;
1930 222a3336 balrog
    }
1931 222a3336 balrog
1932 222a3336 balrog
    if (res)
1933 222a3336 balrog
       CC_SRC |= CC_C;
1934 222a3336 balrog
    if (res & 1)
1935 222a3336 balrog
       CC_SRC |= CC_O;
1936 222a3336 balrog
1937 222a3336 balrog
    return res;
1938 222a3336 balrog
}
1939 222a3336 balrog
1940 222a3336 balrog
static inline int rffs1(unsigned int val)
1941 222a3336 balrog
{
1942 222a3336 balrog
    int ret = 1, hi;
1943 222a3336 balrog
1944 222a3336 balrog
    for (hi = sizeof(val) * 4; hi; hi /= 2)
1945 222a3336 balrog
        if (val >> hi) {
1946 222a3336 balrog
            val >>= hi;
1947 222a3336 balrog
            ret += hi;
1948 222a3336 balrog
        }
1949 222a3336 balrog
1950 222a3336 balrog
    return ret;
1951 222a3336 balrog
}
1952 222a3336 balrog
1953 222a3336 balrog
static inline int ffs1(unsigned int val)
1954 222a3336 balrog
{
1955 222a3336 balrog
    int ret = 1, hi;
1956 222a3336 balrog
1957 222a3336 balrog
    for (hi = sizeof(val) * 4; hi; hi /= 2)
1958 222a3336 balrog
        if (val << hi) {
1959 222a3336 balrog
            val <<= hi;
1960 222a3336 balrog
            ret += hi;
1961 222a3336 balrog
        }
1962 222a3336 balrog
1963 222a3336 balrog
    return ret;
1964 222a3336 balrog
}
1965 222a3336 balrog
1966 222a3336 balrog
void glue(helper_pcmpestri, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
1967 222a3336 balrog
{
1968 222a3336 balrog
    unsigned int res = pcmpxstrx(d, s, ctrl,
1969 222a3336 balrog
                    pcmp_elen(R_EDX, ctrl),
1970 222a3336 balrog
                    pcmp_elen(R_EAX, ctrl));
1971 222a3336 balrog
1972 222a3336 balrog
    if (res)
1973 222a3336 balrog
        env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1;
1974 222a3336 balrog
    else
1975 222a3336 balrog
        env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
1976 222a3336 balrog
}
1977 222a3336 balrog
1978 222a3336 balrog
void glue(helper_pcmpestrm, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
1979 222a3336 balrog
{
1980 222a3336 balrog
    int i;
1981 222a3336 balrog
    unsigned int res = pcmpxstrx(d, s, ctrl,
1982 222a3336 balrog
                    pcmp_elen(R_EDX, ctrl),
1983 222a3336 balrog
                    pcmp_elen(R_EAX, ctrl));
1984 222a3336 balrog
1985 222a3336 balrog
    if ((ctrl >> 6) & 1) {
1986 222a3336 balrog
        if (ctrl & 1)
1987 222a3336 balrog
            for (i = 0; i <= 8; i--, res >>= 1)
1988 222a3336 balrog
                d->W(i) = (res & 1) ? ~0 : 0;
1989 222a3336 balrog
        else
1990 222a3336 balrog
            for (i = 0; i <= 16; i--, res >>= 1)
1991 222a3336 balrog
                d->B(i) = (res & 1) ? ~0 : 0;
1992 222a3336 balrog
    } else {
1993 222a3336 balrog
        d->Q(1) = 0;
1994 222a3336 balrog
        d->Q(0) = res;
1995 222a3336 balrog
    }
1996 222a3336 balrog
}
1997 222a3336 balrog
1998 222a3336 balrog
void glue(helper_pcmpistri, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
1999 222a3336 balrog
{
2000 222a3336 balrog
    unsigned int res = pcmpxstrx(d, s, ctrl,
2001 222a3336 balrog
                    pcmp_ilen(s, ctrl),
2002 222a3336 balrog
                    pcmp_ilen(d, ctrl));
2003 222a3336 balrog
2004 222a3336 balrog
    if (res)
2005 222a3336 balrog
        env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1;
2006 222a3336 balrog
    else
2007 222a3336 balrog
        env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
2008 222a3336 balrog
}
2009 222a3336 balrog
2010 222a3336 balrog
void glue(helper_pcmpistrm, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
2011 222a3336 balrog
{
2012 222a3336 balrog
    int i;
2013 222a3336 balrog
    unsigned int res = pcmpxstrx(d, s, ctrl,
2014 222a3336 balrog
                    pcmp_ilen(s, ctrl),
2015 222a3336 balrog
                    pcmp_ilen(d, ctrl));
2016 222a3336 balrog
2017 222a3336 balrog
    if ((ctrl >> 6) & 1) {
2018 222a3336 balrog
        if (ctrl & 1)
2019 222a3336 balrog
            for (i = 0; i <= 8; i--, res >>= 1)
2020 222a3336 balrog
                d->W(i) = (res & 1) ? ~0 : 0;
2021 222a3336 balrog
        else
2022 222a3336 balrog
            for (i = 0; i <= 16; i--, res >>= 1)
2023 222a3336 balrog
                d->B(i) = (res & 1) ? ~0 : 0;
2024 222a3336 balrog
    } else {
2025 222a3336 balrog
        d->Q(1) = 0;
2026 222a3336 balrog
        d->Q(0) = res;
2027 222a3336 balrog
    }
2028 222a3336 balrog
}
2029 222a3336 balrog
2030 222a3336 balrog
#define CRCPOLY        0x1edc6f41
2031 222a3336 balrog
#define CRCPOLY_BITREV 0x82f63b78
2032 222a3336 balrog
target_ulong helper_crc32(uint32_t crc1, target_ulong msg, uint32_t len)
2033 222a3336 balrog
{
2034 222a3336 balrog
    target_ulong crc = (msg & ((target_ulong) -1 >>
2035 222a3336 balrog
                            (TARGET_LONG_BITS - len))) ^ crc1;
2036 222a3336 balrog
2037 222a3336 balrog
    while (len--)
2038 222a3336 balrog
        crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_BITREV : 0);
2039 222a3336 balrog
2040 222a3336 balrog
    return crc;
2041 222a3336 balrog
}
2042 222a3336 balrog
2043 222a3336 balrog
#define POPMASK(i)     ((target_ulong) -1 / ((1LL << (1 << i)) + 1))
2044 222a3336 balrog
#define POPCOUNT(n, i) (n & POPMASK(i)) + ((n >> (1 << i)) & POPMASK(i))
2045 222a3336 balrog
target_ulong helper_popcnt(target_ulong n, uint32_t type)
2046 222a3336 balrog
{
2047 222a3336 balrog
    CC_SRC = n ? 0 : CC_Z;
2048 222a3336 balrog
2049 222a3336 balrog
    n = POPCOUNT(n, 0);
2050 222a3336 balrog
    n = POPCOUNT(n, 1);
2051 222a3336 balrog
    n = POPCOUNT(n, 2);
2052 222a3336 balrog
    n = POPCOUNT(n, 3);
2053 222a3336 balrog
    if (type == 1)
2054 222a3336 balrog
        return n & 0xff;
2055 222a3336 balrog
2056 222a3336 balrog
    n = POPCOUNT(n, 4);
2057 222a3336 balrog
#ifndef TARGET_X86_64
2058 222a3336 balrog
    return n;
2059 222a3336 balrog
#else
2060 222a3336 balrog
    if (type == 2)
2061 222a3336 balrog
        return n & 0xff;
2062 222a3336 balrog
2063 222a3336 balrog
    return POPCOUNT(n, 5);
2064 222a3336 balrog
#endif
2065 222a3336 balrog
}
2066 222a3336 balrog
#endif
2067 222a3336 balrog
2068 664e0f19 bellard
#undef SHIFT
2069 664e0f19 bellard
#undef XMM_ONLY
2070 664e0f19 bellard
#undef Reg
2071 664e0f19 bellard
#undef B
2072 664e0f19 bellard
#undef W
2073 664e0f19 bellard
#undef L
2074 664e0f19 bellard
#undef Q
2075 664e0f19 bellard
#undef SUFFIX