Revision 5578ceab target-sparc/op_helper.c

b/target-sparc/op_helper.c
1203 1203
                                    (val & 0x00ffffff);
1204 1204
                // Mappings generated during no-fault mode or MMU
1205 1205
                // disabled mode are invalid in normal mode
1206
                if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
1207
                    (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
1206
                if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1207
                    (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
1208 1208
                    tlb_flush(env, 1);
1209 1209
                break;
1210 1210
            case 1: // Context Table Pointer Register
1211
                env->mmuregs[reg] = val & env->mmu_ctpr_mask;
1211
                env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
1212 1212
                break;
1213 1213
            case 2: // Context Register
1214
                env->mmuregs[reg] = val & env->mmu_cxr_mask;
1214
                env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
1215 1215
                if (oldreg != env->mmuregs[reg]) {
1216 1216
                    /* we flush when the MMU context changes because
1217 1217
                       QEMU has no MMU context support */
......
1222 1222
            case 4: // Synchronous Fault Address Register
1223 1223
                break;
1224 1224
            case 0x10: // TLB Replacement Control Register
1225
                env->mmuregs[reg] = val & env->mmu_trcr_mask;
1225
                env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
1226 1226
                break;
1227 1227
            case 0x13: // Synchronous Fault Status Register with Read and Clear
1228
                env->mmuregs[3] = val & env->mmu_sfsr_mask;
1228
                env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
1229 1229
                break;
1230 1230
            case 0x14: // Synchronous Fault Address Register
1231 1231
                env->mmuregs[4] = val;
......
1552 1552
#endif
1553 1553

  
1554 1554
    if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1555
        || ((env->features & CPU_FEATURE_HYPV) && asi >= 0x30 && asi < 0x80
1555
        || ((env->def->features & CPU_FEATURE_HYPV)
1556
            && asi >= 0x30 && asi < 0x80
1556 1557
            && !(env->hpstate & HS_PRIV)))
1557 1558
        raise_exception(TT_PRIV_ACT);
1558 1559

  
......
1565 1566
    case 0x88: // Primary LE
1566 1567
    case 0x8a: // Primary no-fault LE
1567 1568
        if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1568
            if ((env->features & CPU_FEATURE_HYPV) && env->hpstate & HS_PRIV) {
1569
            if ((env->def->features & CPU_FEATURE_HYPV)
1570
                && env->hpstate & HS_PRIV) {
1569 1571
                switch(size) {
1570 1572
                case 1:
1571 1573
                    ret = ldub_hypv(addr);
......
1791 1793
    dump_asi("write", addr, asi, size, val);
1792 1794
#endif
1793 1795
    if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1794
        || ((env->features & CPU_FEATURE_HYPV) && asi >= 0x30 && asi < 0x80
1796
        || ((env->def->features & CPU_FEATURE_HYPV)
1797
            && asi >= 0x30 && asi < 0x80
1795 1798
            && !(env->hpstate & HS_PRIV)))
1796 1799
        raise_exception(TT_PRIV_ACT);
1797 1800

  
......
1828 1831
    case 0x80: // Primary
1829 1832
    case 0x88: // Primary LE
1830 1833
        if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1831
            if ((env->features & CPU_FEATURE_HYPV) && env->hpstate & HS_PRIV) {
1834
            if ((env->def->features & CPU_FEATURE_HYPV)
1835
                && env->hpstate & HS_PRIV) {
1832 1836
                switch(size) {
1833 1837
                case 1:
1834 1838
                    stb_hypv(addr, val);
......
2108 2112
void helper_ldda_asi(target_ulong addr, int asi, int rd)
2109 2113
{
2110 2114
    if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2111
        || ((env->features & CPU_FEATURE_HYPV) && asi >= 0x30 && asi < 0x80
2115
        || ((env->def->features & CPU_FEATURE_HYPV)
2116
            && asi >= 0x30 && asi < 0x80
2112 2117
            && !(env->hpstate & HS_PRIV)))
2113 2118
        raise_exception(TT_PRIV_ACT);
2114 2119

  
......
2682 2687

  
2683 2688
void helper_wrpstate(target_ulong new_state)
2684 2689
{
2685
    if (!(env->features & CPU_FEATURE_GL))
2690
    if (!(env->def->features & CPU_FEATURE_GL))
2686 2691
        change_pstate(new_state & 0xf3f);
2687 2692
}
2688 2693

  

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