Revision 5578ceab target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 59 | 59 |
int fpu_enabled; |
| 60 | 60 |
int address_mask_32bit; |
| 61 | 61 |
struct TranslationBlock *tb; |
| 62 |
uint32_t features;
|
|
| 62 |
sparc_def_t *def;
|
|
| 63 | 63 |
} DisasContext; |
| 64 | 64 |
|
| 65 | 65 |
// This function uses non-native bit order |
| ... | ... | |
| 1905 | 1905 |
} |
| 1906 | 1906 |
|
| 1907 | 1907 |
#define CHECK_IU_FEATURE(dc, FEATURE) \ |
| 1908 |
if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
|
|
| 1908 |
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
|
|
| 1909 | 1909 |
goto illegal_insn; |
| 1910 | 1910 |
#define CHECK_FPU_FEATURE(dc, FEATURE) \ |
| 1911 |
if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
|
|
| 1911 |
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
|
|
| 1912 | 1912 |
goto nfpu_insn; |
| 1913 | 1913 |
|
| 1914 | 1914 |
/* before an instruction, dc->pc must be static */ |
| ... | ... | |
| 4141 | 4141 |
goto jmp_insn; |
| 4142 | 4142 |
#endif |
| 4143 | 4143 |
case 0x3b: /* flush */ |
| 4144 |
if (!((dc)->features & CPU_FEATURE_FLUSH)) |
|
| 4144 |
if (!((dc)->def->features & CPU_FEATURE_FLUSH))
|
|
| 4145 | 4145 |
goto unimp_flush; |
| 4146 | 4146 |
tcg_gen_helper_0_1(helper_flush, cpu_dst); |
| 4147 | 4147 |
break; |
| ... | ... | |
| 4742 | 4742 |
last_pc = dc->pc; |
| 4743 | 4743 |
dc->npc = (target_ulong) tb->cs_base; |
| 4744 | 4744 |
dc->mem_idx = cpu_mmu_index(env); |
| 4745 |
dc->features = env->features;
|
|
| 4746 |
if ((dc->features & CPU_FEATURE_FLOAT)) {
|
|
| 4745 |
dc->def = env->def;
|
|
| 4746 |
if ((dc->def->features & CPU_FEATURE_FLOAT))
|
|
| 4747 | 4747 |
dc->fpu_enabled = cpu_fpu_enabled(env); |
| 4748 |
#if defined(CONFIG_USER_ONLY) |
|
| 4749 |
dc->features |= CPU_FEATURE_FLOAT128; |
|
| 4750 |
#endif |
|
| 4751 |
} else |
|
| 4748 |
else |
|
| 4752 | 4749 |
dc->fpu_enabled = 0; |
| 4753 | 4750 |
#ifdef TARGET_SPARC64 |
| 4754 | 4751 |
dc->address_mask_32bit = env->pstate & PS_AM; |
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