Revision 559dd74d target-sh4/translate.c
b/target-sh4/translate.c | ||
---|---|---|
70 | 70 |
{ |
71 | 71 |
int i; |
72 | 72 |
static int done_init = 0; |
73 |
static const char * const gregnames[24] = {
|
|
73 |
static const char * const gregnames[24] = { |
|
74 | 74 |
"R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
75 | 75 |
"R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", |
76 | 76 |
"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", |
... | ... | |
344 | 344 |
case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
345 | 345 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
346 | 346 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
347 |
gen_op_addl_imm_T1(B3_0 * 4);
|
|
347 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0 * 4);
|
|
348 | 348 |
gen_op_stl_T0_T1(ctx); |
349 | 349 |
return; |
350 | 350 |
case 0x5000: /* mov.l @(disp,Rm),Rn */ |
351 | 351 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
352 |
gen_op_addl_imm_T0(B3_0 * 4);
|
|
352 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0 * 4);
|
|
353 | 353 |
gen_op_ldl_T0_T0(ctx); |
354 | 354 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
355 | 355 |
return; |
... | ... | |
367 | 367 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
368 | 368 |
return; |
369 | 369 |
case 0x7000: /* add #imm,Rn */ |
370 |
gen_op_add_imm_rN(B7_0s, REG(B11_8));
|
|
370 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], B7_0s);
|
|
371 | 371 |
return; |
372 | 372 |
case 0xa000: /* bra disp */ |
373 | 373 |
CHECK_NOT_DELAY_SLOT |
... | ... | |
419 | 419 |
return; |
420 | 420 |
case 0x2004: /* mov.b Rm,@-Rn */ |
421 | 421 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
422 |
gen_op_dec1_rN(REG(B11_8)); /* modify register status */ |
|
422 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
423 |
cpu_gregs[REG(B11_8)], 1); /* modify register status */ |
|
423 | 424 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
424 |
gen_op_inc1_rN(REG(B11_8)); /* recover register status */ |
|
425 |
gen_op_stb_T0_T1(ctx); /* might cause re-execution */ |
|
426 |
gen_op_dec1_rN(REG(B11_8)); /* modify register status */ |
|
425 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], |
|
426 |
cpu_gregs[REG(B11_8)], 1); /* recover register status */ |
|
427 |
gen_op_stb_T0_T1(ctx); /* might cause re-execution */ |
|
428 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
429 |
cpu_gregs[REG(B11_8)], 1); /* modify register status */ |
|
427 | 430 |
return; |
428 | 431 |
case 0x2005: /* mov.w Rm,@-Rn */ |
429 | 432 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
430 |
gen_op_dec2_rN(REG(B11_8)); |
|
433 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
434 |
cpu_gregs[REG(B11_8)], 2); |
|
431 | 435 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
432 |
gen_op_inc2_rN(REG(B11_8)); |
|
436 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], |
|
437 |
cpu_gregs[REG(B11_8)], 2); |
|
433 | 438 |
gen_op_stw_T0_T1(ctx); |
434 |
gen_op_dec2_rN(REG(B11_8)); |
|
439 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
440 |
cpu_gregs[REG(B11_8)], 2); |
|
435 | 441 |
return; |
436 | 442 |
case 0x2006: /* mov.l Rm,@-Rn */ |
437 | 443 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
438 |
gen_op_dec4_rN(REG(B11_8)); |
|
444 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
445 |
cpu_gregs[REG(B11_8)], 4); |
|
439 | 446 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
440 |
gen_op_inc4_rN(REG(B11_8)); |
|
447 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], |
|
448 |
cpu_gregs[REG(B11_8)], 4); |
|
441 | 449 |
gen_op_stl_T0_T1(ctx); |
442 |
gen_op_dec4_rN(REG(B11_8)); |
|
450 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
451 |
cpu_gregs[REG(B11_8)], 4); |
|
443 | 452 |
return; |
444 | 453 |
case 0x6004: /* mov.b @Rm+,Rn */ |
445 | 454 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
446 | 455 |
gen_op_ldb_T0_T0(ctx); |
447 | 456 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
448 | 457 |
if ( B11_8 != B7_4 ) |
449 |
gen_op_inc1_rN(REG(B7_4)); |
|
458 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
|
459 |
cpu_gregs[REG(B7_4)], 1); |
|
450 | 460 |
return; |
451 | 461 |
case 0x6005: /* mov.w @Rm+,Rn */ |
452 | 462 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
453 | 463 |
gen_op_ldw_T0_T0(ctx); |
454 | 464 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
455 | 465 |
if ( B11_8 != B7_4 ) |
456 |
gen_op_inc2_rN(REG(B7_4)); |
|
466 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
|
467 |
cpu_gregs[REG(B7_4)], 2); |
|
457 | 468 |
return; |
458 | 469 |
case 0x6006: /* mov.l @Rm+,Rn */ |
459 | 470 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
460 | 471 |
gen_op_ldl_T0_T0(ctx); |
461 | 472 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
462 | 473 |
if ( B11_8 != B7_4 ) |
463 |
gen_op_inc4_rN(REG(B7_4)); |
|
474 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
|
475 |
cpu_gregs[REG(B7_4)], 4); |
|
464 | 476 |
return; |
465 | 477 |
case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
466 | 478 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
467 | 479 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
468 |
gen_op_add_rN_T1(REG(0));
|
|
480 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
|
469 | 481 |
gen_op_stb_T0_T1(ctx); |
470 | 482 |
return; |
471 | 483 |
case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
472 | 484 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
473 | 485 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
474 |
gen_op_add_rN_T1(REG(0));
|
|
486 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
|
475 | 487 |
gen_op_stw_T0_T1(ctx); |
476 | 488 |
return; |
477 | 489 |
case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
478 | 490 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
479 | 491 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
480 |
gen_op_add_rN_T1(REG(0));
|
|
492 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
|
481 | 493 |
gen_op_stl_T0_T1(ctx); |
482 | 494 |
return; |
483 | 495 |
case 0x000c: /* mov.b @(R0,Rm),Rn */ |
484 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
485 |
gen_op_add_rN_T0(REG(0)); |
|
496 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
|
486 | 497 |
gen_op_ldb_T0_T0(ctx); |
487 | 498 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
488 | 499 |
return; |
489 | 500 |
case 0x000d: /* mov.w @(R0,Rm),Rn */ |
490 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
491 |
gen_op_add_rN_T0(REG(0)); |
|
501 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
|
492 | 502 |
gen_op_ldw_T0_T0(ctx); |
493 | 503 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
494 | 504 |
return; |
495 | 505 |
case 0x000e: /* mov.l @(R0,Rm),Rn */ |
496 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
497 |
gen_op_add_rN_T0(REG(0)); |
|
506 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
|
498 | 507 |
gen_op_ldl_T0_T0(ctx); |
499 | 508 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
500 | 509 |
return; |
501 | 510 |
case 0x6008: /* swap.b Rm,Rn */ |
502 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
503 |
gen_op_swapb_T0(); |
|
504 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
511 |
tcg_gen_andi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], 0xffff0000); |
|
512 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xff); |
|
513 |
tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 8); |
|
514 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
515 |
tcg_gen_shri_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 8); |
|
516 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff); |
|
517 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
505 | 518 |
return; |
506 | 519 |
case 0x6009: /* swap.w Rm,Rn */ |
507 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
508 |
gen_op_swapw_T0(); |
|
509 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
520 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xffff); |
|
521 |
tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 16); |
|
522 |
tcg_gen_shri_i32(cpu_T[1], cpu_gregs[REG(B7_4)], 16); |
|
523 |
tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff); |
|
524 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_T[0], cpu_T[1]); |
|
510 | 525 |
return; |
511 | 526 |
case 0x200d: /* xtrct Rm,Rn */ |
512 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
513 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
514 |
gen_op_xtrct_T0_T1(); |
|
515 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); |
|
527 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xffff); |
|
528 |
tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 16); |
|
529 |
tcg_gen_shri_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 16); |
|
530 |
tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff); |
|
531 |
tcg_gen_ori_i32(cpu_gregs[REG(B11_8)], cpu_T[0], cpu_T[1]); |
|
516 | 532 |
return; |
517 | 533 |
case 0x300c: /* add Rm,Rn */ |
518 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
519 |
gen_op_add_T0_rN(REG(B11_8)); |
|
534 |
tcg_gen_add_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
|
520 | 535 |
return; |
521 | 536 |
case 0x300e: /* addc Rm,Rn */ |
522 | 537 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
... | ... | |
531 | 546 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); |
532 | 547 |
return; |
533 | 548 |
case 0x2009: /* and Rm,Rn */ |
534 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
535 |
gen_op_and_T0_rN(REG(B11_8)); |
|
549 |
tcg_gen_and_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
|
536 | 550 |
return; |
537 | 551 |
case 0x3000: /* cmp/eq Rm,Rn */ |
538 | 552 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
... | ... | |
614 | 628 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
615 | 629 |
gen_op_ldl_T0_T0(ctx); |
616 | 630 |
gen_op_macl_T0_T1(); |
617 |
gen_op_inc4_rN(REG(B11_8));
|
|
618 |
gen_op_inc4_rN(REG(B7_4));
|
|
631 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], cpu_gregs[REG(B7_4)], 4);
|
|
632 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
619 | 633 |
return; |
620 | 634 |
case 0x400f: /* mac.w @Rm+,@Rn+ */ |
621 | 635 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
... | ... | |
624 | 638 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
625 | 639 |
gen_op_ldl_T0_T0(ctx); |
626 | 640 |
gen_op_macw_T0_T1(); |
627 |
gen_op_inc2_rN(REG(B11_8));
|
|
628 |
gen_op_inc2_rN(REG(B7_4));
|
|
641 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
|
642 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], cpu_gregs[REG(B7_4)], 2);
|
|
629 | 643 |
return; |
630 | 644 |
case 0x0007: /* mul.l Rm,Rn */ |
631 | 645 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
... | ... | |
649 | 663 |
gen_op_muluw_T0_T1(); |
650 | 664 |
return; |
651 | 665 |
case 0x600b: /* neg Rm,Rn */ |
652 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
653 |
gen_op_neg_T0(); |
|
654 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
666 |
tcg_gen_neg_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
|
655 | 667 |
return; |
656 | 668 |
case 0x600a: /* negc Rm,Rn */ |
657 | 669 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
... | ... | |
659 | 671 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
660 | 672 |
return; |
661 | 673 |
case 0x6007: /* not Rm,Rn */ |
662 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
663 |
gen_op_not_T0(); |
|
664 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
674 |
tcg_gen_not_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
|
665 | 675 |
return; |
666 | 676 |
case 0x200b: /* or Rm,Rn */ |
667 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
668 |
gen_op_or_T0_rN(REG(B11_8)); |
|
677 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
|
669 | 678 |
return; |
670 | 679 |
case 0x400c: /* shad Rm,Rn */ |
671 | 680 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
... | ... | |
680 | 689 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); |
681 | 690 |
return; |
682 | 691 |
case 0x3008: /* sub Rm,Rn */ |
683 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
684 |
gen_op_sub_T0_rN(REG(B11_8)); |
|
692 |
tcg_gen_sub_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
|
685 | 693 |
return; |
686 | 694 |
case 0x300a: /* subc Rm,Rn */ |
687 | 695 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
... | ... | |
701 | 709 |
gen_op_tst_T0_T1(); |
702 | 710 |
return; |
703 | 711 |
case 0x200a: /* xor Rm,Rn */ |
704 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
705 |
gen_op_xor_T0_rN(REG(B11_8)); |
|
712 |
tcg_gen_xor_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
|
706 | 713 |
return; |
707 | 714 |
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
708 | 715 |
if (ctx->fpscr & FPSCR_SZ) { |
... | ... | |
740 | 747 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
741 | 748 |
gen_op_ldfq_T0_DT0(ctx); |
742 | 749 |
gen_op_fmov_DT0_drN(XREG(B11_8)); |
743 |
gen_op_inc8_rN(REG(B7_4)); |
|
750 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
|
751 |
cpu_gregs[REG(B7_4)], 8); |
|
744 | 752 |
} else { |
745 | 753 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
746 | 754 |
gen_op_ldfl_T0_FT0(ctx); |
747 | 755 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
748 |
gen_op_inc4_rN(REG(B7_4)); |
|
756 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
|
757 |
cpu_gregs[REG(B7_4)], 4); |
|
749 | 758 |
} |
750 | 759 |
return; |
751 | 760 |
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
752 | 761 |
if (ctx->fpscr & FPSCR_SZ) { |
753 |
gen_op_dec8_rN(REG(B11_8));
|
|
762 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
754 | 763 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
755 | 764 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
756 |
gen_op_inc8_rN(REG(B11_8));
|
|
765 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
757 | 766 |
gen_op_stfq_DT0_T1(ctx); |
758 |
gen_op_dec8_rN(REG(B11_8));
|
|
767 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
759 | 768 |
} else { |
760 |
gen_op_dec4_rN(REG(B11_8));
|
|
769 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
761 | 770 |
gen_op_fmov_frN_FT0(FREG(B7_4)); |
762 | 771 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
763 |
gen_op_inc4_rN(REG(B11_8));
|
|
772 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
764 | 773 |
gen_op_stfl_FT0_T1(ctx); |
765 |
gen_op_dec4_rN(REG(B11_8));
|
|
774 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
766 | 775 |
} |
767 | 776 |
return; |
768 | 777 |
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
778 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
|
769 | 779 |
if (ctx->fpscr & FPSCR_SZ) { |
770 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
771 |
gen_op_add_rN_T0(REG(0)); |
|
772 | 780 |
gen_op_ldfq_T0_DT0(ctx); |
773 | 781 |
gen_op_fmov_DT0_drN(XREG(B11_8)); |
774 | 782 |
} else { |
775 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
776 |
gen_op_add_rN_T0(REG(0)); |
|
777 | 783 |
gen_op_ldfl_T0_FT0(ctx); |
778 | 784 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
779 | 785 |
} |
... | ... | |
782 | 788 |
if (ctx->fpscr & FPSCR_SZ) { |
783 | 789 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
784 | 790 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
785 |
gen_op_add_rN_T1(REG(0));
|
|
791 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
|
786 | 792 |
gen_op_stfq_DT0_T1(ctx); |
787 | 793 |
} else { |
788 | 794 |
gen_op_fmov_frN_FT0(FREG(B7_4)); |
789 | 795 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
790 |
gen_op_add_rN_T1(REG(0));
|
|
796 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
|
791 | 797 |
gen_op_stfl_FT0_T1(ctx); |
792 | 798 |
} |
793 | 799 |
return; |
... | ... | |
840 | 846 |
|
841 | 847 |
switch (ctx->opcode & 0xff00) { |
842 | 848 |
case 0xc900: /* and #imm,R0 */ |
843 |
gen_op_and_imm_rN(B7_0, REG(0));
|
|
849 |
tcg_gen_andi_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0);
|
|
844 | 850 |
return; |
845 | 851 |
case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
846 | 852 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
847 | 853 |
gen_op_addl_GBR_T0(); |
848 | 854 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
849 | 855 |
gen_op_ldub_T0_T0(ctx); |
850 |
gen_op_and_imm_T0(B7_0);
|
|
856 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0);
|
|
851 | 857 |
gen_op_stb_T0_T1(ctx); |
852 | 858 |
return; |
853 | 859 |
case 0x8b00: /* bf label */ |
... | ... | |
878 | 884 |
return; |
879 | 885 |
case 0xc400: /* mov.b @(disp,GBR),R0 */ |
880 | 886 |
gen_op_stc_gbr_T0(); |
881 |
gen_op_addl_imm_T0(B7_0);
|
|
887 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0);
|
|
882 | 888 |
gen_op_ldb_T0_T0(ctx); |
883 | 889 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
884 | 890 |
return; |
885 | 891 |
case 0xc500: /* mov.w @(disp,GBR),R0 */ |
886 | 892 |
gen_op_stc_gbr_T0(); |
887 |
gen_op_addl_imm_T0(B7_0 * 2);
|
|
893 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 2);
|
|
888 | 894 |
gen_op_ldw_T0_T0(ctx); |
889 | 895 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
890 | 896 |
return; |
891 | 897 |
case 0xc600: /* mov.l @(disp,GBR),R0 */ |
892 | 898 |
gen_op_stc_gbr_T0(); |
893 |
gen_op_addl_imm_T0(B7_0 * 4);
|
|
899 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 4);
|
|
894 | 900 |
gen_op_ldl_T0_T0(ctx); |
895 | 901 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
896 | 902 |
return; |
897 | 903 |
case 0xc000: /* mov.b R0,@(disp,GBR) */ |
898 | 904 |
gen_op_stc_gbr_T0(); |
899 |
gen_op_addl_imm_T0(B7_0);
|
|
905 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0);
|
|
900 | 906 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
901 | 907 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
902 | 908 |
gen_op_stb_T0_T1(ctx); |
903 | 909 |
return; |
904 | 910 |
case 0xc100: /* mov.w R0,@(disp,GBR) */ |
905 | 911 |
gen_op_stc_gbr_T0(); |
906 |
gen_op_addl_imm_T0(B7_0 * 2);
|
|
912 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 2);
|
|
907 | 913 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
908 | 914 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
909 | 915 |
gen_op_stw_T0_T1(ctx); |
910 | 916 |
return; |
911 | 917 |
case 0xc200: /* mov.l R0,@(disp,GBR) */ |
912 | 918 |
gen_op_stc_gbr_T0(); |
913 |
gen_op_addl_imm_T0(B7_0 * 4);
|
|
919 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 4);
|
|
914 | 920 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
915 | 921 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
916 | 922 |
gen_op_stl_T0_T1(ctx); |
... | ... | |
918 | 924 |
case 0x8000: /* mov.b R0,@(disp,Rn) */ |
919 | 925 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
920 | 926 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]); |
921 |
gen_op_addl_imm_T1(B3_0);
|
|
927 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0);
|
|
922 | 928 |
gen_op_stb_T0_T1(ctx); |
923 | 929 |
return; |
924 | 930 |
case 0x8100: /* mov.w R0,@(disp,Rn) */ |
925 | 931 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
926 | 932 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]); |
927 |
gen_op_addl_imm_T1(B3_0 * 2);
|
|
933 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0 * 2);
|
|
928 | 934 |
gen_op_stw_T0_T1(ctx); |
929 | 935 |
return; |
930 | 936 |
case 0x8400: /* mov.b @(disp,Rn),R0 */ |
931 | 937 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
932 |
gen_op_addl_imm_T0(B3_0);
|
|
938 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0);
|
|
933 | 939 |
gen_op_ldb_T0_T0(ctx); |
934 | 940 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
935 | 941 |
return; |
936 | 942 |
case 0x8500: /* mov.w @(disp,Rn),R0 */ |
937 | 943 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
938 |
gen_op_addl_imm_T0(B3_0 * 2);
|
|
944 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0 * 2);
|
|
939 | 945 |
gen_op_ldw_T0_T0(ctx); |
940 | 946 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
941 | 947 |
return; |
... | ... | |
944 | 950 |
((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
945 | 951 |
return; |
946 | 952 |
case 0xcb00: /* or #imm,R0 */ |
947 |
gen_op_or_imm_rN(B7_0, REG(0));
|
|
953 |
tcg_gen_ori_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0);
|
|
948 | 954 |
return; |
949 | 955 |
case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
950 | 956 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
951 | 957 |
gen_op_addl_GBR_T0(); |
952 | 958 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
953 | 959 |
gen_op_ldub_T0_T0(ctx); |
954 |
gen_op_or_imm_T0(B7_0);
|
|
960 |
tcg_gen_ori_i32(cpu_T[0], cpu_T[0], B7_0);
|
|
955 | 961 |
gen_op_stb_T0_T1(ctx); |
956 | 962 |
return; |
957 | 963 |
case 0xc300: /* trapa #imm */ |
... | ... | |
969 | 975 |
gen_op_tst_imm_T0(B7_0); |
970 | 976 |
return; |
971 | 977 |
case 0xca00: /* xor #imm,R0 */ |
972 |
gen_op_xor_imm_rN(B7_0, REG(0));
|
|
978 |
tcg_gen_xori_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0);
|
|
973 | 979 |
return; |
974 | 980 |
case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
975 | 981 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
976 | 982 |
gen_op_addl_GBR_T0(); |
977 | 983 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
978 | 984 |
gen_op_ldub_T0_T0(ctx); |
979 |
gen_op_xor_imm_T0(B7_0);
|
|
985 |
tcg_gen_xori_i32(cpu_T[0], cpu_T[0], B7_0);
|
|
980 | 986 |
gen_op_stb_T0_T1(ctx); |
981 | 987 |
return; |
982 | 988 |
} |
... | ... | |
990 | 996 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
991 | 997 |
gen_op_ldl_T0_T0(ctx); |
992 | 998 |
tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]); |
993 |
gen_op_inc4_rN(REG(B11_8));
|
|
999 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
994 | 1000 |
return; |
995 | 1001 |
case 0x0082: /* stc Rm_BANK,Rn */ |
996 | 1002 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]); |
997 | 1003 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
998 | 1004 |
return; |
999 | 1005 |
case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
1000 |
gen_op_dec4_rN(REG(B11_8));
|
|
1006 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
1001 | 1007 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
1002 | 1008 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]); |
1003 |
gen_op_inc4_rN(REG(B11_8));
|
|
1009 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
1004 | 1010 |
gen_op_stl_T0_T1(ctx); |
1005 |
gen_op_dec4_rN(REG(B11_8));
|
|
1011 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
1006 | 1012 |
return; |
1007 | 1013 |
} |
1008 | 1014 |
|
... | ... | |
1051 | 1057 |
case ldpnum: \ |
1052 | 1058 |
tcg_gen_mov_i32 (cpu_T[0], cpu_gregs[REG(B11_8)]); \ |
1053 | 1059 |
gen_op_ldl_T0_T0 (ctx); \ |
1054 |
gen_op_inc4_rN (REG(B11_8)); \ |
|
1060 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], \ |
|
1061 |
cpu_gregs[REG(B11_8)], 4); \ |
|
1055 | 1062 |
gen_op_##ldop##_T0_##reg (); \ |
1056 | 1063 |
extrald \ |
1057 | 1064 |
return; \ |
... | ... | |
1061 | 1068 |
return; \ |
1062 | 1069 |
case stpnum: \ |
1063 | 1070 |
gen_op_##stop##_##reg##_T0 (); \ |
1064 |
gen_op_dec4_rN (REG(B11_8)); \ |
|
1071 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], \ |
|
1072 |
cpu_gregs[REG(B11_8)], 4); \ |
|
1065 | 1073 |
tcg_gen_mov_i32 (cpu_T[1], cpu_gregs[REG(B11_8)]); \ |
1066 |
gen_op_inc4_rN (REG(B11_8)); \ |
|
1074 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], \ |
|
1075 |
cpu_gregs[REG(B11_8)], 4); \ |
|
1067 | 1076 |
gen_op_stl_T0_T1 (ctx); \ |
1068 |
gen_op_dec4_rN (REG(B11_8)); \ |
|
1077 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], \ |
|
1078 |
cpu_gregs[REG(B11_8)], 4); \ |
|
1069 | 1079 |
return; |
1070 | 1080 |
LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->bstate = |
1071 | 1081 |
BS_STOP;) |
... | ... | |
1125 | 1135 |
gen_op_shlr_Rn(REG(B11_8)); |
1126 | 1136 |
return; |
1127 | 1137 |
case 0x4008: /* shll2 Rn */ |
1128 |
gen_op_shll2_Rn(REG(B11_8));
|
|
1138 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
|
1129 | 1139 |
return; |
1130 | 1140 |
case 0x4018: /* shll8 Rn */ |
1131 |
gen_op_shll8_Rn(REG(B11_8));
|
|
1141 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
1132 | 1142 |
return; |
1133 | 1143 |
case 0x4028: /* shll16 Rn */ |
1134 |
gen_op_shll16_Rn(REG(B11_8));
|
|
1144 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 16);
|
|
1135 | 1145 |
return; |
1136 | 1146 |
case 0x4009: /* shlr2 Rn */ |
1137 |
gen_op_shlr2_Rn(REG(B11_8));
|
|
1147 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
|
1138 | 1148 |
return; |
1139 | 1149 |
case 0x4019: /* shlr8 Rn */ |
1140 |
gen_op_shlr8_Rn(REG(B11_8));
|
|
1150 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
1141 | 1151 |
return; |
1142 | 1152 |
case 0x4029: /* shlr16 Rn */ |
1143 |
gen_op_shlr16_Rn(REG(B11_8));
|
|
1153 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 16);
|
|
1144 | 1154 |
return; |
1145 | 1155 |
case 0x401b: /* tas.b @Rn */ |
1146 | 1156 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
1147 | 1157 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
1148 | 1158 |
gen_op_ldub_T0_T0(ctx); |
1149 | 1159 |
gen_op_cmp_eq_imm_T0(0); |
1150 |
gen_op_or_imm_T0(0x80);
|
|
1160 |
tcg_gen_ori_i32(cpu_T[0], cpu_T[0], 0x80);
|
|
1151 | 1161 |
gen_op_stb_T0_T1(ctx); |
1152 | 1162 |
return; |
1153 | 1163 |
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
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